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1. 发明授权

US06791155B1 Stress-relieved shallow trench isolation (STI) structure and method for forming the same 有权
标题翻译：应力消除浅沟槽隔离（STI）结构及其形成方法
公开(公告)号：US06791155B1
公开(公告)日：2004-09-14
申请号：US10251550
申请日：2002-09-20
申请人： Guo-Qiang (Patrick) Lo , Brian Schorr , Gary Foley , Shih-Ked Lee
发明人： Guo-Qiang (Patrick) Lo , Brian Schorr , Gary Foley , Shih-Ked Lee
IPC分类号： H01L2176
CPC分类号： H01L21/764 , H01L21/76224
摘要： A shallow trench isolation (STI) structure in a semiconductor substrate and a method for forming the same are provided. A trench is formed in a semiconductor substrate. A first dielectric layer is formed on sidewalls of the trench. The first dielectric layer is formed thicker at a top portion of the sidewalls than a bottom portion of the sidewalls and leaving an entrance of the trench open to expose the trench. A second dielectric layer is conformally formed on the first dielectric layer to close the entrance, thus forming a void buried within the trench. Thus, the stress between the trench dielectric layer and the surrounding silicon substrate during thermal cycling can be substantially reduced.
摘要翻译：提供半导体衬底中的浅沟槽隔离（STI）结构及其形成方法。在半导体衬底中形成沟槽。第一电介质层形成在沟槽的侧壁上。第一电介质层在侧壁的顶部处形成得比侧壁的底部更厚，并且使沟槽的入口敞开以暴露沟槽。在第一电介质层上共形形成第二电介质层以封闭入口，从而形成埋在沟槽内的空隙。因此，可以显着地减少在热循环期间沟槽电介质层和周围硅衬底之间的应力。

2. 发明授权

US07015116B1 Stress-relieved shallow trench isolation (STI) structure and method for forming the same 有权
标题翻译：应力消除浅沟槽隔离（STI）结构及其形成方法
公开(公告)号：US07015116B1
公开(公告)日：2006-03-21
申请号：US10897601
申请日：2004-07-23
申请人： Guo-Qiang (Patrick) Lo , Brian Schorr , Gary Foley , Shih-Ked Lee
发明人： Guo-Qiang (Patrick) Lo , Brian Schorr , Gary Foley , Shih-Ked Lee
IPC分类号： H01L21/76
CPC分类号： H01L21/764 , H01L21/76224
摘要： A shallow trench isolation (STI) structure in a semiconductor substrate and a method for forming the same are provided. A trench is formed in a semiconductor substrate. A first dielectric layer is formed on sidewalls of the trench. The first dielectric layer is formed thicker at a top portion of the sidewalls than a bottom portion of the sidewalls and leaving an entrance of the trench open to expose the trench. A second dielectric layer is conformally formed on the first dielectric layer to close the entrance, thus forming a void buried within the trench. Thus, the stress between the trench dielectric layer and the surrounding silicon substrate during thermal cycling can be substantially reduced.
摘要翻译：提供半导体衬底中的浅沟槽隔离（STI）结构及其形成方法。在半导体衬底中形成沟槽。第一电介质层形成在沟槽的侧壁上。第一电介质层在侧壁的顶部处形成得比侧壁的底部更厚，并且使沟槽的入口敞开以暴露沟槽。在第一电介质层上共形形成第二电介质层以封闭入口，从而形成埋在沟槽内的空隙。因此，可以显着地减少在热循环期间沟槽电介质层和周围硅衬底之间的应力。

3. 发明授权

US06627543B1 Low-temperature sputtering system and method for salicide process 失效
标题翻译：低温溅射系统和自杀剂方法
公开(公告)号：US06627543B1
公开(公告)日：2003-09-30
申请号：US09564304
申请日：2000-05-03
申请人： Wanqing Cao , Guo-Qiang Patrick Lo , Shih-Ked Lee , Robert B. Hixson , Eric S. Lee
发明人： Wanqing Cao , Guo-Qiang Patrick Lo , Shih-Ked Lee , Robert B. Hixson , Eric S. Lee
IPC分类号： H01L2144
CPC分类号： H01L21/28518 , H01L21/2855
摘要： Disclosed are methods and systems for forming salicide, in which a semiconductor substrate is provided with at least one exposed silicon surface. The semiconductor substrate is placed into a sputtering chamber. A silicide-forming metal layer, formed of a metal such as Co, Ni, is sputter-deposited over the exposed silicon surface. A process temperature is controlled below room temperature during the sputter deposition and preferably between approximately 0° C. to 10° C. The silicide-forming metal layer formed on the exposed silicon surface is first annealed to convert the silicide-forming metal layer into a salicide layer. Also, the system of the present invention is comprised of a sputter chamber including a mount for mounting a semiconductor substrate and a cooling mechanism coupled with the mount for cooling the semiconductor substrate. The cooling mechanism includes a controller to maintain a process temperature below room temperature. Improved device characteristics such as increased charge-to-breakdown can be achieved in the devices according to the present invention compared to the devices with high-temperature sputtered salicide.
摘要翻译：公开了用于形成硅化物的方法和系统，其中半导体衬底设置有至少一个暴露的硅表面。将半导体衬底放置在溅射室中。由诸如Co，Ni的金属形成的硅化物形成金属层溅射沉积在暴露的硅表面上。在溅射沉积期间将工艺温度控制在室温以下，优选在约0℃至10℃之间。形成在暴露的硅表面上的硅化物形成金属层首先退火，以将硅化物形成金属层转变为自杀层而且，本发明的系统包括一个包括一个用于安装一个半导体衬底的安装座和一个冷却机构的溅射室，该冷却机构与用于冷却半导体衬底的安装座相连。冷却机构包括将工艺温度保持在室温以下的控制器。与具有高温溅射的自对准硅化物的装置相比，在根据本发明的装置中可以实现改进的装置特性，例如增加的电荷到击穿电压。

4. 发明授权

US06407008B1 Method of forming an oxide layer 失效
标题翻译：形成氧化物层的方法
公开(公告)号：US06407008B1
公开(公告)日：2002-06-18
申请号：US09564786
申请日：2000-05-05
申请人： Yingbo Jia , Ohm-Guo Pan , Long-Ching Wang , Jeong Yeol Choi , Guo-Qiang (Patrick) Lo , Shih-Ked Lee
发明人： Yingbo Jia , Ohm-Guo Pan , Long-Ching Wang , Jeong Yeol Choi , Guo-Qiang (Patrick) Lo , Shih-Ked Lee
IPC分类号： H01L21314
CPC分类号： H01L21/28202 , C23C8/10 , C30B29/06 , C30B33/005 , H01L21/3144 , H01L21/31658 , H01L29/518
摘要： Methods for forming nitrided oxides in semiconductor devices by rapid thermal oxidation, in which a semiconductor substrate having an exposed silicon surface is placed into a thermal process chamber. Then, an ambient gas comprising N2O and an inert gas such as argon or N2 is introduced into the process chamber. Next, the silicon surface is heated to a predefined process temperature, thereby oxidizing at least a portion of the silicon surface. Finally, the semiconductor substrate is cooled. An ultra-thin oxide layer with uniform oxide characteristics, such as more boron penetration resistance, good oxide composition and thickness uniformity, increased charge to breakdown voltage in the oxide layer, can be formed.
摘要翻译：通过快速热氧化在半导体器件中形成氮化氧化物的方法，其中具有暴露的硅表面的半导体衬底被放置在热处理室中。然后，将包含N 2 O和惰性气体如氩气或N 2的环境气体引入处理室。接下来，将硅表面加热到预定的工艺温度，从而氧化硅表面的至少一部分。最后，冷却半导体衬底。可以形成具有均匀氧化特性的超薄氧化物层，例如更多的硼渗透阻力，良好的氧化物组成和厚度均匀性，增加氧化物层中的电荷到击穿电压。

5. 发明授权

US5767558A Structures for preventing gate oxide degradation 失效
标题翻译：防止栅极氧化物降解的结构
公开(公告)号：US5767558A
公开(公告)日：1998-06-16
申请号：US644468
申请日：1996-05-10
申请人： Guo-Qiang (Patrick) Lo , Shih-Ked Lee
发明人： Guo-Qiang (Patrick) Lo , Shih-Ked Lee
IPC分类号： H01L21/28 , H01L29/49 , H01L29/76 , H01L23/48
CPC分类号： H01L21/28061 , H01L29/4933
摘要： The degradation of integrity of the gate oxide in a CMOS transistor due to the formation of a tungsten silicide strapping layer on the polycrystalline silicon gate as a result of the migration of fluorine atoms from the tungsten hexafluoride used to form the tungsten silicide is reduced by increasing the dopant concentration of the polycrystalline silicon layer thereby to form dopant atoms in the grain boundaries of the polycrystalline silicon to block the migration of fluorine through the polycrystalline silicon to the underlying gate oxide. By preventing fluorine from reaching the gate oxide in this manner, the degradation of the gate oxide due to the replacement of oxygen by fluorine is decreased. The method maintains the gate-oxide integrity (such as charge-to-breakdown characteristics), and the method also makes more predictable the performance of the resulting transistors by reducing the thickening of the oxide due to the migration of oxygen replaced by fluorine into the underlying silicon substrate thereby to form additional silicon oxide. The polysilicon thus preserves the gate oxide integrity. In addition, the heavily-doped polysilicon will also sufficiently dope the contacted polysilicon and thus reduce the contact resistance of the polycrystalline silicon and silicon.
摘要翻译：由于由用于形成硅化钨的六氟化钨的氟原子的迁移导致在多晶硅栅极上形成硅化钨夹层而导致的CMOS晶体管中的栅极氧化物的完整性的劣化通过增加多晶硅层的掺杂剂浓度从而在多晶硅的晶界中形成掺杂剂原子，以阻止氟通过多晶硅迁移到下面的栅极氧化物。通过防止氟以这种方式到达栅极氧化物，由于由氟代替氧而导致的栅极氧化物的降解降低。该方法保持栅氧化物的完整性（例如电荷到击穿特性），并且该方法还通过减少氧被氟取代的氧的迁移而减小氧化物的增厚而使得所得晶体管的性能更可预测从而形成额外的氧化硅。因此，多晶硅保持了栅极氧化物的完整性。此外，重掺杂多晶硅还将充分掺杂接触的多晶硅，从而降低多晶硅和硅的接触电阻。

6. 发明授权

US06566236B1 Gate structures with increased etch margin for self-aligned contact and the method of forming the same 失效
标题翻译：具有增加的用于自对准接触的蚀刻余量的栅极结构及其形成方法
公开(公告)号：US06566236B1
公开(公告)日：2003-05-20
申请号：US09558941
申请日：2000-04-26
申请人： Tsengyou Syau , Guo-Qiang (Patrick) Lo , Shih-Ked Lee , Chuen-Der Lien , Sang-Yun Lee , Ching-Kai (Robert) Lin
发明人： Tsengyou Syau , Guo-Qiang (Patrick) Lo , Shih-Ked Lee , Chuen-Der Lien , Sang-Yun Lee , Ching-Kai (Robert) Lin
IPC分类号： H01L213205
CPC分类号： H01L21/76897 , H01L21/28061 , H01L21/28114 , H01L21/32137
摘要： A novel gate structure and a method of forming the same for a self-aligned contact on a semiconductor substrate. The method includes forming a gate oxide layer on the semiconductor substrate. Then a first conductive layer is formed on the gate oxide layer. Next, a second conductive layer, preferably a refractory metal silicide (e.g. WSix), is formed overlying the first conductive layer. A capping layer is formed overlying the second conductive layer. Then the capping layer is etched to form a patterned capping layer having a lower outside corner. An upper portion of the second conductive layer is selectively dry etched laterally to form a lateral recess under the capping layer to increase etch margin. A lower portion of the second conductive layer is then etched anisotropically down to the first conductive layer along a sidewall approximately vertically aligned with the lower outside corner of the patterned capping layer. The recess has an inward extant from the lower outside corner in a range of between 100-300 Angstroms. Increased etch margin is provided in the gate structure to prevent shorts between contact plugs and gate structures during contact formation.
摘要翻译：一种新颖的栅极结构及其在半导体衬底上形成自对准接触的方法。该方法包括在半导体衬底上形成栅氧化层。然后在栅极氧化物层上形成第一导电层。接下来，形成第二导电层，优选难熔金属硅化物（例如WSix），覆盖在第一导电层上。形成覆盖在第二导电层上的覆盖层。然后对覆盖层进行蚀刻以形成具有较低外角的图案化覆盖层。第二导电层的上部被横向选择性干蚀刻以在覆盖层下方形成横向凹槽以增加蚀刻余量。然后，第二导电层的下部沿着与图案化覆盖层的下部外角大致垂直对准的侧壁各向异性地蚀刻到第一导电层。该凹陷部位在下外角处具有介于100-300埃之间的范围内。在栅极结构中提供增加的蚀刻余量以防止接触形成期间接触插塞和栅极结构之间的短路。

7. 发明授权

US6093589A Methods for preventing gate oxide degradation 失效
标题翻译：防止栅极氧化物降解的方法
公开(公告)号：US6093589A
公开(公告)日：2000-07-25
申请号：US928429
申请日：1997-09-12
申请人： Guo-Qiang (Patrick) Lo , Shih-Ked Lee
发明人： Guo-Qiang (Patrick) Lo , Shih-Ked Lee
IPC分类号： H01L21/28 , H01L29/49 , H01L21/336 , H01L21/3205
CPC分类号： H01L21/28061 , H01L29/4933
摘要： The degradation of integrity of the gate oxide in a CMOS transistor due to the formation of a tungsten silicide strapping layer on the polycrystalline silicon gate as a result of the migration of fluorine atoms from the tungsten hexafluoride used to form the tungsten silicide is reduced by increasing the dopant concentration of the polycrystalline silicon layer thereby to form dopant atoms in the grain boundaries of the polycrystalline silicon to block the migration of fluorine through the polycrystalline silicon to the underlying gate oxide. By preventing fluorine from reaching the gate oxide in this manner, the degradation of the gate oxide due to the replacement of oxygen by fluorine is decreased. The method maintains the gate-oxide integrity (such as charge-to-breakdown characteristics), and the method also makes more predictable the performance of the resulting transistors by reducing the thickening of the oxide due to the migration of oxygen replaced by fluorine into the underlying silicon substrate thereby to form additional silicon oxide. The polysilicon thus preserves the gate oxide integrity. In addition, the heavily-doped polysilicon will also sufficiently dope the contacted polysilicon and thus reduce the contact resistance of the polycrystalline silicon and silicon.
摘要翻译：由于由用于形成硅化钨的六氟化钨的氟原子的迁移导致在多晶硅栅极上形成硅化钨夹层而导致CMOS晶体管中的栅极氧化物的完整性的劣化通过增加多晶硅层的掺杂剂浓度从而在多晶硅的晶界中形成掺杂剂原子，以阻止氟通过多晶硅迁移到下面的栅极氧化物。通过防止氟以这种方式到达栅极氧化物，由于由氟代替氧而导致的栅极氧化物的降解降低。该方法保持栅极氧化物的完整性（例如电荷到击穿特性），并且该方法还通过减少氧被氟取代的氧的迁移而减小氧化物的增厚而使得所得晶体管的性能更可预测从而形成额外的氧化硅。因此，多晶硅保持了栅极氧化物的完整性。此外，重掺杂多晶硅还将充分掺杂接触的多晶硅，从而降低多晶硅和硅的接触电阻。

8. 发明授权

US07400026B2 Thin film resistor structure 有权
标题翻译：薄膜电阻器结构
公开(公告)号：US07400026B2
公开(公告)日：2008-07-15
申请号：US11342134
申请日：2006-01-26
申请人： Gaolong Jin , Wanqing Cao , Guo-Qiang Lo , Shih-Ked Lee
发明人： Gaolong Jin , Wanqing Cao , Guo-Qiang Lo , Shih-Ked Lee
IPC分类号： H01L29/00
CPC分类号： H01L28/24 , H01L27/016 , H01L27/0802 , H01L29/78
摘要： The present invention relates to a thin film resistor formed over a semiconductor substrate. A gate structure is formed and a dielectric layer is formed over the gate structure. A via is then etched that extends through the dielectric layer so as to expose a conductive layer of the gate structure. A layer of titanium nitride is deposited and a rapid thermal anneal is performed in an oxygen ambient. The rapid thermal anneal incorporates oxygen into the titanium nitride, forming titanium oxynitride film. A layer of dielectric material is then deposited and etched-back to form a dielectric plug that fills the remaining portion of the via. The titanium oxynitride film is patterned to form a titanium oxynitride structure that is electrically coupled to the gate structure.
摘要翻译：本发明涉及形成在半导体衬底上的薄膜电阻器。形成栅极结构，并且在栅极结构上形成介电层。然后蚀刻通孔，其延伸穿过电介质层，以暴露栅极结构的导电层。沉积一层氮化钛，并在氧气氛中进行快速热退火。快速热退火将氧气纳入氮化钛中，形成氮氧化钛膜。然后沉积介电材料层并将其蚀刻回来形成填充通孔的剩余部分的电介质塞子。将氮氧化钛膜图案化以形成电耦合到栅极结构的氮氧化钛结构。

9. 发明授权

US07078306B1 Method for forming a thin film resistor structure 失效
标题翻译：用于形成薄膜电阻器结构的方法
公开(公告)号：US07078306B1
公开(公告)日：2006-07-18
申请号：US10805718
申请日：2004-03-22
申请人： Gaolong Jin , Wanqing Cao , Guo-Qiang Lo , Shih-Ked Lee
发明人： Gaolong Jin , Wanqing Cao , Guo-Qiang Lo , Shih-Ked Lee
IPC分类号： H01L21/20
CPC分类号： H01L28/24 , H01L27/016 , H01L27/0802 , H01L29/78
摘要： The present invention relates to a method for forming a thin film resistor and a thin film resistor formed over a semiconductor substrate. A gate structure is formed and a dielectric layer is formed over the gate structure. A via is then etched that extends through the dielectric layer so as to expose a portion of the gate structure. A layer of titanium nitride is deposited using a chemical vapor deposition process. A rapid thermal anneal is performed in an oxygen ambient. The rapid thermal anneal incorporates oxygen into the titanium nitride, forming titanium oxynitride film. A layer of dielectric material is then deposited and etched-back to form a dielectric plug that fills the remaining portion of the via. The titanium oxynitride film is patterned to form a titanium oxynitride structure that is electrically coupled to the gate structure. A metal layer is deposited and patterned to form an interconnect structure that electrically couples the titanium oxynitride structure to other circuitry.
摘要翻译：本发明涉及形成在半导体衬底上的薄膜电阻器和薄膜电阻器的形成方法。形成栅极结构，并且在栅极结构上形成介电层。然后蚀刻通孔，其延伸穿过电介质层，以暴露栅极结构的一部分。使用化学气相沉积工艺沉积一层氮化钛。在氧环境中进行快速热退火。快速热退火将氧气纳入氮化钛中，形成氮氧化钛膜。然后沉积介电材料层并将其蚀刻回来形成填充通孔的剩余部分的电介质塞子。将氮氧化钛膜图案化以形成电耦合到栅极结构的氮氧化钛结构。金属层被沉积并图案化以形成将氮氧化钛结构电耦合到其它电路的互连结构。

10. 发明申请

US20060118910A1 Thin film resistor structure 有权
标题翻译：薄膜电阻器结构
公开(公告)号：US20060118910A1
公开(公告)日：2006-06-08
申请号：US11342134
申请日：2006-01-26
申请人： Gaolong Jin , Wanqing Cao , Guo-Qiang Lo , Shih-Ked Lee
发明人： Gaolong Jin , Wanqing Cao , Guo-Qiang Lo , Shih-Ked Lee
IPC分类号： H01L29/00
CPC分类号： H01L28/24 , H01L27/016 , H01L27/0802 , H01L29/78
摘要： The present invention relates to a thin film resistor formed over a semiconductor substrate. A gate structure is formed and a dielectric layer is formed over the gate structure. A via is then etched that extends through the dielectric layer so as to expose a conductive layer of the gate structure. A layer of titanium nitride is deposited A and a rapid thermal anneal is performed in an oxygen ambient. The rapid thermal anneal incorporates oxygen into the titanium nitride, forming titanium oxynitride film. A layer of dielectric material is then deposited and etched-back to form a dielectric plug that fills the remaining portion of the via. The titanium oxynitride film is patterned to form a titanium oxynitride structure that is electrically coupled to the gate structure.
摘要翻译：本发明涉及形成在半导体衬底上的薄膜电阻器。形成栅极结构，并且在栅极结构上形成介电层。然后蚀刻通孔，其延伸穿过电介质层，以暴露栅极结构的导电层。淀积一层氮化钛，并在氧气氛中进行快速热退火。快速热退火将氧气纳入氮化钛中，形成氮氧化钛膜。然后沉积介电材料层并将其蚀刻回来形成填充通孔的剩余部分的电介质塞子。将氮氧化钛膜图案化以形成电耦合到栅极结构的氮氧化钛结构。

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