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    • 1. 发明授权
    • EPROM circuit with error correction
    • EPROM电路具有纠错功能
    • US06201762B1
    • 2001-03-13
    • US09593964
    • 2000-06-15
    • Shigenori YamauchiSeiki Aoyama
    • Shigenori YamauchiSeiki Aoyama
    • G11C1600
    • G11C16/26
    • To correct an unintentionally erasing error in an EPROM circuit, in accordance with the same one-bit data, each of first and second EPROM cells is either unprogrammed to output a first logic value representing an unprogrammed condition when reading or programmed to output a second logic value representing a programmed condition when reading. A logic operation gate outputs the first logic value when both the first and second EPROM cells output the first logic value and outputting the second logic value when at least one of the first and second EPROM cells output the second logic value. To correct unintentionally writing error in an N-bit EPROM circuit, a first parity is stored and a second parity is detected from N logic operation gates. If the first parity disagrees with the second parity, a correction signal is generated. In the presence of the correction signal, when it is detected at each of N-bit that an output of the first EPROM cell disagrees with that of the second one, an inverted output of the logic operation gate at the bit instead the output of the logic operation gate.
    • 为了纠正EPROM电路中的无意擦除错误,根据相同的一位数据,当读取或编程为输出第二逻辑时,第一和第二EPROM单元中的每一个未被编程以输出表示未编程状态的第一逻辑值 表示读取时的编程状态的值。 当第一和第二EPROM单元都输出第一逻辑值时,逻辑运算门输出第一逻辑值,并且当第一和第二EPROM单元中的至少一个输出第二逻辑值时输出第二逻辑值。 为了纠正在N位EPROM电路中的无意写入错误,存储第一奇偶校验,并从N个逻辑运算门检测第二奇偶校验。 如果第一奇偶校验与第二奇偶校验不一致,则产生校正信号。 在存在校正信号的情况下,当在每个N位检测到第一EPROM单元的输出与第二EPROM单元的输出不一致时,逻辑运算门的反相输出而不是输出 逻辑运算门
    • 2. 发明授权
    • Physical quantity detecting device
    • 物理量检测装置
    • US6082196A
    • 2000-07-04
    • US845895
    • 1997-04-28
    • Shigeru NonoyamaShigenori YamauchiTakamoto Watanabe
    • Shigeru NonoyamaShigenori YamauchiTakamoto Watanabe
    • G01D5/24G01P15/125G01P15/13G01P15/14
    • G01P15/131G01P15/125
    • A physical quantity detecting is capable of easily adjusting sensitivity and an offset of a detected output without being increased in size. In a signal processor for driving a sensor element in which fixed electrodes are disposed on both sides of a movable electrode displaced in response to acceleration, a signal generator generates PWM signals PA and PB in which an invalid control period during which the fixed electrodes are both deenergized only during a period corresponding to data M3 stored in a memory, is, at a predetermined ratio, inserted into a valid control period during which the fixed electrodes are alternately energized and their energization ratio is controlled so that the movable electrode is placed in position. Since the sensitivity of the sensor element to the acceleration changes according to the length of the invalid control period which does not contribute to control of the position of the movable electrode, its sensitivity can be easily adjusted by simply changing the value set in the memory.
    • 物理量检测能够容易地调节灵敏度和检测输出的偏移而不增大尺寸。 在用于驱动传感器元件的信号处理器中,其中固定电极设置在响应于加速度而移位的可移动电极的两侧,信号发生器产生PWM信号PA和PB,其中固定电极均为无效控制周期 仅在对应于存储在存储器中的数据M3的周期期间被断电,以预定比例插入到固定电极交替通电的有效控制周期中,并且控制其通电率,使得可动电极位于 。 由于传感器元件对加速度的灵敏度根据无效控制周期的长度而变化,这对于可移动电极的位置的控制无助于其灵敏度,因此可以通过简单地改变在存储器中设置的值来容易地调整灵敏度。
    • 3. 发明授权
    • Programmable delay line programmable delay circuit and digital
controlled oscillator
    • 可编程延迟线可编程延迟电路和数字控制振荡器
    • US5465076A
    • 1995-11-07
    • US111488
    • 1993-08-25
    • Shigenori YamauchiTakamoto Watanabe
    • Shigenori YamauchiTakamoto Watanabe
    • H03K3/03H03K5/135H03L7/099H03B28/00H03K5/14H03K5/159
    • H03K5/135H03K3/0315H03L7/0996H03L7/0997
    • A programmable delay line comprises a plurality of delay stages connected in series, each of the delay stages including: a basic path for passing an input signal; a delay path for passing the input signal with a predetermined delay time; and a selector for selecting either the basic path or the delay path to pass the input signal in accordance with digital data externally inputted, wherein differences in times for passing the input signal through the basic path and through the delay path in the plurality delay stages are UD.2.sup.n (n=0, 1, 2 . . . ), UD being unit delay time. A programmable delay apparatus comprises: an oscillator and counter, which determine a coarse delay time in accordance with the upper bit data of control data, and a programmable delay line, which determines a fine delay time according to the lower bit data of the control data after the finish of the coarse delay time to obtain a total delay time. The counter provides a wide range of available delay times. The oscillator of the programmable delay apparatus can be controlled by a control signal. Addition of a feedback circuit for supplying the delay signal from the delay line as the control signal to the oscillator of the programmable delay apparatus provides a digital controlled oscillator.
    • 可编程延迟线包括串联连接的多个延迟级,每个延迟级包括:用于传递输入信号的基本路径; 用于以预定的延迟时间传递输入信号的延迟路径; 以及选择器,用于选择基本路径或延迟路径以根据外部输入的数字数据传递输入信号,其中通过基本路径的输入信号和通过多个延迟级中的延迟路径的时间差为 UD.2n(n = 0,1,2,...),UD为单位延迟时间。 一种可编程延迟装置包括:振荡器和计数器,其根据控制数据的高位数据确定粗延迟时间;以及可编程延迟线,其根据控制数据的较低位数据确定精细延迟时间 完成粗延时后获得总延迟时间。 该计数器提供广泛的可用延迟时间。 可编程延迟装置的振荡器可以通过控制信号来控制。 添加用于将来自延迟线的延迟信号作为控制信号提供给可编程延迟装置的振荡器的反馈电路提供数字控制振荡器。
    • 4. 发明授权
    • Ring oscillator and pulse phase difference encoding circuit
    • 环形振荡器和脉冲相位差编码电路
    • US5416444A
    • 1995-05-16
    • US177682
    • 1994-01-05
    • Shigenori YamauchiTakamoto WatanabeYoshinori Ohtsuka
    • Shigenori YamauchiTakamoto WatanabeYoshinori Ohtsuka
    • G01R25/08H03K3/03H03K5/13H03B5/00
    • H03K3/0315G01R25/08H03K5/131Y10S331/03
    • A ring oscillator for circulating pulse edges of two types therein includes an even number of inverting circuits connected in a ring. Each of the inverting circuits is operative to invert an input signal and output an inversion of the input signal. One of the inverting circuits is a first start inverting circuit which starts an operation of inverting an input signal in response to a first control signal applied from an external input. One of the inverting circuits except the first start inverting circuit and an inverting circuit immediately following the first start inverting circuit is a second start inverting circuit which starts an operation of inverting an input signal in response to a second control signal. A control signal inputting arrangement serves to input the second control signal to the second start inverting circuit during an interval from a first moment at which the first control signal is inputted into the first start inverting circuit and the first start inverting circuit starts the inverting operation to a second moment at which a pulse edge initially generated by the start of the inverting operation of the first start inverting circuit and travelling while being sequentially inverted by the inverting circuits enters the second start inverting circuit.
    • 用于循环两种类型的脉冲边缘的环形振荡器包括以环形连接的偶数反相电路。 每个反相电路用于反转输入信号并输出​​输入信号的反相。 反相电路中的一个是第一启动反相电路,其响应于从外部输入施加的第一控制信号开始反相输入信号的操作。 除了第一启动反相电路和紧接在第一启动反相电路之后的反相电路之一的反相电路中的一个是响应于第二控制信号开始反相输入信号的操作的第二启动反相电路。 控制信号输入装置用于在从第一控制信号被输入到第一起动反向电路的第一时刻开始间隔期间将第二控制信号输入到第二启动反转电路,并且第一启动反相电路开始转换操作 第二时刻,由第一起动反转电路的反相操作开始初始产生的脉冲沿并且由反相电路顺序反转的第二时刻进入第二启动反相电路。
    • 10. 发明授权
    • Digitization apparatus
    • 数字化装置
    • US07450049B2
    • 2008-11-11
    • US11803392
    • 2007-05-14
    • Shigenori YamauchiTakamoto Watanabe
    • Shigenori YamauchiTakamoto Watanabe
    • H03M1/60
    • H03M1/206H03M1/14H03M1/502H03M1/60
    • The digitization apparatus includes, as a main scale, a pulse delay circuit constituted by a plurality of delay units connected in series or in ring form, a latch/encoder, a circulation number counter, and a latch circuit, and includes, as a vernier, a reverse timing extraction circuit detecting a reverse timing at which any one of the delay units has reversed, and an interpolation circuit. The main scale digitizes a time interval between two successive measurement signals in a resolution equal to a delay time per one delay unit. The vernier digitizes a time difference between a measurement timing indicated by the measurement signal and the reverse timing in a resolution equal to 1/M (M being an integer not smaller than 2). The interpolation circuit includes two delay lines each constituted by a plurality of delay units connected in series or in ring form.
    • 数字化装置包括作为主要尺度的由串联或环形连接的多个延迟单元,锁存/编码器,循环号计数器和锁存电路构成的脉冲延迟电路,并且包括作为游标 检测任一个延迟单元已经反转的反向定时的反向定时提取电路和内插电路。 主比例数字化两个连续的测量信号之间的时间间隔,其分辨率等于每个延迟单元的延迟时间。 游标数字化测量信号所示的测量定时与反向定时之间的时差,其分辨率等于1 / M(M为不小于2的整数)。 插补电路包括两个延迟线,每条延迟线由串联或环形连接的多个延迟单元构成。