专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07078998B2 Via/line inductor on semiconductor material 有权
标题翻译：半导体材料上的通/线电感
公开(公告)号：US07078998B2
公开(公告)日：2006-07-18
申请号：US10754973
申请日：2004-01-09
申请人： Jiong Zhang , Yi Min Wang , Shao-fu Sanford Chu
发明人： Jiong Zhang , Yi Min Wang , Shao-fu Sanford Chu
IPC分类号： H01F5/00
CPC分类号： H01L28/10 , H01L27/08 , Y10T29/4902
摘要： A spiral inductor is provided including a substrate and an inductor dielectric layer over the substrate having a spiral opening provided therein. The spiral inductor is in the spiral opening with the spiral inductor including a plurality of parallel spiral vias connected together at center proximate and center distal ends of the spiral inductor.
摘要翻译：提供螺旋电感器，其包括衬底和在其上设置有螺旋开口的衬底上的电感器电介质层。螺旋电感器处于螺旋形开口中，螺旋电感器包括在螺旋电感器的中心近端和中心远端处连接在一起的多个平行螺旋通孔。

2. 发明授权

US06297132B1 Process to control the lateral doping profile of an implanted channel region 有权
标题翻译：控制植入通道区域的横向掺杂分布的方法
公开(公告)号：US06297132B1
公开(公告)日：2001-10-02
申请号：US09498978
申请日：2000-02-07
申请人： Jiong Zhang , Kai Shao , Shao-Fu Sanford Chu
发明人： Jiong Zhang , Kai Shao , Shao-Fu Sanford Chu
IPC分类号： H01L21425
CPC分类号： H01L29/66537 , H01L29/66553 , H01L29/6659 , H01L29/7833
摘要： A process for fabricating a MOSFET device, featuring a narrow lateral delta doping, or a narrow anti-punchthrough region, located in the center of the MOSFET channel region, has been developed. The process features formation of the narrow, anti-punchthrough region, via use of an ion implantation procedure, performed using an opening, comprised with sidewall spacers, as an implant mask. After formation of the narrow, anti-punchthrough region, the sidewall spacers are removed, and a gate insulator layer, and a polysilicon gate structure, are formed in the spacerless opening, defining a channel region wider than the narrow, anti-punchthrough region.
摘要翻译：已经开发了一种制造MOSFET器件的工艺，其具有窄的侧向delta掺杂或位于MOSFET沟道区域的中心的窄反穿通区域。该方法的特征在于，通过使用离子注入程序，使用包括侧壁间隔件的开口作为植入物掩模来执行窄的抗穿透区域的形成。在形成窄的防穿透区域之后，去除侧壁间隔物，并且在无间隔开口中形成栅极绝缘体层和多晶硅栅极结构，限定比窄的反穿通区域宽的沟道区域。

3. 发明授权

US06300201B1 Method to form a high K dielectric gate insulator layer, a metal gate structure, and self-aligned channel regions, post source/drain formation 有权
标题翻译：形成高K介质栅极绝缘体层，金属栅极结构和自对准沟道区的方法，形成源极/漏极
公开(公告)号：US06300201B1
公开(公告)日：2001-10-09
申请号：US09523992
申请日：2000-03-13
申请人： Kai Shao , Jiong Zhang , Qing Hua Zhang , Yi Min Wang , Sanford Shao Fu Chu
发明人： Kai Shao , Jiong Zhang , Qing Hua Zhang , Yi Min Wang , Sanford Shao Fu Chu
IPC分类号： H01L21336
CPC分类号： H01L29/495 , H01L21/28079 , H01L21/28167 , H01L21/28194 , H01L21/28202 , H01L21/8238 , H01L29/517 , H01L29/518 , H01L29/66537 , H01L29/66545 , H01L29/6659 , H01L29/7833
摘要： A process of fabricating a sub-micron MOSFET device, featuring a high dielectric constant gate insulator layer, and a metal gate structure, has been developed. Processes performed at temperatures detrimental to the high dielectric, gate insulator layer, such as formation of spacers on the sides of subsequent gate structures, as well as formation of source/drain regions, are introduced prior to the formation of the high dielectric, gate insulator layer. This is accomplished via use of a dummy gate structure, comprised of silicon nitride, used as a mask to define the source/drain regions, and used as the structure in which sidewall spacers are formed on. After selective removal of the dummy gate structure, creating an opening in an interlevel dielectric layer exposing the MOSFET channel region, deposition of the high dielectric, gate insulator layer, on the surface of the MOSFET channel region, is performed.
摘要翻译：已经开发了制造具有高介电常数栅极绝缘体层和金属栅极结构的亚微米MOSFET器件的工艺。在形成高电介质栅极绝缘体之前，引入在高电介质栅极绝缘体层有害的温度下进行的工艺，例如在随后的栅极结构的侧面上形成间隔物，以及形成源极/漏极区域层。这是通过使用由氮化硅组成的虚拟栅极结构来实现的，该栅极结构用作掩模以限定源极/漏极区域，并且用作其中形成侧壁间隔物的结构。在选择性地去除虚拟栅极结构之后，在暴露MOSFET沟道区的层间电介质层中形成开口，进行在MOSFET沟道区的表面上沉积高电介质栅极绝缘体层。

4. 发明授权

US07022475B2 Genotyping assay to predict CYP3A5 phenotype 有权
公开(公告)号：US07022475B2
公开(公告)日：2006-04-04
申请号：US09974619
申请日：2001-10-10
申请人： Erin Schuetz , Jiong Zhang , Mahfoud Assem
发明人： Erin Schuetz , Jiong Zhang , Mahfoud Assem
IPC分类号： C12Q1/68 , C12P19/34 , C07H21/04
CPC分类号： C12Q1/6886 , C12Q2600/156 , Y02A90/26
摘要： Genetic polymorphisms responsible or associated with altered expression of cytochrome P450 CYP3A5 enzyme are described. Single nucleotide polymorphisms are provided. Methods for identifying subjects having a low or high drug metabolizing phenotype associated with CYP3A5 expression are provided. Assays, kits and methods for determining and assaying the CYP3A5 genotype and phenotype of individual patients are disclosed. Oligonucleotide probes and primers for use in the assays, kits and methods are described. Assays and methods for determining and evaluating an individual's metabolism of drugs and therapeutic agents, the potential for drug interactions, and thereby toxicity and effectiveness of certain drugs and treatment modalities, are provided.

5. 发明申请

US20070034960A1 ESD protection structure using contact-via chains as ballast resistors 有权
标题翻译：使用接触通道链作为镇流电阻的ESD保护结构
公开(公告)号：US20070034960A1
公开(公告)日：2007-02-15
申请号：US11201638
申请日：2005-08-10
申请人： Jiong Zhang , Yuhua Cheng
发明人： Jiong Zhang , Yuhua Cheng
IPC分类号： H01L23/62
CPC分类号： H01L27/0266 , H01L27/0629 , H01L29/0692 , H01L29/41725 , H01L29/41758 , H01L29/78 , H01L2924/0002 , H01L2924/00
摘要： According to an exemplary embodiment, an ESD protection structure situated in a semiconductor die includes a FET including a gate and first and second active regions, where the gate includes at least one gate finger, and where the at least one gate finger is situated between the first and second active regions. The ESD protection structure further includes at least one contact-via chain connected to the first active region, where the at least one contact-via chain includes a contact connected to a via. The at least one contact-via chain forms a ballast resistor for increased ESD current distribution uniformity. The contact is connected to the via by a first metal segment situated in a first interconnect metal layer of a die. The at least one contact-via chain is connected between the first active region and a second metal segment situated in a second interconnect metal layer of the die.
摘要翻译：根据示例性实施例，位于半导体管芯中的ESD保护结构包括包括栅极和第一和第二有源区的FET，其中栅极包括至少一个栅极指，并且其中至少一个栅极指位于第一和第二活跃区域。 ESD保护结构还包括连接到第一有源区的至少一个接触通孔链，其中至少一个接触通孔链包括连接到通孔的触点。所述至少一个接触通孔链形成用于增加ESD电流分布均匀性的镇流电阻器。触点通过位于模具的第一互连金属层中的第一金属段连接到通孔。所述至少一个接触通孔链连接在所述第一有源区和位于所述管芯的第二互连金属层中的第二金属段之间。

6. 发明申请

US20060110767A1 Genotyping assay to predict cytochrome P4503A5 exression 审中-公开
标题翻译：基因分型法预测细胞色素P4503A5的表达
公开(公告)号：US20060110767A1
公开(公告)日：2006-05-25
申请号：US11285364
申请日：2005-11-22
申请人： Erin Schuetz , Jiong Zhang , Mahfoud Assem
发明人： Erin Schuetz , Jiong Zhang , Mahfoud Assem
IPC分类号： C12Q1/68 , G06F19/00 , C12P19/34
CPC分类号： C12Q1/6886 , C12Q2600/156 , Y02A90/26
摘要： Genetic polymorphisms responsible or associated with altered expression of cytochrome P450 CYP3A5 enzyme are described. Single nucleotide polymorphisms are provided. Methods for identifying subjects having a low or high drug metabolizing phenotype associated with CYP3A5 expression are provided. Assays, kits and methods for determining and assaying the CYP3A5 genotype and phenotype of individual patients are disclosed. Oligonucleotide probes and primers for use in the assays, kits and methods are described. Assays and methods for determining and evaluating an individual's metabolism of drugs and therapeutic agents, the potential for drug interactions, and thereby toxicity and effectiveness of certain drugs and treatment modalities, are provided.
摘要翻译：描述了负责或与细胞色素P450 CYP3A5酶表达改变相关的遗传多态性。提供单核苷酸多态性。提供了用于鉴定与CYP3A5表达相关的低或高药物代谢表型的受试者的方法。公开了用于确定和测定个体患者的CYP3A5基因型和表型的测定，试剂盒和方法。描述了用于测定，试剂盒和方法的寡核苷酸探针和引物。提供了用于确定和评估个体的药物和治疗剂代谢的药物相互作用的可能性，以及某些药物和治疗方式的毒性和有效性的测定和方法。

7. 发明授权

US09123719B2 Metal-oxide-metal capacitor 有权
标题翻译：金属氧化物金属电容器
公开(公告)号：US09123719B2
公开(公告)日：2015-09-01
申请号：US13533280
申请日：2012-06-26
申请人： Jiong Zhang , Joseph King , Akira Ito
发明人： Jiong Zhang , Joseph King , Akira Ito
IPC分类号： H01G4/002 , H01L23/522 , H01L27/08
CPC分类号： H01L23/5223 , H01L27/0805 , H01L2924/0002 , Y10T29/417 , H01L2924/00
摘要： A semiconductor structure may implement a metal-oxide-metal capacitor. When layer design rules change from one layer to the next, the structure may change the direction of the interleaved plates of the capacitor. For example, when the metallization width or spacing design rules change from layer M3 to layer M4, the structure may run the capacitor traces in different directions (e.g., orthogonal to one another) on M3 as compared to M4. Among the layers that adhere to the same design rules, for example layers M1, M2, and M3, the structure may run the capacitor traces in the same direction in each of the layers M1, M2, and M3. In this way, the capacitor traces overlap to large extent without misalignment on layers that have the same design rules, and the structure avoids misalignment of the capacitor traces when the design rules change.
摘要翻译：半导体结构可以实现金属氧化物 - 金属电容器。当层设计规则从一层改变到下一层时，结构可能改变电容器交错板的方向。例如，当金属化宽度或间距设计规则从层M3改变到层M4时，与M4相比，该结构可以在M3上沿不同方向（例如，彼此正交）运行电容器迹线。在遵循相同设计规则的层中，例如层M1，M2和M3，该结构可以在层M1，M2和M3中的每一层沿同一方向运行电容器迹线。以这种方式，电容器迹线在很大程度上重叠而不具有相同设计规则的层上的对准，并且当设计规则改变时，该结构避免了电容器迹线的未对准。

8. 发明申请

US20130342955A1 Metal-Oxide-Metal Capacitor 有权
标题翻译：金属 - 氧化物 - 金属电容器
公开(公告)号：US20130342955A1
公开(公告)日：2013-12-26
申请号：US13533280
申请日：2012-06-26
申请人： Jiong Zhang , Joseph King , Akira Ito
发明人： Jiong Zhang , Joseph King , Akira Ito
IPC分类号： H01G4/002 , H01G4/00
CPC分类号： H01L23/5223 , H01L27/0805 , H01L2924/0002 , Y10T29/417 , H01L2924/00
摘要： A semiconductor structure may implement a metal-oxide-metal capacitor. When layer design rules change from one layer to the next, the structure may change the direction of the interleaved plates of the capacitor. For example, when the metallization width or spacing design rules change from layer M3 to layer M4, the structure may run the capacitor traces in different directions (e.g., orthogonal to one another) on M3 as compared to M4. Among the layers that adhere to the same design rules, for example layers M1, M2, and M3, the structure may run the capacitor traces in the same direction in each of the layers M1, M2, and M3. In this way, the capacitor traces overlap to large extent without misalignment on layers that have the same design rules, and the structure avoids misalignment of the capacitor traces when the design rules change.
摘要翻译：半导体结构可以实现金属氧化物 - 金属电容器。当层设计规则从一层改变到下一层时，结构可能改变电容器交错板的方向。例如，当金属化宽度或间距设计规则从层M3改变到层M4时，与M4相比，该结构可以在M3上沿不同方向（例如，彼此正交）运行电容器迹线。在遵循相同设计规则的层中，例如层M1，M2和M3，该结构可以在层M1，M2和M3中的每一层沿同一方向运行电容器迹线。以这种方式，电容器迹线在很大程度上重叠而不具有相同设计规则的层上的对准，并且当设计规则改变时，该结构避免了电容器迹线的未对准。

9. 发明申请

US20090040671A1 Power clamp for on-chip ESD protection 审中-公开
标题翻译：用于片上ESD保护的电源钳
公开(公告)号：US20090040671A1
公开(公告)日：2009-02-12
申请号：US12221286
申请日：2008-08-01
申请人： Jiong Zhang
发明人： Jiong Zhang
IPC分类号： H02H9/04
CPC分类号： H02H9/046
摘要： According to an exemplary embodiment, a power clamp for providing on-chip ESD and mistrigger event protection includes a clamping transistor coupled between a power bus and a ground. The power clamp further includes a number of inverter stages coupled in series, where a first inverter stage has an output coupled to the clamping transistor. The power clamp further includes a turn-off resistor coupled between the power bus and an input of the first inverter. The turn-off resistor is configured to cause the clamping transistor to automatically turn off after having been turned on. The turn-off resistor determines a period of time that the clamping transistor is turned on after an ESD or mistrigger event has occurred on the power bus. The power clamp further includes a timing circuit coupled to the inverter stages. The power clamp further includes a feedback transistor coupled between a second inverter stage and the power bus.
摘要翻译：根据示例性实施例，用于提供片上ESD和失速触发器事件保护的功率钳包括耦合在电力总线和地之间的钳位晶体管。功率钳还包括串联耦合的多个反相器级，其中第一反相器级具有耦合到钳位晶体管的输出。电源钳还包括耦合在电源总线和第一反相器的输入端之间的关断电阻器。关断电阻被配置为使得钳位晶体管在导通之后自动关闭。关断电阻确定在电源总线上发生ESD或失火触发事件之后夹紧晶体管导通的时间段。功率钳还包括耦合到逆变器级的定时电路。功率钳还包括耦合在第二反相器级与电源总线之间的反馈晶体管。

10. 发明授权

US07397089B2 ESD protection structure using contact-via chains as ballast resistors 有权
标题翻译：使用接触通道链作为镇流电阻的ESD保护结构
公开(公告)号：US07397089B2
公开(公告)日：2008-07-08
申请号：US11201638
申请日：2005-08-10
申请人： Jiong Zhang , Yuhua Cheng
发明人： Jiong Zhang , Yuhua Cheng
IPC分类号： H01L23/62
CPC分类号： H01L27/0266 , H01L27/0629 , H01L29/0692 , H01L29/41725 , H01L29/41758 , H01L29/78 , H01L2924/0002 , H01L2924/00
摘要： According to an exemplary embodiment, an ESD protection structure situated in a semiconductor die includes a FET including a gate and first and second active regions, where the gate includes at least one gate finger, and where the at least one gate finger is situated between the first and second active regions. The ESD protection structure further includes at least one contact-via chain connected to the first active region, where the at least one contact-via chain includes a contact connected to a via. The at least one contact-via chain forms a ballast resistor for increased ESD current distribution uniformity. The contact is connected to the via by a first metal segment situated in a first interconnect metal layer of a die. The at least one contact-via chain is connected between the first active region and a second metal segment situated in a second interconnect metal layer of the die.
摘要翻译：根据示例性实施例，位于半导体管芯中的ESD保护结构包括包括栅极和第一和第二有源区的FET，其中栅极包括至少一个栅极指，并且其中至少一个栅极指位于第一和第二活跃区域。 ESD保护结构还包括连接到第一有源区的至少一个接触通孔链，其中至少一个接触通孔链包括连接到通孔的触点。所述至少一个接触通孔链形成用于增加ESD电流分布均匀性的镇流电阻器。触点通过位于模具的第一互连金属层中的第一金属段连接到通孔。所述至少一个接触通孔链连接在所述第一有源区和位于所述管芯的第二互连金属层中的第二金属段之间。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式