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1. 发明申请

WO2007035681A1 EXPLORATION OF THE METHOD OF THE INTERCONNECT EFFORT IN NANO-TECHNOLOGIES 审中-公开
标题翻译：探索纳米技术中互连作用的方法
公开(公告)号：WO2007035681A1
公开(公告)日：2007-03-29
申请号：PCT/US2006/036367
申请日：2006-09-18
申请人： QUALCOMM INCORPORATED , HWANG, Myeong-Eun , SEONG-OOK, Jung
发明人： HWANG, Myeong-Eun , SEONG-OOK, Jung
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F17/5036 , G06F2217/84
摘要： Methods and apparatus for estimating the propagation delay along a logical signal path are described herein. The methods and apparatus account for the behavior of multi-stage logic gates along a signal path, initial input transition times, inter-stage fanouts, as well as different logic gate types. The methods and apparatus convert signal transition features into an effective fanout to provide estimates of gate delay dependencies on input slope and gate logic topology.
摘要翻译：本文描述了用于估计沿着逻辑信号路径的传播延迟的方法和装置。这些方法和装置考虑了沿着信号路径的多级逻辑门的行为，初始输入转换时间，级间扇出以及不同的逻辑门类型。方法和装置将信号转换特征转换为有效的扇出，以提供对输入斜率和门逻辑拓扑的门延迟依赖性的估计。

2. 发明授权

US08531902B2 Sensing circuit 有权
标题翻译：感应电路
公开(公告)号：US08531902B2
公开(公告)日：2013-09-10
申请号：US13173795
申请日：2011-06-30
申请人： Seong-Ook Jung , Jisu Kim , Kyungho Ryu , Jung Pill Kim , Seung H. Kang
发明人： Seong-Ook Jung , Jisu Kim , Kyungho Ryu , Jung Pill Kim , Seung H. Kang
IPC分类号： G11C7/02
CPC分类号： G11C7/067 , G11C7/12 , G11C11/1659 , G11C11/1673 , G11C11/4091 , G11C16/26
摘要： A circuit includes a degeneration p-channel metal-oxide-semiconductor (PMOS) transistor, a load PMOS transistor, and a clamp transistor configured to clamp a voltage applied to a resistance based memory element during a sensing operation. A gate of the load PMOS transistor is controlled by an output of a not-AND (NAND) circuit.
摘要翻译：电路包括退化的p沟道金属氧化物半导体（PMOS）晶体管，负载PMOS晶体管和钳位晶体管，其被配置为在感测操作期间钳位施加到基于电阻的存储元件的电压。负载PMOS晶体管的栅极由非AND（NAND）电路的输出控制。

3. 发明授权

US08423329B2 System and method of adjusting a resistance-based memory circuit parameter 有权
标题翻译：调整基于电阻的存储器电路参数的系统和方法
公开(公告)号：US08423329B2
公开(公告)日：2013-04-16
申请号：US12691415
申请日：2010-01-21
申请人： Seong-Ook Jung , Jisu Kim , Jee-Hwan Song , Seung H. Kang
发明人： Seong-Ook Jung , Jisu Kim , Jee-Hwan Song , Seung H. Kang
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F2217/10 , G11C7/02 , G11C7/06 , G11C11/1673
摘要： Systems and methods of resistance-based memory circuit parameter adjustment are disclosed. In a particular embodiment, a method of determining a set of parameters of a resistance-based memory circuit includes determining a range of sizes for a clamp transistor and selecting a set of clamp transistors having sizes within the determined range of sizes. For each clamp transistor in the set of clamp transistors, a simulation may be executed to generate a first contour graph representing current values over a range of statistical values. The first contour graph may be used to identify a read disturbance area and a design range of the gate voltage of the clamp transistor and a load of the clamp transistor. The method may execute a simulation to generate a second contour graph representing sense margin over a range of statistical values of the gate voltage of the clamp transistor and the load of the clamp transistor. A sense margin may be selected based on the second contour graph that also satisfies the design range of the first contour graph. A sense margin may be determined for a selected clamp transistor in the set of transistors and the corresponding gate voltage and the load of the selected clamp transistor is determined based on the determined sense margin.
摘要翻译：公开了基于电阻的存储器电路参数调整的系统和方法。在特定实施例中，确定基于电阻的存储器电路的一组参数的方法包括确定钳位晶体管的尺寸范围，并选择尺寸在所确定的尺寸范围内的一组钳位晶体管。对于钳位晶体管组中的每个钳位晶体管，可以执行仿真以生成表示一定范围的统计值的当前值的第一轮廓图。第一轮廓图可以用于识别钳位晶体管的栅极电压和钳位晶体管的负载的读取扰动区域和设计范围。该方法可以执行仿真以产生表示钳位晶体管的栅极电压和钳位晶体管的负载的统计值范围内的检测余量的第二轮廓图。可以基于也满足第一轮廓图的设计范围的第二轮廓图来选择感测余量。可以针对晶体管组中的选定的钳位晶体管确定感测余量，并且基于所确定的感测余量来确定相应的栅极电压，并且选择的钳位晶体管的负载被确定。

4. 发明申请

US20130003447A1 SENSING CIRCUIT 有权
标题翻译：感应电路
公开(公告)号：US20130003447A1
公开(公告)日：2013-01-03
申请号：US13173795
申请日：2011-06-30
申请人： Seong-Ook Jung , Jisu Kim , Kyungho Ryu , Jung Pill Kim , Seung H. Kang
发明人： Seong-Ook Jung , Jisu Kim , Kyungho Ryu , Jung Pill Kim , Seung H. Kang
IPC分类号： G11C11/00 , G06F17/50 , H03K5/08
CPC分类号： G11C7/067 , G11C7/12 , G11C11/1659 , G11C11/1673 , G11C11/4091 , G11C16/26
摘要： A circuit includes a degeneration p-channel metal-oxide-semiconductor (PMOS) transistor, a load PMOS transistor, and a clamp transistor configured to clamp a voltage applied to a resistance based memory element during a sensing operation. A gate of the load PMOS transistor is controlled by an output of a not-AND (NAND) circuit.
摘要翻译：电路包括退化的p沟道金属氧化物半导体（PMOS）晶体管，负载PMOS晶体管和钳位晶体管，其被配置为在感测操作期间钳位施加到基于电阻的存储元件的电压。负载PMOS晶体管的栅极由非AND（NAND）电路的输出控制。

5. 发明授权

US07813166B2 Controlled value reference signal of resistance based memory circuit 有权
标题翻译：基于电阻的存储电路的受控值参考信号
公开(公告)号：US07813166B2
公开(公告)日：2010-10-12
申请号：US12164436
申请日：2008-06-30
申请人： Seong-Ook Jung , Jisu Kim , Jee-Hwan Song , Seung H. Kang , Sei Seung Yoon
发明人： Seong-Ook Jung , Jisu Kim , Jee-Hwan Song , Seung H. Kang , Sei Seung Yoon
IPC分类号： G11C7/00
CPC分类号： G11C7/14 , G11C11/1673 , G11C13/0002 , G11C13/004 , G11C2013/0054
摘要： Systems and methods of controlled value reference signals of resistance based memory circuits are disclosed. In a particular embodiment, a circuit device is disclosed that includes a first input configured to receive a reference control signal. The circuit device also includes an output responsive to the first input to selectively provide a controlled value reference voltage to a sense amplifier coupled to a resistance based memory cell.
摘要翻译：公开了基于电阻的存储器电路的受控值参考信号的系统和方法。在特定实施例中，公开了一种电路装置，其包括被配置为接收参考控制信号的第一输入。电路装置还包括响应于第一输入的输出，以选择性地向耦合到基于电阻的存储器单元的读出放大器提供受控值参考电压。

6. 发明申请

US20100194456A1 Delay locked loop, electronic device including the same, and method of operating the same 有权
标题翻译：延迟锁定环，包括相同的电子设备及其操作方法
公开(公告)号：US20100194456A1
公开(公告)日：2010-08-05
申请号：US12592753
申请日：2009-12-02
申请人： Hee Chai Kang , Kyeong Ho Ryu , Seong Ook Jung , Won Lee , Dong Hwan Lee , Alex Joo , Jong Ryun Choi
发明人： Hee Chai Kang , Kyeong Ho Ryu , Seong Ook Jung , Won Lee , Dong Hwan Lee , Alex Joo , Jong Ryun Choi
IPC分类号： H03L7/06
CPC分类号： H03L7/0814 , H03K5/00006 , H03K5/133 , H03K2005/00058 , H03L7/07 , H03L7/0995 , H03L7/10
摘要： A delay locked loop controls a plurality of delay blocks included in a delay line and thus generate a plurality of clock signals which have a frequency obtained by multiplying a frequency of a reference clock signal, an accurate phase delay, and a constant duty cycle. The delay locked loop calculates an initial delay value and applies it to the delay blocks, thereby preventing harmonic locking and reducing locking time.
摘要翻译：延迟锁定环控制包括在延迟线中的多个延迟块，从而产生具有通过将参考时钟信号的频率，精确相位延迟和恒定占空比相乘而获得的频率的多个时钟信号。延迟锁定环路计算初始延迟值并将其应用于延迟块，从而防止谐波锁定并减少锁定时间。

7. 发明申请

US20080101143A1 MEMORY DEVICE WITH CONFIGURABLE DELAY TRACKING 有权
标题翻译：具有可配置延迟跟踪的存储器件
公开(公告)号：US20080101143A1
公开(公告)日：2008-05-01
申请号：US11552893
申请日：2006-10-25
申请人： Seong-Ook Jung , Sei Seung Yoon , Yi Han
发明人： Seong-Ook Jung , Sei Seung Yoon , Yi Han
IPC分类号： G11C7/02
CPC分类号： G11C7/08 , G11C7/14 , G11C7/22 , G11C8/08 , G11C11/41 , G11C11/419 , G11C29/02 , G11C29/023 , G11C29/028 , G11C2207/065
摘要： A memory device with configurable delay tracking is described. The memory device includes M normal word line drivers, a dummy word line driver a memory array, N sense amplifiers, and a timing control circuit. The memory array includes M rows and N columns of memory cells and a column of dummy cells. The word line drivers drive word lines for the rows of memory cells. The dummy word line driver drives a dummy word line for at least one dummy cell in the column of dummy cells. The timing control circuit generates enable signals having configurable delay, which may be obtained with an acceleration circuit that provides variable drive for a dummy bit line coupled to the column of memory cells. The sense amplifiers detect bit lines for the columns of memory cells based on the enable signals.
摘要翻译：描述了具有可配置延迟跟踪的存储器件。存储器件包括M个正常字线驱动器，一个虚拟字线驱动器，一个存储器阵列，N个读出放大器和一个定时控制电路。存储器阵列包括M行和N列存储器单元和一列虚拟单元。字线驱动程序驱动内存单元行的字线。虚拟字线驱动器驱动虚拟单元列中的至少一个虚拟单元的虚拟字线。定时控制电路产生具有可配置延迟的使能信号，其可以通过为耦合到存储器单元列的虚拟位线提供可变驱动的加速电路来获得。读出放大器基于使能信号来检测存储器单元列的位线。

8. 发明授权

US06903987B2 Single data line sensing scheme for TCCT-based memory cells 失效
标题翻译：基于TCCT的存储单元的单数据线感测方案
公开(公告)号：US06903987B2
公开(公告)日：2005-06-07
申请号：US10211766
申请日：2002-08-01
申请人： Sei-Seung Yoon , Jin-Man Han , Seong-Ook Jung
发明人： Sei-Seung Yoon , Jin-Man Han , Seong-Ook Jung
IPC分类号： G11C11/00 , G11C11/39 , H01L21/8244 , H01L27/11 , H01L31/111
CPC分类号： H01L27/11 , G11C11/39
摘要： A sensing circuit including a sense amplifier to resolve a data signal generated by a memory cell is disclosed herein. The sensing circuit includes a bit line to receive the data signal, a first pre-charge device coupled to the bit line and configured to pre-charge the bit line, a device for providing a bias coupled to the bit line and configured to provide a bias to the bit line, and a reference node configured to be at least one pre-determined level. In one embodiment the pre-determined level is equal to a low potential such as ground and in another embodiment equal to a high potential such as VDD. One or more switching devices allows for the activation or deactivation of the pre-charge device allowing to pre-charge the bit line to a certain potential and the sensing circuit quickly and accurately determines whether a logical state of ‘1’ or ‘0’ is being applied to the bit line.
摘要翻译：本文公开了一种包括用于解析由存储器单元产生的数据信号的读出放大器的感测电路。感测电路包括用于接收数据信号的位线，耦合到位线并被配置为对位线预充电的第一预充电器件，用于提供耦合到位线的偏置并被配置为提供偏置到位线，以及被配置为至少一个预定电平的参考节点。在一个实施例中，预定电平等于诸如地电位的低电位，而在另一实施例中等于诸如V DD的高电位。一个或多个开关装置允许激活或去激活预充电装置，允许将位线预充电到特定电位，感测电路快速而准确地确定逻辑状态“1”或“0”是否为应用于位线。

9. 发明授权

US06735113B2 Circuit and method for implementing a write operation with TCCT-based memory cells 失效
标题翻译：用于基于TCCT的存储单元实现写入操作的电路和方法
公开(公告)号：US06735113B2
公开(公告)日：2004-05-11
申请号：US10272360
申请日：2002-10-15
申请人： Sei-Seung Yoon , Seong-Ook Jung
发明人： Sei-Seung Yoon , Seong-Ook Jung
IPC分类号： G11C1134
CPC分类号： G11C11/39
摘要： The present invention provides a circuit and a method for providing nondestructive write operations and optimized memory access operations with reduced power consumption during memory access, such as during write operations. In one embodiment, a memory device comprises a memory cell configured to store a first data bit. The memory device also comprises a write access circuit coupled to the memory cell for providing a write data bit having a write data bit magnitude. The write access circuit is configured to adjust the write data bit magnitude to an intermediate logic state magnitude in a memory operation.
摘要翻译：本发明提供一种电路和方法，用于在存储器访问期间（例如在写入操作期间）以降低的功耗提供非破坏性写入操作和优化的存储器访问操作。在一个实施例中，存储器设备包括被配置为存储第一数据位的存储器单元。存储器件还包括耦合到存储器单元的写存取电路，用于提供具有写数据位幅值的写数据位。写访问电路被配置为在存储器操作中将写入数据位幅度调整到中间逻辑状态幅度。

10. 发明授权

US5760791A Graphic RAM having a dual port and a serial data access method thereof 失效
标题翻译：具有双端口的图形RAM及其串行数据访问方法
公开(公告)号：US5760791A
公开(公告)日：1998-06-02
申请号：US378277
申请日：1995-01-26
申请人： Seong-Ook Jung , Seung-Mo Seo , Dae-Je Chin
发明人： Seong-Ook Jung , Seung-Mo Seo , Dae-Je Chin
IPC分类号： G11C11/401 , G09G5/395 , G11C7/10 , G09G5/36
CPC分类号： G09G5/395 , G11C7/1075
摘要： A graphic RAM array has a plurality of sub blocks which share random and serial output paths. This structure enables random access to the random output path of one RAM array while a specific sub block of another other RAM array is performing a display operation via the serial output path. The graphic RAM does not have a separate data register and outputs the serial data using only the RAM array. Thus, only the RAM array is formed in the cell core region, thereby reducing the size and price of the chip. In addition, it is possible for the graphic RAM to be compatible with a system having a conventional video RAM controller.
摘要翻译：图形RAM阵列具有共享随机和串行输出路径的多个子块。该结构能够随机访问一个RAM阵列的随机输出路径，而另一个RAM阵列的特定子块通过串行输出路径执行显示操作。图形RAM不具有单独的数据寄存器，仅使用RAM阵列输出串行数据。因此，在单元芯区域中仅形成RAM阵列，从而减小芯片的尺寸和价格。此外，图形RAM可以与具有常规视频RAM控制器的系统兼容。

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