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1. 发明授权

US09196337B2 Low sensing current non-volatile flip-flop 有权
标题翻译：低感测电流非易失性触发器
公开(公告)号：US09196337B2
公开(公告)日：2015-11-24
申请号：US13613205
申请日：2012-09-13
申请人： Seong-Ook Jung , Youngdon Jung , Kyungho Ryu , Jisu Kim , Jung Pill Kim , Seung H. Kang
发明人： Seong-Ook Jung , Youngdon Jung , Kyungho Ryu , Jisu Kim , Jung Pill Kim , Seung H. Kang
IPC分类号： G11C11/16 , G11C7/06 , G11C14/00
CPC分类号： G11C11/1673 , G11C7/065 , G11C11/1659 , G11C14/0081
摘要： A low sensing current non volatile flip flop includes a first stage to sense a resistance difference between two magnetic tunnel junctions (MTJs) and a second stage having circuitry to amplify the output of the first stage. The output of the first stage is initially pre-charged and determined by the resistance difference of the two MTJs when the sensing operation starts. The first stage does not have a pull-up path to a source voltage (VDD), and therefore does not have a DC path from VDD to ground during the sensing operation. A slow sense enable (SE) signal slope reduces peak sensing current in the first stage. A secondary current path reduces the sensing current duration of the first stage.
摘要翻译：低感测电流非易失性触发器包括用于感测两个磁性隧道结（MTJ）之间的电阻差的第一级和具有用于放大第一级的输出的电路的第二级。第一级的输出最初是预充电的，并且由感测操作开始时的两个MTJ的电阻差决定。第一级没有到源极电压（VDD）的上拉路径，因此在感测操作期间没有从VDD到地的DC路径。缓慢感应使能（SE）信号斜率可以降低第一级的峰值检测电流。次级电流路径减小了第一级的感测电流持续时间。

2. 发明申请

US20130194862A1 NON-VOLATILE FLIP-FLOP 有权
标题翻译：非挥发性飞溅
公开(公告)号：US20130194862A1
公开(公告)日：2013-08-01
申请号：US13361760
申请日：2012-01-30
申请人： Seong-Ook Jung , Kyungho Ryu , Youngdon Jung , Jisu Kim , Jung Pill Kim , Seung H. Kang
发明人： Seong-Ook Jung , Kyungho Ryu , Youngdon Jung , Jisu Kim , Jung Pill Kim , Seung H. Kang
IPC分类号： G11C11/16
CPC分类号： G11C14/00 , G11C11/1659 , G11C11/1673 , G11C14/0081
摘要： A flip-flop has an output control node and an isolation switch selectively couples a retention sense node to the output control node. A sense circuit selectively couples an external sense current source to the retention sense node and to magnetic tunneling junction (MTJ) elements. Optionally a write circuit selectively injects a write current through one MTJ element and then another MTJ element. Optionally, a write circuit injects a write current through a first MTJ element concurrently with injecting a write current through a second MTJ element.
摘要翻译：触发器具有输出控制节点，并且隔离开关选择性地将保持感测节点耦合到输出控制节点。感测电路将外部感测电流源选择性地耦合到保持感测节点和磁性隧道结（MTJ）元件。可选地，写入电路通过一个MTJ元件和另一个MTJ元件选择性地注入写入电流。可选地，写入电路通过第一MTJ元件同时注入写入电流，并通过第二MTJ元件注入写入电流。

3. 发明授权

US08493116B2 Clock delay circuit and delay locked loop including the same 有权
标题翻译：时钟延迟电路和延迟锁定环包括相同
公开(公告)号：US08493116B2
公开(公告)日：2013-07-23
申请号：US13232555
申请日：2011-09-14
申请人： Jong-Ryun Choi , Seong-Ook Jung , Suho Kim , Heechai Kang , Kyungho Ryu
发明人： Jong-Ryun Choi , Seong-Ook Jung , Suho Kim , Heechai Kang , Kyungho Ryu
IPC分类号： H03L7/06
CPC分类号： H03H11/26 , H03L7/0814
摘要： A digital delay line includes a plurality of delay cells therein. The delay line is configured to delay a periodic signal received at a first input thereof by passing the periodic signal through a selected number of the plurality of delay cells, in response to a discontinuous thermometer code that encodes the selected number. A code converter is provided, which includes a group bit decoder, a shared bit decoder and a code output cell array, which are collectively configured to generate the discontinuous thermometer code in response to a binary control code.
摘要翻译：数字延迟线在其中包括多个延迟单元。延迟线被配置为响应于编码所选择的数量的不连续的温度计代码，通过使周期信号通过选定数量的多个延迟单元来延迟在其第一输入处接收到的周期信号。提供了一种代码转换器，其包括组位解码器，共享位解码器和代码输出单元阵列，它们被共同配置为响应二进制控制代码产生不连续的温度计代码。

4. 发明申请

US20120026783A1 Latching Circuit 有权
标题翻译：闭锁电路
公开(公告)号：US20120026783A1
公开(公告)日：2012-02-02
申请号：US12847371
申请日：2010-07-30
申请人： Seong-Ook Jung , Kyungho Ryu , Jisu Kim , Jung Pill Kim , Seung H. Kang
发明人： Seong-Ook Jung , Kyungho Ryu , Jisu Kim , Jung Pill Kim , Seung H. Kang
IPC分类号： G11C11/00 , G11C7/10
CPC分类号： G11C11/1675 , G11C11/1659 , G11C11/1673 , G11C13/0002 , G11C14/009
摘要： A non-volatile latch circuit includes a pair of cross-coupled inverters, a pair of resistance-based memory elements, and write circuitry configured to write data to the pair of resistance-based memory elements. The pair of resistance-based memory elements is isolated from the pair of cross-coupled inverters during a latching operation. A sensing circuit includes a first current path that includes a first resistance-based memory element and an output of the sensing circuit. The sensing circuit includes a second current path to reduce current flow through the first resistance-based memory element at a first operating point of the sensing circuit. The sensing circuit may also include an n-type metal-oxide-semiconductor (NMOS) transistor to provide a step down supply voltage to the first current path.
摘要翻译：非易失性锁存电路包括一对交叉耦合的反相器，一对基于电阻的存储器元件和被配置为将数据写入到该对基于电阻的存储器元件的写入电路。在锁定操作期间，一对基于电阻的存储器元件与一对交叉耦合的反相器隔离。感测电路包括第一电流路径，其包括第一基于电阻的存储元件和感测电路的输出。感测电路包括第二电流路径，以减小在感测电路的第一工作点处通过第一基于电阻的存储元件的电流。感测电路还可以包括n型金属氧化物半导体（NMOS）晶体管，以向第一电流路径提供降压电源电压。

5. 发明申请

US20110267874A1 Invalid Write Prevention for STT-MRAM Array 有权
标题翻译： STT-MRAM阵列无效写入预防
公开(公告)号：US20110267874A1
公开(公告)日：2011-11-03
申请号：US12769995
申请日：2010-04-29
申请人： Kyungho Ryu , Jisu Kim , Seong-Ook Jung , Seung H. Kang
发明人： Kyungho Ryu , Jisu Kim , Seong-Ook Jung , Seung H. Kang
IPC分类号： G11C11/00 , H01F7/06 , G11C7/22 , G11C8/08
CPC分类号： G11C11/1675 , G11C11/1659 , H01L43/12 , Y10T29/4902
摘要： In a Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) a bit cell array can have a source line substantially parallel to a word line. The source line can be substantially perpendicular to bit lines. A source line control unit includes a common source line driver and a source line selector configured to select individual ones of the source lines. The source line driver and source line selector can be coupled in multiplexed relation. A bit line control unit includes a common bit line driver and a bit line selector in multiplexed relation. The bit line control unit includes a positive channel metal oxide semiconductor (PMOS) element coupled between the common source line driver and bit line select lines and bit lines.
摘要翻译：在自旋转移力矩磁阻随机存取存储器（STT-MRAM）中，位单元阵列可以具有基本上平行于字线的源极线。源极线可以基本上垂直于位线。源极线控制单元包括公共源极线驱动器和被配置为选择各个源极线的源极线选择器。源极线驱动器和源极线选择器可以以多路复用关系耦合。位线控制单元包括公共位线驱动器和复用关系的位线选择器。位线控制单元包括耦合在公共源线驱动器和位线选择线和位线之间的正沟道金属氧化物半导体（PMOS）元件。

6. 发明授权

US08670266B2 Non-volatile flip-flop 有权
标题翻译：非易失性触发器
公开(公告)号：US08670266B2
公开(公告)日：2014-03-11
申请号：US13361760
申请日：2012-01-30
申请人： Seong-Ook Jung , Kyungho Ryu , Youngdon Jung , Jisu Kim , Jung Pill Kim , Seung H. Kang
发明人： Seong-Ook Jung , Kyungho Ryu , Youngdon Jung , Jisu Kim , Jung Pill Kim , Seung H. Kang
IPC分类号： G11C11/00 , G11C11/14 , G11C7/10
CPC分类号： G11C14/00 , G11C11/1659 , G11C11/1673 , G11C14/0081
摘要： A flip-flop has an output control node and an isolation switch selectively couples a retention sense node to the output control node. A sense circuit selectively couples an external sense current source to the retention sense node and to magnetic tunneling junction (MTJ) elements. Optionally a write circuit selectively injects a write current through one MTJ element and then another MTJ element. Optionally, a write circuit injects a write current through a first MTJ element concurrently with injecting a write current through a second MTJ element.
摘要翻译：触发器具有输出控制节点，并且隔离开关选择性地将保持感测节点耦合到输出控制节点。感测电路将外部感测电流源选择性地耦合到保持感测节点和磁性隧道结（MTJ）元件。可选地，写入电路通过一个MTJ元件和另一个MTJ元件选择性地注入写入电流。可选地，写入电路通过第一MTJ元件同时注入写入电流，并通过第二MTJ元件注入写入电流。

7. 发明申请

US20110221495A1 DIGITAL DLL INCLUDING SKEWED GATE TYPE DUTY CORRECTION CIRCUIT AND DUTY CORRECTION METHOD THEREOF 有权
标题翻译：数字DLL，其中包括门锁类型校正电路及其校正方法
公开(公告)号：US20110221495A1
公开(公告)日：2011-09-15
申请号：US13046073
申请日：2011-03-11
申请人： Won LEE , Donghwan Lee , Seong-Ook Jung , Heechai Kang , Kyungho Ryu , Donghoon Jung
发明人： Won LEE , Donghwan Lee , Seong-Ook Jung , Heechai Kang , Kyungho Ryu , Donghoon Jung
IPC分类号： H03L7/06 , H03K5/156
CPC分类号： H03K5/1565 , G11C7/222 , H03L7/0814
摘要： Provided are a delay locked loop (DLL) that may can be included in a data processing device and may include a duty correction circuit, and a duty correction method of such a DLL. The duty correction method includes aligning a second transition of an output clock at a first transition of a clock for duty correction, sampling the clock for duty correction at the first transition of the output clock to detect an error of a duty cycle, and performing duty correction using a skewed gate chain according to the detected error of a duty cycle.
摘要翻译：提供了可以包括在数据处理装置中的延迟锁定环（DLL），并且可以包括这样的DLL的占空比校正电路和占空比校正方法。占空比校正方法包括：在时钟的第一次转换时对输出时钟进行二次转换，对输出时钟的第一次转换进行占空比校正的时钟采样，以检测占空比的误差，并执行占空比根据检测到的占空比误差，使用偏斜栅极链进行校正。

8. 发明授权

US08531902B2 Sensing circuit 有权
标题翻译：感应电路
公开(公告)号：US08531902B2
公开(公告)日：2013-09-10
申请号：US13173795
申请日：2011-06-30
申请人： Seong-Ook Jung , Jisu Kim , Kyungho Ryu , Jung Pill Kim , Seung H. Kang
发明人： Seong-Ook Jung , Jisu Kim , Kyungho Ryu , Jung Pill Kim , Seung H. Kang
IPC分类号： G11C7/02
CPC分类号： G11C7/067 , G11C7/12 , G11C11/1659 , G11C11/1673 , G11C11/4091 , G11C16/26
摘要： A circuit includes a degeneration p-channel metal-oxide-semiconductor (PMOS) transistor, a load PMOS transistor, and a clamp transistor configured to clamp a voltage applied to a resistance based memory element during a sensing operation. A gate of the load PMOS transistor is controlled by an output of a not-AND (NAND) circuit.
摘要翻译：电路包括退化的p沟道金属氧化物半导体（PMOS）晶体管，负载PMOS晶体管和钳位晶体管，其被配置为在感测操作期间钳位施加到基于电阻的存储元件的电压。负载PMOS晶体管的栅极由非AND（NAND）电路的输出控制。

9. 发明申请

US20130003447A1 SENSING CIRCUIT 有权
标题翻译：感应电路
公开(公告)号：US20130003447A1
公开(公告)日：2013-01-03
申请号：US13173795
申请日：2011-06-30
申请人： Seong-Ook Jung , Jisu Kim , Kyungho Ryu , Jung Pill Kim , Seung H. Kang
发明人： Seong-Ook Jung , Jisu Kim , Kyungho Ryu , Jung Pill Kim , Seung H. Kang
IPC分类号： G11C11/00 , G06F17/50 , H03K5/08
CPC分类号： G11C7/067 , G11C7/12 , G11C11/1659 , G11C11/1673 , G11C11/4091 , G11C16/26
摘要： A circuit includes a degeneration p-channel metal-oxide-semiconductor (PMOS) transistor, a load PMOS transistor, and a clamp transistor configured to clamp a voltage applied to a resistance based memory element during a sensing operation. A gate of the load PMOS transistor is controlled by an output of a not-AND (NAND) circuit.
摘要翻译：电路包括退化的p沟道金属氧化物半导体（PMOS）晶体管，负载PMOS晶体管和钳位晶体管，其被配置为在感测操作期间钳位施加到基于电阻的存储元件的电压。负载PMOS晶体管的栅极由非AND（NAND）电路的输出控制。

10. 发明授权

US08693272B2 Sensing circuit 有权
标题翻译：感应电路
公开(公告)号：US08693272B2
公开(公告)日：2014-04-08
申请号：US13173641
申请日：2011-06-30
申请人： Seong-Ook Jung , Jisu Kim , Kyungho Ryu , Seung H. Kang
发明人： Seong-Ook Jung , Jisu Kim , Kyungho Ryu , Seung H. Kang
IPC分类号： G11C7/00
CPC分类号： G11C7/067 , G11C7/12 , G11C11/1655 , G11C11/1673 , G11C11/4091 , G11C13/004 , G11C16/26 , G11C2207/002
摘要： A circuit includes a degeneration p-channel metal-oxide-semiconductor (PMOS) transistor, a load PMOS transistor, and a clamp transistor configured to clamp a voltage applied to a resistance based memory element during a sensing operation. A gate of the load PMOS transistor is controlled by an output of an operational amplifier.
摘要翻译：电路包括退化的p沟道金属氧化物半导体（PMOS）晶体管，负载PMOS晶体管和钳位晶体管，其被配置为在感测操作期间钳位施加到基于电阻的存储元件的电压。负载PMOS晶体管的栅极由运算放大器的输出控制。

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