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1. 发明授权

US07288999B1 Pre-distortion system for a synthesizer having modulation applied in the reference path 有权
标题翻译：具有在参考路径中应用的调制的合成器的预失真系统
公开(公告)号：US07288999B1
公开(公告)日：2007-10-30
申请号：US11347956
申请日：2006-02-06
申请人： Alexander Wayne Hietala , Ryan Lee Bunch , Scott Robert Humphreys , Barry Travis Hunt, Jr.
发明人： Alexander Wayne Hietala , Ryan Lee Bunch , Scott Robert Humphreys , Barry Travis Hunt, Jr.
IPC分类号： H03L7/197 , H04L25/49
CPC分类号： H03L7/1976 , H03C3/0966 , H03L7/23 , H03L2207/12
摘要： A system providing a phase or frequency modulated signal is provided. In general, the system includes a phase locked loop (PLL) having a fractional-N divider in a reference path of the PLL operating to divide a reference frequency based on a pre-distorted modulation signal. Pre-distortion circuitry operates to provide the pre-distorted modulation signal by pre-distorting a modulation signal such that a convolution, or cascade, of the pre-distortion and a transfer function of the PLL results in a substantially flat frequency response for a range of modulation rates greater than a bandwidth of the PLL.
摘要翻译：提供了提供相位或频率调制信号的系统。通常，该系统包括在PLL的参考路径中具有分数N分频器的锁相环（PLL），其操作以基于预失真调制信号来划分参考频率。预失真电路通过对调制信号进行预失真来提供预失真调制信号，使得预失真和PLL的传递函数的卷积或级联导致范围内的基本平坦的频率响应的调制率大于PLL的带宽。

2. 发明授权

US07626462B1 Fractional-N based digital AFC system with a translational PLL transmitter 有权
标题翻译：基于分数N的数字AFC系统具有平移PLL发射机
公开(公告)号：US07626462B1
公开(公告)日：2009-12-01
申请号：US11415578
申请日：2006-05-02
申请人： Alexander Wayne Hietala , Ryan Lee Bunch , Scott Robert Humphreys , Barry Travis Hunt, Jr. , Stephen T. Janesch
发明人： Alexander Wayne Hietala , Ryan Lee Bunch , Scott Robert Humphreys , Barry Travis Hunt, Jr. , Stephen T. Janesch
IPC分类号： H03L7/00
CPC分类号： H03L7/23 , H03J1/005 , H03J7/065 , H03L7/1974
摘要： A fractional-N based Automatic Frequency Control (AFC) system for a mobile terminal is provided. In general, automatic frequency control is implemented in a frequency synthesizer to correct or compensate for a frequency error of an associated reference oscillator. The frequency synthesizer includes a first fractional-N phase-locked loop (FN-PLL) generating a baseband clock signal used by a baseband processor of the mobile terminal, a second FN-PLL generating a receiver local oscillator signal used by a receiver of the mobile terminal to downconvert a received radio frequency signal to a desired frequency, and a translational PLL generating a transmitter local oscillator signal used by a transmitter of the mobile terminal to provide a radio frequency transmit signal. The automatic frequency control is performed by applying a digital correction value, which is preferably multiplicative, to fractional-N dividers of the first and second FN-PLLs.
摘要翻译：提供了一种用于移动终端的基于分数N的自动频率控制（AFC）系统。通常，在频率合成器中实现自动频率控制以校正或补偿相关参考振荡器的频率误差。频率合成器包括产生由移动终端的基带处理器使用的基带时钟信号的第一小数N锁相环（FN-PLL），第二FN-PLL产生由接收机使用的接收机本地振荡器信号移动终端将所接收的射频信号下变频到期望的频率，以及平移PLL，其生成由移动终端的发射机使用以提供射频发射信号的发射机本地振荡器信号。通过将优选乘法的数字校正值应用于第一和第二FN-PLL的分数N分频器来执行自动频率控制。

3. 发明授权

US07098754B2 Fractional-N offset phase locked loop 有权
标题翻译：小数N偏移锁相环
公开(公告)号：US07098754B2
公开(公告)日：2006-08-29
申请号：US11047258
申请日：2005-01-31
申请人： Scott Robert Humphreys , Ryan Lee Bunch , Barry Travis Hunt, Jr. , Alexander Wayne Hietala
发明人： Scott Robert Humphreys , Ryan Lee Bunch , Barry Travis Hunt, Jr. , Alexander Wayne Hietala
IPC分类号： H03C3/00 , H04L27/20
CPC分类号： H03L7/1976 , H03C3/0966 , H03L7/23 , H03L2207/12
摘要： A fractional-N offset phase locked loop (FN-OPLL) is provided. The FN-OPLL includes a fractional divider, a phase detector, a loop filter, a voltage controlled oscillator (VCO), and feedback circuitry. Combiner circuitry combines an initial fractional divide value and a modulation signal to provide a combined fractional divide value. Based on the combined fractional divide value, the fractional-N divider divides a reference frequency and provides a divided reference frequency to the phase detector. The phase detector compares a phase of the divided reference frequency to a phase of a feedback signal to provide a comparison signal. The comparison signal is filtered by the loop filter to provide a control signal to the VCO, where the control signal controls a frequency of an output signal of the VCO. The output signal is processed by the feedback circuitry to provide the feedback signal to the phase detector.
摘要翻译：提供了一个分数N偏移锁相环（FN-OPLL）。 FN-OPLL包括分数分频器，相位检测器，环路滤波器，压控振荡器（VCO）和反馈电路。组合器电路组合初始分数除法值和调制信号以提供组合分数除数值。基于组合分数除法，分数N分频器划分参考频率，并向相位检测器提供分频参考频率。相位检测器将分频参考频率的相位与反馈信号的相位进行比较，以提供比较信号。比较信号由环路滤波器滤波，以向VCO提供控制信号，其中控制信号控制VCO的输出信号的频率。输出信号由反馈电路处理，以将反馈信号提供给相位检测器。

4. 发明授权

US06891414B1 Digital calibration for capacitor voltage non-linearity 有权
标题翻译：数字校准电容器电压非线性
公开(公告)号：US06891414B1
公开(公告)日：2005-05-10
申请号：US10794861
申请日：2004-03-05
申请人： Ryan Lee Bunch , Scott Robert Humphreys , Barry Travis Hunt, Jr. , Paul Gerard Martyniuk , Christopher Truong Ngo
发明人： Ryan Lee Bunch , Scott Robert Humphreys , Barry Travis Hunt, Jr. , Paul Gerard Martyniuk , Christopher Truong Ngo
IPC分类号： H03L7/06 , H03L7/089 , H03L7/093 , H03L7/18
CPC分类号： H03L7/0891 , H03L7/093 , H03L7/18
摘要： The present invention provides a system for adjusting a selectable capacitance of a variable capacitance array to compensate for voltage non-linearity of the variable capacitance array. In general, the system includes the variable capacitance array and a calibration circuit. The calibration circuit operates to determine a voltage across the variable capacitance array and to generate a capacitance selection signal based on the voltage across the variable capacitance array and a known capacitance versus voltage characteristic of the variable capacitance array.
摘要翻译：本发明提供了一种用于调整可变电容阵列的可选择电容以补偿可变电容阵列的电压非线性的系统。通常，该系统包括可变电容阵列和校准电路。校准电路用于确定可变电容阵列上的电压，并且基于可变电容阵列上的电压和可变电容阵列的已知电容对电压特性来产生电容选择信号。

5. 发明授权

US06731145B1 Phase-locked loop having loop gain and frequency response calibration 有权
标题翻译：锁相环具有环路增益和频率响应校准
公开(公告)号：US06731145B1
公开(公告)日：2004-05-04
申请号：US10409291
申请日：2003-04-08
申请人： Scott Robert Humphreys , Barry Travis Hunt, Jr.
发明人： Scott Robert Humphreys , Barry Travis Hunt, Jr.
IPC分类号： H03L706
CPC分类号： H03L7/18 , H03L7/1075
摘要： The invention provides an apparatus and method for calibrating both the pole/zero locations and the gain of a charge pump phase-locked loop's (PLL's) frequency response with one calibration operation. In one embodiment, the calibration is performed using a bandgap voltage reference and a stable frequency reference in order to measure a slew rate (I/C), defined as a current-to-capacitance ratio, and then adjusting the RC time constant (tRC) by adjusting the capacitance value. The adjustment setting is used in the loop filter capacitors, thereby calibrating the pole and zero locations of the PLL, which depend on the RC product. The charge pump reference current is proportional to the ratio of the bandgap voltage to the resistor value. When the capacitance is adjusted, the slew rate is calibrated as well, wherein the slew rate represents a portion of the loop gain of the PLL.
摘要翻译：本发明提供一种用于通过一次校准操作来校准电极/锁相环（PLL）频率响应的极点/零点位置和增益的装置和方法。在一个实施例中，使用带隙电压参考和稳定频率参考来执行校准，以便测量被定义为电流 - 电容比的转换速率（I / C），然后调整RC时间常数（tRC ）通过调整电容值。调节设置用于环路滤波电容器，从而校准PLL的极点和零点位置，这取决于RC产品。电荷泵参考电流与带隙电压与电阻值的比例成正比。当调整电容时，压摆率也被校准，其中转换速率表示PLL的环路增益的一部分。

6. 发明授权

US06448831B1 True single-phase flip-flop 有权
标题翻译：真正的单相触发器
公开(公告)号：US06448831B1
公开(公告)日：2002-09-10
申请号：US09879671
申请日：2001-06-12
申请人： Barry Travis Hunt, Jr. , Scott Robert Humphreys
发明人： Barry Travis Hunt, Jr. , Scott Robert Humphreys
IPC分类号： H03K3356
CPC分类号： H03K23/40 , H03K23/44
摘要： Undersired glitches in output signals from TSPC-1 flip-flop circuits having an output stage comprising an node and a second node are removed by precharging the second node (prior to a clock transition) to a value desired at the output node during a period following the clock transition, and connecting the output node to the second node upon such clock transition. Corrective circuitry illustratively comprising two NMOS transistors added to the output stage and receiving an input reflecting the desired future output is active during a portion of the operating cycle when the output stage exhibits a high impedance tristate condition.
摘要翻译：在具有包括节点和第二节点的输出级的TSPC-1触发器电路的输出信号中，通过在第二节点（在时钟转换之前）预充电到在输出节点期望的值，从而消除了对输出信号的不足的毛刺时钟转换，并且在这种时钟转换时将输出节点连接到第二节点。示例性地包括被添加到输出级并且接收反映期望的未来输出的输入的两个NMOS晶体管的校正电路在工作周期的一部分期间是有效的，当输出级呈现高阻抗三态条件时。

7. 发明授权

US06385276B1 Dual-modulus prescaler 有权
标题翻译：双模预分频器
公开(公告)号：US06385276B1
公开(公告)日：2002-05-07
申请号：US09879670
申请日：2001-06-12
申请人： Barry Travis Hunt, Jr. , Scott Robert Humphreys
发明人： Barry Travis Hunt, Jr. , Scott Robert Humphreys
IPC分类号： H03K2100
CPC分类号： H03K23/667
摘要： A dual-modulus digital prescaler circuit having an extended period in which responses to a divider control indicating a possible modulus change must be made, such extended period permitting higher speed operation while suffering no penalty in manufacturing cost or increased power use. In embodiments comprising a dual modulus divider, a fixed-modulus divider and interconnected control logic, dual modulus divider state transitions giving rise to incrementing of fixed-modulus divider states are selected to be independent of short-term instabilities in divider control inputs. Identified critical state transitions associated with output signals from the dual modulus divider are constrained to occur at times prior to periods of insensitivity to stability of the dual-modulus control signal. Thus, timing of such output signals is determined so that there will be following time interval sufficient to provide desired stability of the modulus control signal for the next divide cycle.
摘要翻译：一种具有延长周期的双模数字预分频器电路，其中必须对表示可能的模数变化的分频器控制器作出响应，这样的延长时间允许更高速度的操作，同时不牺牲制造成本或增加的功率使用。在包括双模式分配器，固定模数分频器和互连控制逻辑的实施例中，引起固定模数分频器状态增加的双模除法器状态转换被选择为与分频器控制输入中的短期不稳定性无关。与双模式分配器的输出信号相关联的识别的临界状态转变被限制为在对双模控制信号的稳定性不敏感的时段之前发生。因此，确定这种输出信号的定时，使得将存在足以提供用于下一个分频周期的模数控制信号的期望稳定性的后续时间间隔。

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