专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08665663B2 Memory circuit and control method thereof 有权
标题翻译：存储电路及其控制方法
公开(公告)号：US08665663B2
公开(公告)日：2014-03-04
申请号：US13095153
申请日：2011-04-27
申请人： Kallol Mazumder , Scott E. Smith
发明人： Kallol Mazumder , Scott E. Smith
IPC分类号： G11C7/22
CPC分类号： G11C7/222 , G11C7/02 , G11C7/1057 , G11C7/1066 , G11C7/1084 , G11C7/1093
摘要： A memory circuit according to one embodiment of the present invention includes a clock driver and an ODT timer. The clock driver is configured to provide a system clock signal based on a root clock signal when the memory circuit is in a read mode, and is configured to stop providing the system clock signal when the memory circuit is not in the read mode. The ODT timer is configured to provide a system ODT signal when the memory circuit is not in the read mode, wherein the transition edge of the system ODT signal is aligned with the transition edge of the root clock signal.
摘要翻译：根据本发明的一个实施例的存储器电路包括时钟驱动器和ODT定时器。时钟驱动器被配置为当存储器电路处于读取模式时基于根时钟信号提供系统时钟信号，并且被配置为在存储器电路不处于读取模式时停止提供系统时钟信号。 ODT定时器被配置为当存储器电路不处于读取模式时提供系统ODT信号，其中系统ODT信号的转换边沿与根时钟信号的转换边沿对准。

2. 发明申请

US20130163713A1 METHODS, APPARATUSES, AND CIRCUITS FOR BIMODAL DISABLE CIRCUITS 有权
标题翻译：双向禁用电路的方法，装置和电路
公开(公告)号：US20130163713A1
公开(公告)日：2013-06-27
申请号：US13333850
申请日：2011-12-21
申请人： Eric Booth , Tyler Gomm , Kallol Mazumder , Scott E. Smith , John F. Schreck
发明人： Eric Booth , Tyler Gomm , Kallol Mazumder , Scott E. Smith , John F. Schreck
IPC分类号： G06M11/00 , H03K17/00
CPC分类号： H03L1/00 , G06F1/10 , H03K5/132 , H03K5/133 , H03K21/38
摘要： Circuits, integrated circuits, and methods are disclosed for bimodal disable circuits. In one such example method, a counter is maintained, with the counter indicating a logic level at which an output signal will be disabled during at least a portion of one of a plurality of disable cycles. The logic level indicated by the counter is transitioned. An input signal is provided as the output signal responsive to the enable signal indicating that the output signal is to be enabled, and the output signal is disabled at the logic level indicated by the counter responsive to the enable signal indicating that the output signal is to be disabled.
摘要翻译：公开了用于双模禁止电路的电路，集成电路和方法。在一个这样的示例性方法中，维持计数器，其中计数器指示在多个禁用周期中的至少一个的至少一部分期间输出信号将被禁用的逻辑电平。由计数器指示的逻辑电平转换。响应于指示输出信号被使能的使能信号，输出信号被提供作为输出信号，并且输出信号在由计数器指示的逻辑电平处被禁用，响应于使能信号，指示输出信号为被禁用

3. 发明申请

US20090195287A1 APPARATUS AND METHOD FOR EXTERNAL TO INTERNAL CLOCK GENERATION 有权
标题翻译：用于外部时钟产生的装置和方法
公开(公告)号：US20090195287A1
公开(公告)日：2009-08-06
申请号：US12027124
申请日：2008-02-06
申请人： Michael V. Ho , Tyler J. Gomm , Scott E. Smith
发明人： Michael V. Ho , Tyler J. Gomm , Scott E. Smith
IPC分类号： G06F1/06 , G06F1/04
CPC分类号： G06F1/12 , G06F1/06
摘要： A phase recombination circuit includes a first phase input and a first one-shot pulse generator adapted to receive the first phase input and produce a first signal to pull a signal to a first state. The phase recombination circuit also includes a second phase input in phase relationship with the first phase input, and a second one-shot pulse generator adapted to receive the second phase input and produce a second signal to pull a signal to a second state.
摘要翻译：相位复合电路包括第一相位输入和第一单触发脉冲发生器，其适于接收第一相位输入并产生第一信号以将信号拉至第一状态。相位复合电路还包括与第一相位输入相位关系的第二相位输入，以及适于接收第二相位输入并产生第二信号以将信号拉至第二状态的第二单触发脉冲发生器。

4. 发明授权

US07482855B2 Circuit and method for stable fuse detection 有权
标题翻译：用于稳定保险丝检测的电路和方法
公开(公告)号：US07482855B2
公开(公告)日：2009-01-27
申请号：US11897244
申请日：2007-08-29
申请人： Christian N. Mohr , Scott E. Smith
发明人： Christian N. Mohr , Scott E. Smith
IPC分类号： H01H37/76
CPC分类号： G11C17/18
摘要： A fuse state detection circuit is comprised of a first fuse element, a second fuse element, and an output for carrying an output signal, the output signal represents a first logic state when the first fuse element is blown and the second fuse element is unblown and the output signal represents a second logic state when the first element is unblown and the second element is blown. The fuse state detection circuit produces an output signal whose state is recoverable from a negative triggering event and is capable of resolving itself to the correct state without the need for a reset pulse. Methods of using the fuse state detection circuit, such as a method of using fuse elements to control a setting within an electronic circuit, the improvement comprising using a pair of fuse elements to control a single setting, are also given.
摘要翻译：熔丝状态检测电路包括第一熔丝元件，第二熔丝元件和用于承载输出信号的输出端，所述输出信号表示当第一熔丝元件被吹制而第二熔丝元件未被吹出时的第一逻辑状态，当第一元件未吹出并且第二元件被吹动时，输出信号表示第二逻辑状态。熔丝状态检测电路产生其状态可从负触发事件中恢复的输出信号，并且能够将其自身解析为正确状态而无需复位脉冲。还提供了使用熔丝状态检测电路的方法，例如使用熔丝元件来控制电子电路内的设置的方法，包括使用一对熔丝元件来控制单个设置的改进。

5. 发明授权

US07276955B2 Circuit and method for stable fuse detection 有权
标题翻译：用于稳定保险丝检测的电路和方法
公开(公告)号：US07276955B2
公开(公告)日：2007-10-02
申请号：US11106100
申请日：2005-04-14
申请人： Christian N. Mohr , Scott E. Smith
发明人： Christian N. Mohr , Scott E. Smith
IPC分类号： H01H37/76
CPC分类号： G11C17/18
摘要： A fuse state detection circuit is comprised of a first fuse element, a second fuse element, and an output for carrying an output signal, the output signal represents a first logic state when the first fuse element is blown and the second fuse element is unblown and the output signal represents a second logic state when the first element is unblown and the second element is blown. The fuse state detection circuit produces an output signal whose state is recoverable from a negative triggering event and is capable of resolving itself to the correct state without the need for a reset pulse. Methods of using the fuse state detection circuit, such as a method of using fuse elements to control a setting within an electronic circuit, the improvement comprising using a pair of fuse elements to control a single setting, are also given.
摘要翻译：熔丝状态检测电路包括第一熔丝元件，第二熔丝元件和用于承载输出信号的输出端，所述输出信号表示当第一熔丝元件被吹制而第二熔丝元件未被吹出时的第一逻辑状态，当第一元件未吹出并且第二元件被吹动时，输出信号表示第二逻辑状态。熔丝状态检测电路产生其状态可从负触发事件中恢复的输出信号，并且能够将其自身解析为正确状态而无需复位脉冲。还提供了使用熔丝状态检测电路的方法，例如使用熔丝元件来控制电子电路内的设置的方法，包括使用一对熔丝元件来控制单个设置的改进。

6. 发明授权

US07145817B2 Reduced power redundancy address decoder and comparison circuit 有权
标题翻译：减少冗余地址解码器和比较电路
公开(公告)号：US07145817B2
公开(公告)日：2006-12-05
申请号：US11015703
申请日：2004-12-17
申请人： Christian N. Mohr , Scott E. Smith
发明人： Christian N. Mohr , Scott E. Smith
IPC分类号： G11C7/00
CPC分类号： G11C29/83 , G11C29/844
摘要： A redundancy address decoder for a memory having at least one bank of memory segmented into a plurality of memory blocks. The redundancy address decoder includes a plurality of redundancy comparison circuitry coupled to a respective programmable element block storing addresses that are mapped to redundant memory of a memory plane. The redundancy address decoder further includes redundancy driver select logic coupled to each of the redundancy comparison circuitry to activate a selected one of the redundancy comparison circuitry for comparing a portion of a memory address corresponding to a memory location with the programmed addresses of the respective programmable element blocks, which leads to power reduction for column accesses to the memory device. The selection of the redundancy driver is based on the memory bank in which the memory location is located.
摘要翻译：一种用于存储器的冗余地址解码器，其具有被分割成多个存储块的至少一组存储器。冗余地址解码器包括耦合到存储映射到存储器平面的冗余存储器的地址的相应可编程元件块的多个冗余比较电路。冗余地址解码器还包括耦合到冗余比较电路中的每一个的冗余驱动器选择逻辑，以激活冗余比较电路中的所选择的一个，用于将对应于存储器位置的存储器地址的一部分与相应可编程元件的编程地址进行比较块，这导致对存储器设备的列访问的功率降低。冗余驱动器的选择基于存储器位置所在的存储体。

7. 发明授权

US06546510B1 Burn-in mode detect circuit for semiconductor device 有权
标题翻译：半导体器件的老化模式检测电路
公开(公告)号：US06546510B1
公开(公告)日：2003-04-08
申请号：US09351384
申请日：1999-07-13
申请人： Kallol Mazumder , Scott E. Smith , Francis Hii
发明人： Kallol Mazumder , Scott E. Smith , Francis Hii
IPC分类号： G11C2900
CPC分类号： G11C29/50 , G11C11/401 , G11C29/38 , G11C29/46
摘要： A synchronous dynamic random access memory (SDRAM) is disclosed that includes an operational mode in which the functionality of the SDRAM can be tested under burn-in conditions. The SDRAM can be placed in a burn-in monitor mode in which burn-in information is provided at data outputs, in lieu of memory cell information. The burn-in monitor mode helps to ensure that the SDRAM functions are properly exercised during burn-in. The preferred embodiment includes a data buffer coupled to a data bus and a mode register. The mode register stores burn-in mode data. In a standard mode of operation, the data buffer couples the data bus to data outputs (D0-Dz). In a burn-in monitor mode of operation, the data buffer couples the burn-in mode data to the data outputs (D0-Dz).
摘要翻译：公开了一种同步动态随机存取存储器（SDRAM），其包括可在老化条件下测试SDRAM功能的操作模式。可以将SDRAM放置在老化监视器模式中，其中在数据输出端提供老化信息，代替存储器单元信息。老化监视器模式有助于确保在老化期间SDRAM功能被正确地运行。优选实施例包括耦合到数据总线和模式寄存器的数据缓冲器。模式寄存器存储老化模式数据。在标准操作模式下，数据缓冲器将数据总线耦合到数据输出（D0-Dz）。在老化监视器操作模式下，数据缓冲器将老化模式数据耦合到数据输出（D0-Dz）。

8. 发明授权

US06242936B1 Circuit for driving conductive line and testing conductive line for current leakage 有权
标题翻译：用于驱动导线的电路和测试导线用于漏电
公开(公告)号：US06242936B1
公开(公告)日：2001-06-05
申请号：US09366232
申请日：1999-08-03
申请人： Michael Duc Ho , Duy-Loan T. Le , Scott E. Smith
发明人： Michael Duc Ho , Duy-Loan T. Le , Scott E. Smith
IPC分类号： G01R3126
CPC分类号： G01R31/3004
摘要： A circuit (100) that drives word lines and tests a word line (102) in a semiconductor device is disclosed. A charge circuit (108) couples a supply voltage (VPP) to a charge node (106) according to a potential at a boot node (110). The charge node (106) supplies a charge voltage for the word line (102). In a standard cycle, the boot node (110) is charged to a high voltage, and maintained at the high potential, to keep the word line (102) charged. In a test cycle, the boot node (110) is charged to a high voltage, and then discharged to a low voltage, thereby isolating the charge node (106) and the word line (102). In the event the word line (102) suffers from current leakage, a drop in potential will be detected at the charge rode (106).
摘要翻译：公开了一种在半导体器件中驱动字线并测试字线（102）的电路（100）。充电电路（108）根据引导节点（110）处的电位将电源电压（VPP）耦合到充电节点（106）。充电节点（106）为字线（102）提供充电电压。在标准周期中，引导节点（110）被充电到高电压并保持在高电位，以保持字线（102）充电。在测试周期中，引导节点（110）被充电到高电压，然后被放电到低电压，从而隔离充电节点（106）和字线（102）。在字线（102）遇到电流泄漏的情况下，在充电路径（106）处将检测到电位下降。

9. 发明授权

US06201752B1 Timing circuit for high voltage testing 有权
标题翻译：高电压测试定时电路
公开(公告)号：US06201752B1
公开(公告)日：2001-03-13
申请号：US09398240
申请日：1999-09-20
申请人： Anh Bui , Scott E. Smith , Duy-Loan T. Le
发明人： Anh Bui , Scott E. Smith , Duy-Loan T. Le
IPC分类号： G11C700
CPC分类号： C07H13/06 , C07H15/18 , C07H17/08 , C07H19/16 , G11C5/143 , G11C7/1072 , G11C11/401 , G11C29/028 , G11C29/50 , G11C29/50012
摘要： A circuit is designed with a detector circuit (700) coupled between a supply voltage terminal (705) and a reference voltage terminal (755). The detector circuit produces a first control signal in response to a detected mode and produces a second control signal in response to another mode. A first circuit (205, 207) including a delay circuit receives the first control signal and a third control signal. The delay circuit produces a fourth control signal at an output terminal (215) in response to the first and third control signals. A second circuit (203) receives the second control signal and the third control signal. The second circuit produces the fourth control signal at the output terminal in response to the second and third control signals.
摘要翻译：电路设计有耦合在电源电压端（705）和参考电压端（755）之间的检测器电路（700）。检测器电路响应于检测模式产生第一控制信号，并且响应于另一模式产生第二控制信号。包括延迟电路的第一电路（205,207）接收第一控制信号和第三控制信号。延迟电路响应于第一和第三控制信号在输出端（215）产生第四控制信号。第二电路（203）接收第二控制信号和第三控制信号。第二电路响应于第二和第三控制信号在输出端产生第四控制信号。

10. 发明授权

US6134168A Circuit and method for internal refresh counter 有权
标题翻译：内部刷新计数器的电路和方法
公开(公告)号：US6134168A
公开(公告)日：2000-10-17
申请号：US327734
申请日：1999-06-08
申请人： Matthew R. Harrington , Steven C. Eplett , Kallol Mazumder , Scott E. Smith
发明人： Matthew R. Harrington , Steven C. Eplett , Kallol Mazumder , Scott E. Smith
IPC分类号： G11C11/406 , H03K23/00 , G11C7/00
CPC分类号： G11C11/406 , H03K23/004
摘要： A counter (450) for generating a series of binary addresses, each of the addresses including a set of one or more most-significant bits. The counter includes circuitry to generate the addresses, including the set of most-significant bits (402), in a first mode and circuitry to generate the addresses (400), excluding the set of most significant bits, in a second mode. The counter is operable to transition between the first and second modes. The counter also includes circuitry to generate the addresses in the first mode in a non-binary count order in which the set of most-significant address bits is a set of least-significant bits in the count order.
摘要翻译：一种用于产生一系列二进制地址的计数器（450），每个地址包括一个或多个最高有效位的集合。计数器包括用于在第一模式中产生包括最高有效位组（402）的地址的电路，以及在第二模式中生成不包括最高有效位集合的地址（400）的电路。计数器可操作以在第一和第二模式之间转换。计数器还包括用于以非二进制计数顺序在第一模式中产生地址的电路，其中最高有效地址位集合是计数次序中的一组最低有效位。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式