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1. 发明授权

US09118309B2 Shifter can avoid utilizing partial pulse 有权
标题翻译：移位器可以避免使用部分脉冲
公开(公告)号：US09118309B2
公开(公告)日：2015-08-25
申请号：US13654421
申请日：2012-10-18
申请人： Kallol Mazumder , Scott Smith
发明人： Kallol Mazumder , Scott Smith
IPC分类号： H03K3/00 , H03K3/037
CPC分类号： H03K3/0375
摘要： A shifter that can avoid utilizing a partial pulse, comprising: at least one shifting stage, for receiving an external clock signal or a command triggering clock signal to generate sampling signals according a command signal; and a command triggering clock signal generating circuit, for generating the command triggering clock signal according to the command signal. The shifting stage utilizes the external clock signal to generate the sampling signal but does not utilize the command triggering clock signal to generate the sampling signal, if the command triggering clock signal may have a partial pulse for a cycle that the shifting stage generates the sampling signal.
摘要翻译：一种可以避免利用部分脉冲的移位器，包括：至少一个移位级，用于接收外部时钟信号或触发时钟信号的命令以根据命令信号产生采样信号; 以及命令触发时钟信号发生电路，用于根据命令信号产生命令触发时钟信号。移位级利用外部时钟信号产生采样信号，但是如果命令触发时钟信号可能具有偏移级产生采样信号的周期的部分脉冲，则不利用指令触发时钟信号来产生采样信号。

2. 发明申请

US20140111263A1 SHIFTER CAN AVOID UTILIZING PARTIAL PULSE 有权
标题翻译：更换可避免使用部分脉冲
公开(公告)号：US20140111263A1
公开(公告)日：2014-04-24
申请号：US13654421
申请日：2012-10-18
申请人： Kallol Mazumder , Scott Smith
发明人： Kallol Mazumder , Scott Smith
IPC分类号： G06F1/04 , H03K3/0233
CPC分类号： H03K3/0375
摘要： A shifter that can avoid utilizing a partial pulse, comprising: at least one shifting stage, for receiving an external clock signal or a command triggering clock signal to generate sampling signals according a command signal; and a command triggering clock signal generating circuit, for generating the command triggering clock signal according to the command signal. The shifting stage utilizes the external clock signal to generate the sampling signal but does not utilize the command triggering clock signal to generate the sampling signal, if the command triggering clock signal may have a partial pulse for a cycle that the shifting stage generates the sampling signal.
摘要翻译：一种可以避免利用部分脉冲的移位器，包括：至少一个移位级，用于接收外部时钟信号或触发时钟信号的命令以根据命令信号产生采样信号; 以及命令触发时钟信号发生电路，用于根据命令信号产生命令触发时钟信号。移位级利用外部时钟信号产生采样信号，但是如果命令触发时钟信号可能具有偏移级产生采样信号的周期的部分脉冲，则不利用指令触发时钟信号来产生采样信号。

3. 发明申请

US20130342254A1 APPARATUSES AND METHODS FOR ADJUSTING A MINIMUM FORWARD PATH DELAY OF A SIGNAL PATH 有权
标题翻译：调整信号路径最小前进路径延迟的装置和方法
公开(公告)号：US20130342254A1
公开(公告)日：2013-12-26
申请号：US13531341
申请日：2012-06-22
申请人： Kallol Mazumder , Jongtae Kwak , Tsugio Takahashi , Yasuo Satoh
发明人： Kallol Mazumder , Jongtae Kwak , Tsugio Takahashi , Yasuo Satoh
IPC分类号： H03H11/26
CPC分类号： H03H11/26
摘要： Apparatuses and methods related to adjusting a minimum forward path delay of a signal path are disclosed. One such signal path includes a signal path having a minimum forward path delay, wherein the signal path is configured to adjust the minimum forward path delay based at least in part on a selected latency and a propagation delay of the minimum forward path delay. An example method includes reducing a forward path delay of a command path by at least one clock cycle of a clock signal to provide a command according to a selected latency responsive to a count value representative of a minimum forward path delay of the command path being greater than a maximum count value for the selected latency.
摘要翻译：公开了与调整信号路径的最小前向路径延迟相关的装置和方法。一个这样的信号路径包括具有最小正向路径延迟的信号路径，其中信号路径被配置为至少部分地基于所选等待时间和最小前向路径延迟的传播延迟来调整最小前向路径延迟。一个示例性方法包括：通过时钟信号的至少一个时钟周期来减少命令路径的前向路径延迟，以根据表示命令路径的最小前向路径延迟的计数值的选定延迟来提供命令更大比所选延迟的最大计数值。

4. 发明授权

US08519767B2 Methods, apparatuses, and circuits for bimodal disable circuits 有权
公开(公告)号：US08519767B2
公开(公告)日：2013-08-27
申请号：US13333850
申请日：2011-12-21
申请人： Eric Booth , Tyler Gomm , Kallol Mazumder , Scott E. Smith , John F. Schreck
发明人： Eric Booth , Tyler Gomm , Kallol Mazumder , Scott E. Smith , John F. Schreck
IPC分类号： H03K3/00
CPC分类号： H03L1/00 , G06F1/10 , H03K5/132 , H03K5/133 , H03K21/38
摘要： Circuits, integrated circuits, and methods are disclosed for bimodal disable circuits. In one such example method, a counter is maintained, with the counter indicating a logic level at which an output signal will be disabled during at least a portion of one of a plurality of disable cycles. The logic level indicated by the counter is transitioned. An input signal is provided as the output signal responsive to the enable signal indicating that the output signal is to be enabled, and the output signal is disabled at the logic level indicated by the counter responsive to the enable signal indicating that the output signal is to be disabled.

5. 发明申请

US20130194013A1 APPARATUSES AND METHODS FOR ALTERING A FORWARD PATH DELAY OF A SIGNAL PATH 有权
标题翻译：用于改变信号路径的前进路径延迟的装置和方法
公开(公告)号：US20130194013A1
公开(公告)日：2013-08-01
申请号：US13364198
申请日：2012-02-01
申请人： Jongtae Kwak , Kallol Mazumder
发明人： Jongtae Kwak , Kallol Mazumder
IPC分类号： H03L7/18
CPC分类号： H03L7/08 , H03L7/0816
摘要： Apparatuses and methods related to altering the timing of command signals for executing commands is disclosed. One such method includes calculating a forward path delay of a clock circuit in terms of a number of clock cycles of an output clock signal provided by the clock circuit and adding a number of additional clock cycles of delay to a forward path delay of a signal path. The forward path delay of the clock circuit is representative of the forward path delay of the signal path and the number of additional clock cycles is based at least in part on the number of clock cycles of forward path delay.
摘要翻译：公开了与改变用于执行命令的命令信号的定时相关的装置和方法。一种这样的方法包括根据由时钟电路提供的输出时钟信号的时钟周期的数量来计算时钟电路的前向路径延迟，并将多个延迟的附加时钟周期与信号路径的前向路径延迟相加。时钟电路的正向路径延迟表示信号路径的前向路径延迟，并且附加时钟周期的数量至少部分地基于前向路径延迟的时钟周期数。

6. 发明授权

US5999473A Circuit and method for internal refresh counter 失效
公开(公告)号：US5999473A
公开(公告)日：1999-12-07
申请号：US63506
申请日：1998-04-21
申请人： Matthew R. Harrington , Steven C. Eplett , Kallol Mazumder , Scott E. Smith
发明人： Matthew R. Harrington , Steven C. Eplett , Kallol Mazumder , Scott E. Smith
IPC分类号： G11C11/406 , H03K23/00 , G11C7/00
CPC分类号： H03K23/004 , G11C11/406
摘要： A counter (450) for generating a series of binary addresses, each of the addresses including a set of one or more most-significant bits. The counter includes circuitry to generate the addresses, including the set of most-significant bits (402), in a first mode and circuitry to generate the addresses (400), excluding the set of most significant bits, in a second mode. The counter is operable to transition between the first and second modes. The counter also includes circuitry to generate the addresses in the first mode in a non-binary count order in which the set of most-significant address bits is a set of least-significant bits in the count order.

7. 发明授权

US09088268B2 Invalid signal filtering method and shifter utilizing the method 有权
标题翻译：无效的信号滤波方法和移位器利用该方法
公开(公告)号：US09088268B2
公开(公告)日：2015-07-21
申请号：US13531580
申请日：2012-06-24
申请人： Kallol Mazumder
发明人： Kallol Mazumder
IPC分类号： H04L25/03 , G11C7/22 , H03H11/40
CPC分类号： H03H11/40 , G11C7/22 , G11C19/00 , G11C19/28
摘要： A shifter with invalid signal filtering mechanism, comprising: a first shifting stage, for receiving and capturing an input signal in a first clock cycle; and a second shifting stage, after the first shifting stage, for receiving the input signal from the first shifting stage, and for receiving a validity signal indicating whether the input signal is valid or invalid, before a second clock cycle next to the first clock cycle occurs; wherein the second shifting stage captures the input signal transmitted from the first shifting stage if the validity signal indicates that the input signal is valid, where the second shifting stage does not capture the input signal transmitted from the first shifting stage if the validity signal indicates that the input signal is invalid.
摘要翻译：一种具有无效信号滤波机构的移位器，包括：第一移位级，用于在第一时钟周期中接收和捕获输入信号; 以及在第一移位级之后的第二移位级，用于在第一时钟周期之后的第二时钟周期之前接收来自第一移位级的输入信号，并且用于接收指示输入信号是有效还是无效的有效信号发生; 其中，如果有效信号指示输入信号有效，则第二移位级捕获从第一移位级发送的输入信号，其中如果有效信号指示第二移位级没有捕获从第一移位级发送的输入信号，输入信号无效。

8. 发明授权

US09054675B2 Apparatuses and methods for adjusting a minimum forward path delay of a signal path 有权
标题翻译：用于调整信号路径的最小前进路径延迟的装置和方法
公开(公告)号：US09054675B2
公开(公告)日：2015-06-09
申请号：US13531341
申请日：2012-06-22
申请人： Kallol Mazumder , Jongtae Kwak , Tsugio Takahashi , Yasuo Satoh
发明人： Kallol Mazumder , Jongtae Kwak , Tsugio Takahashi , Yasuo Satoh
IPC分类号： H03H11/26
CPC分类号： H03H11/26
摘要： Apparatuses and methods related to adjusting a minimum forward path delay of a signal path are disclosed. One such signal path includes a signal path having a minimum forward path delay, wherein the signal path is configured to adjust the minimum forward path delay based at least in part on a selected latency and a propagation delay of the minimum forward path delay. An example method includes reducing a forward path delay of a command path by at least one clock cycle of a clock signal to provide a command according to a selected latency responsive to a count value representative of a minimum forward path delay of the command path being greater than a maximum count value for the selected latency.
摘要翻译：公开了与调整信号路径的最小前向路径延迟相关的装置和方法。一个这样的信号路径包括具有最小正向路径延迟的信号路径，其中信号路径被配置为至少部分地基于所选等待时间和最小前向路径延迟的传播延迟来调整最小前向路径延迟。一个示例性方法包括：通过时钟信号的至少一个时钟周期来减少命令路径的前向路径延迟，以根据表示命令路径的最小前向路径延迟的计数值的选定延迟来提供命令更大比所选延迟的最大计数值。

9. 发明申请

US20130342239A1 INVALID SIGNAL FILTERING METHOD AND SHIFTER UTILIZING THE METHOD 有权
标题翻译：无效信号滤波方法及其应用
公开(公告)号：US20130342239A1
公开(公告)日：2013-12-26
申请号：US13531580
申请日：2012-06-24
申请人： Kallol Mazumder
发明人： Kallol Mazumder
IPC分类号： H04L1/00
CPC分类号： H03H11/40 , G11C7/22 , G11C19/00 , G11C19/28
摘要： A shifter with invalid signal filtering mechanism, comprising: a first shifting stage, for receiving and capturing an input signal in a first clock cycle; and a second shifting stage, after the first shifting stage, for receiving the input signal from the first shifting stage, and for receiving a validity signal indicating whether the input signal is valid or invalid, before a second clock cycle next to the first clock cycle occurs; wherein the second shifting stage captures the input signal transmitted from the first shifting stage if the validity signal indicates that the input signal is valid, where the second shifting stage does not capture the input signal transmitted from the first shifting stage if the validity signal indicates that the input signal is invalid.
摘要翻译：一种具有无效信号滤波机构的移位器，包括：第一移位级，用于在第一时钟周期中接收和捕获输入信号; 以及在第一移位级之后的第二移位级，用于在第一时钟周期之后的第二时钟周期之前接收来自第一移位级的输入信号，并且用于接收指示输入信号是有效还是无效的有效信号发生; 其中，如果有效信号指示输入信号有效，则第二移位级捕获从第一移位级发送的输入信号，其中如果有效信号指示第二移位级没有捕获从第一移位级发送的输入信号，输入信号无效。

10. 发明申请

US20120275238A1 MEMORY CIRCUIT AND CONTROL METHOD THEREOF 有权
标题翻译：存储器电路及其控制方法
公开(公告)号：US20120275238A1
公开(公告)日：2012-11-01
申请号：US13095153
申请日：2011-04-27
申请人： Kallol Mazumder , Scott E. Smith
发明人： Kallol Mazumder , Scott E. Smith
IPC分类号： G11C7/10 , G11C8/18 , G11C7/00
CPC分类号： G11C7/222 , G11C7/02 , G11C7/1057 , G11C7/1066 , G11C7/1084 , G11C7/1093
摘要： A memory circuit according to one embodiment of the present invention includes a clock driver and an ODT timer. The clock driver is configured to provide a system clock signal based on a root clock signal when the memory circuit is in a read mode, and is configured to stop providing the system clock signal when the memory circuit is not in the read mode. The ODT timer is configured to provide a system ODT signal when the memory circuit is not in the read mode, wherein the transition edge of the system ODT signal is aligned with the transition edge of the root clock signal.
摘要翻译：根据本发明的一个实施例的存储器电路包括时钟驱动器和ODT定时器。时钟驱动器被配置为当存储器电路处于读取模式时基于根时钟信号提供系统时钟信号，并且被配置为在存储器电路不处于读取模式时停止提供系统时钟信号。 ODT定时器被配置为当存储器电路不处于读取模式时提供系统ODT信号，其中系统ODT信号的转换边沿与根时钟信号的转换边沿对准。

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