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1. 发明授权

US06546510B1 Burn-in mode detect circuit for semiconductor device 有权
标题翻译：半导体器件的老化模式检测电路
公开(公告)号：US06546510B1
公开(公告)日：2003-04-08
申请号：US09351384
申请日：1999-07-13
申请人： Kallol Mazumder , Scott E. Smith , Francis Hii
发明人： Kallol Mazumder , Scott E. Smith , Francis Hii
IPC分类号： G11C2900
CPC分类号： G11C29/50 , G11C11/401 , G11C29/38 , G11C29/46
摘要： A synchronous dynamic random access memory (SDRAM) is disclosed that includes an operational mode in which the functionality of the SDRAM can be tested under burn-in conditions. The SDRAM can be placed in a burn-in monitor mode in which burn-in information is provided at data outputs, in lieu of memory cell information. The burn-in monitor mode helps to ensure that the SDRAM functions are properly exercised during burn-in. The preferred embodiment includes a data buffer coupled to a data bus and a mode register. The mode register stores burn-in mode data. In a standard mode of operation, the data buffer couples the data bus to data outputs (D0-Dz). In a burn-in monitor mode of operation, the data buffer couples the burn-in mode data to the data outputs (D0-Dz).
摘要翻译：公开了一种同步动态随机存取存储器（SDRAM），其包括可在老化条件下测试SDRAM功能的操作模式。可以将SDRAM放置在老化监视器模式中，其中在数据输出端提供老化信息，代替存储器单元信息。老化监视器模式有助于确保在老化期间SDRAM功能被正确地运行。优选实施例包括耦合到数据总线和模式寄存器的数据缓冲器。模式寄存器存储老化模式数据。在标准操作模式下，数据缓冲器将数据总线耦合到数据输出（D0-Dz）。在老化监视器操作模式下，数据缓冲器将老化模式数据耦合到数据输出（D0-Dz）。

2. 发明授权

US08519767B2 Methods, apparatuses, and circuits for bimodal disable circuits 有权
公开(公告)号：US08519767B2
公开(公告)日：2013-08-27
申请号：US13333850
申请日：2011-12-21
申请人： Eric Booth , Tyler Gomm , Kallol Mazumder , Scott E. Smith , John F. Schreck
发明人： Eric Booth , Tyler Gomm , Kallol Mazumder , Scott E. Smith , John F. Schreck
IPC分类号： H03K3/00
CPC分类号： H03L1/00 , G06F1/10 , H03K5/132 , H03K5/133 , H03K21/38
摘要： Circuits, integrated circuits, and methods are disclosed for bimodal disable circuits. In one such example method, a counter is maintained, with the counter indicating a logic level at which an output signal will be disabled during at least a portion of one of a plurality of disable cycles. The logic level indicated by the counter is transitioned. An input signal is provided as the output signal responsive to the enable signal indicating that the output signal is to be enabled, and the output signal is disabled at the logic level indicated by the counter responsive to the enable signal indicating that the output signal is to be disabled.

3. 发明申请

US20120275238A1 MEMORY CIRCUIT AND CONTROL METHOD THEREOF 有权
标题翻译：存储器电路及其控制方法
公开(公告)号：US20120275238A1
公开(公告)日：2012-11-01
申请号：US13095153
申请日：2011-04-27
申请人： Kallol Mazumder , Scott E. Smith
发明人： Kallol Mazumder , Scott E. Smith
IPC分类号： G11C7/10 , G11C8/18 , G11C7/00
CPC分类号： G11C7/222 , G11C7/02 , G11C7/1057 , G11C7/1066 , G11C7/1084 , G11C7/1093
摘要： A memory circuit according to one embodiment of the present invention includes a clock driver and an ODT timer. The clock driver is configured to provide a system clock signal based on a root clock signal when the memory circuit is in a read mode, and is configured to stop providing the system clock signal when the memory circuit is not in the read mode. The ODT timer is configured to provide a system ODT signal when the memory circuit is not in the read mode, wherein the transition edge of the system ODT signal is aligned with the transition edge of the root clock signal.
摘要翻译：根据本发明的一个实施例的存储器电路包括时钟驱动器和ODT定时器。时钟驱动器被配置为当存储器电路处于读取模式时基于根时钟信号提供系统时钟信号，并且被配置为在存储器电路不处于读取模式时停止提供系统时钟信号。 ODT定时器被配置为当存储器电路不处于读取模式时提供系统ODT信号，其中系统ODT信号的转换边沿与根时钟信号的转换边沿对准。

4. 发明授权

US5999473A Circuit and method for internal refresh counter 失效
公开(公告)号：US5999473A
公开(公告)日：1999-12-07
申请号：US63506
申请日：1998-04-21
申请人： Matthew R. Harrington , Steven C. Eplett , Kallol Mazumder , Scott E. Smith
发明人： Matthew R. Harrington , Steven C. Eplett , Kallol Mazumder , Scott E. Smith
IPC分类号： G11C11/406 , H03K23/00 , G11C7/00
CPC分类号： H03K23/004 , G11C11/406
摘要： A counter (450) for generating a series of binary addresses, each of the addresses including a set of one or more most-significant bits. The counter includes circuitry to generate the addresses, including the set of most-significant bits (402), in a first mode and circuitry to generate the addresses (400), excluding the set of most significant bits, in a second mode. The counter is operable to transition between the first and second modes. The counter also includes circuitry to generate the addresses in the first mode in a non-binary count order in which the set of most-significant address bits is a set of least-significant bits in the count order.

5. 发明授权

US08665663B2 Memory circuit and control method thereof 有权
标题翻译：存储电路及其控制方法
公开(公告)号：US08665663B2
公开(公告)日：2014-03-04
申请号：US13095153
申请日：2011-04-27
申请人： Kallol Mazumder , Scott E. Smith
发明人： Kallol Mazumder , Scott E. Smith
IPC分类号： G11C7/22
CPC分类号： G11C7/222 , G11C7/02 , G11C7/1057 , G11C7/1066 , G11C7/1084 , G11C7/1093
摘要： A memory circuit according to one embodiment of the present invention includes a clock driver and an ODT timer. The clock driver is configured to provide a system clock signal based on a root clock signal when the memory circuit is in a read mode, and is configured to stop providing the system clock signal when the memory circuit is not in the read mode. The ODT timer is configured to provide a system ODT signal when the memory circuit is not in the read mode, wherein the transition edge of the system ODT signal is aligned with the transition edge of the root clock signal.
摘要翻译：根据本发明的一个实施例的存储器电路包括时钟驱动器和ODT定时器。时钟驱动器被配置为当存储器电路处于读取模式时基于根时钟信号提供系统时钟信号，并且被配置为在存储器电路不处于读取模式时停止提供系统时钟信号。 ODT定时器被配置为当存储器电路不处于读取模式时提供系统ODT信号，其中系统ODT信号的转换边沿与根时钟信号的转换边沿对准。

6. 发明申请

US20130163713A1 METHODS, APPARATUSES, AND CIRCUITS FOR BIMODAL DISABLE CIRCUITS 有权
标题翻译：双向禁用电路的方法，装置和电路
公开(公告)号：US20130163713A1
公开(公告)日：2013-06-27
申请号：US13333850
申请日：2011-12-21
申请人： Eric Booth , Tyler Gomm , Kallol Mazumder , Scott E. Smith , John F. Schreck
发明人： Eric Booth , Tyler Gomm , Kallol Mazumder , Scott E. Smith , John F. Schreck
IPC分类号： G06M11/00 , H03K17/00
CPC分类号： H03L1/00 , G06F1/10 , H03K5/132 , H03K5/133 , H03K21/38
摘要： Circuits, integrated circuits, and methods are disclosed for bimodal disable circuits. In one such example method, a counter is maintained, with the counter indicating a logic level at which an output signal will be disabled during at least a portion of one of a plurality of disable cycles. The logic level indicated by the counter is transitioned. An input signal is provided as the output signal responsive to the enable signal indicating that the output signal is to be enabled, and the output signal is disabled at the logic level indicated by the counter responsive to the enable signal indicating that the output signal is to be disabled.
摘要翻译：公开了用于双模禁止电路的电路，集成电路和方法。在一个这样的示例性方法中，维持计数器，其中计数器指示在多个禁用周期中的至少一个的至少一部分期间输出信号将被禁用的逻辑电平。由计数器指示的逻辑电平转换。响应于指示输出信号被使能的使能信号，输出信号被提供作为输出信号，并且输出信号在由计数器指示的逻辑电平处被禁用，响应于使能信号，指示输出信号为被禁用

7. 发明授权

US6134168A Circuit and method for internal refresh counter 有权
标题翻译：内部刷新计数器的电路和方法
公开(公告)号：US6134168A
公开(公告)日：2000-10-17
申请号：US327734
申请日：1999-06-08
申请人： Matthew R. Harrington , Steven C. Eplett , Kallol Mazumder , Scott E. Smith
发明人： Matthew R. Harrington , Steven C. Eplett , Kallol Mazumder , Scott E. Smith
IPC分类号： G11C11/406 , H03K23/00 , G11C7/00
CPC分类号： G11C11/406 , H03K23/004
摘要： A counter (450) for generating a series of binary addresses, each of the addresses including a set of one or more most-significant bits. The counter includes circuitry to generate the addresses, including the set of most-significant bits (402), in a first mode and circuitry to generate the addresses (400), excluding the set of most significant bits, in a second mode. The counter is operable to transition between the first and second modes. The counter also includes circuitry to generate the addresses in the first mode in a non-binary count order in which the set of most-significant address bits is a set of least-significant bits in the count order.
摘要翻译：一种用于产生一系列二进制地址的计数器（450），每个地址包括一个或多个最高有效位的集合。计数器包括用于在第一模式中产生包括最高有效位组（402）的地址的电路，以及在第二模式中生成不包括最高有效位集合的地址（400）的电路。计数器可操作以在第一和第二模式之间转换。计数器还包括用于以非二进制计数顺序在第一模式中产生地址的电路，其中最高有效地址位集合是计数次序中的一组最低有效位。

8. 发明授权

US6038177A Data pipeline interrupt scheme for preventing data disturbances 有权
标题翻译：用于防止数据干扰的数据流水线中断方案
公开(公告)号：US6038177A
公开(公告)日：2000-03-14
申请号：US253848
申请日：1999-02-22
申请人： M. Kumar Rajith , Kallol Mazumder , Scott E. Smith , Duy-Loan T. Le
发明人： M. Kumar Rajith , Kallol Mazumder , Scott E. Smith , Duy-Loan T. Le
IPC分类号： G11C7/10 , G11C16/04 , G11C8/00
CPC分类号： G11C7/1039 , G11C7/1051
摘要： A read mask circuit (300) is disclosed. A mask command is shifted through a series of mask latches (308 and 310) to generate the output-enable input (OE.sub.--) of an output driver (306). In synchronism with the mask command, data bits are shifted through a series of data latches (312 and 314) to the data input (DIN) of the output driver (306). To prevent a race condition between the mask command and the data bit that is to be masked (B3), the mask command, when latched in the second-to-last mask latch (308), is used to interrupt the last data latch (314). This prevents the to-be-masked data bit (B3) from being latched in the last data latch (314) and generating an undesirable output data transition by the output driver (306).
摘要翻译：公开了一种读掩模电路（300）。屏蔽命令通过一系列掩码锁存器（308和310）移位，以产生输出驱动器（306）的输出使能输入（OE-）。与掩模命令同步，数据位通过一系列数据锁存器（312和314）移动到输出驱动器（306）的数据输入（DIN）。为了防止掩码命令和要被屏蔽的数据位之间的竞争条件（B3），当锁存在第二到最后掩码锁存器（308）中时，掩码命令用于中断最后的数据锁存器 314）。这防止了被屏蔽的数据位（B3）被锁存在最后的数据锁存器（314）中，并且由输出驱动器（306）产生不期望的输出数据转换。

9. 发明授权

US09118309B2 Shifter can avoid utilizing partial pulse 有权
标题翻译：移位器可以避免使用部分脉冲
公开(公告)号：US09118309B2
公开(公告)日：2015-08-25
申请号：US13654421
申请日：2012-10-18
申请人： Kallol Mazumder , Scott Smith
发明人： Kallol Mazumder , Scott Smith
IPC分类号： H03K3/00 , H03K3/037
CPC分类号： H03K3/0375
摘要： A shifter that can avoid utilizing a partial pulse, comprising: at least one shifting stage, for receiving an external clock signal or a command triggering clock signal to generate sampling signals according a command signal; and a command triggering clock signal generating circuit, for generating the command triggering clock signal according to the command signal. The shifting stage utilizes the external clock signal to generate the sampling signal but does not utilize the command triggering clock signal to generate the sampling signal, if the command triggering clock signal may have a partial pulse for a cycle that the shifting stage generates the sampling signal.
摘要翻译：一种可以避免利用部分脉冲的移位器，包括：至少一个移位级，用于接收外部时钟信号或触发时钟信号的命令以根据命令信号产生采样信号; 以及命令触发时钟信号发生电路，用于根据命令信号产生命令触发时钟信号。移位级利用外部时钟信号产生采样信号，但是如果命令触发时钟信号可能具有偏移级产生采样信号的周期的部分脉冲，则不利用指令触发时钟信号来产生采样信号。

10. 发明申请

US20140111263A1 SHIFTER CAN AVOID UTILIZING PARTIAL PULSE 有权
标题翻译：更换可避免使用部分脉冲
公开(公告)号：US20140111263A1
公开(公告)日：2014-04-24
申请号：US13654421
申请日：2012-10-18
申请人： Kallol Mazumder , Scott Smith
发明人： Kallol Mazumder , Scott Smith
IPC分类号： G06F1/04 , H03K3/0233
CPC分类号： H03K3/0375
摘要： A shifter that can avoid utilizing a partial pulse, comprising: at least one shifting stage, for receiving an external clock signal or a command triggering clock signal to generate sampling signals according a command signal; and a command triggering clock signal generating circuit, for generating the command triggering clock signal according to the command signal. The shifting stage utilizes the external clock signal to generate the sampling signal but does not utilize the command triggering clock signal to generate the sampling signal, if the command triggering clock signal may have a partial pulse for a cycle that the shifting stage generates the sampling signal.
摘要翻译：一种可以避免利用部分脉冲的移位器，包括：至少一个移位级，用于接收外部时钟信号或触发时钟信号的命令以根据命令信号产生采样信号; 以及命令触发时钟信号发生电路，用于根据命令信号产生命令触发时钟信号。移位级利用外部时钟信号产生采样信号，但是如果命令触发时钟信号可能具有偏移级产生采样信号的周期的部分脉冲，则不利用指令触发时钟信号来产生采样信号。

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