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1. 发明授权

US5249214A Low skew CMOS clock divider 失效
标题翻译：低偏移CMOS时钟分频器
公开(公告)号：US5249214A
公开(公告)日：1993-09-28
申请号：US907252
申请日：1992-06-30
申请人： Richard W. Ulmer , James Ward
发明人： Richard W. Ulmer , James Ward
IPC分类号： H03K5/15
CPC分类号： H03K5/15066
摘要： A low-skew CMOS clock divider circuit for providing tracking of the divide-by-one and divide-by-two output signals obtained from a source of master clock pulses is fabricated using two matched flip-flops externally wired as divide-by-two devices. Coincidence gates are coupled with the outputs of the flip-flops to produce the desired divide-by-one and divide-by-two output signals in a manner such that the signals in each path pass through substantially identical circuit components, Thus, any delays encountered are the same in both circuit paths. In this manner, skew between the edges of the divide-by-two and divide-by-one clock signals is significantly reduced.
摘要翻译：用于提供对从主时钟脉冲源获得的分频和分频输出信号的跟踪的低偏移CMOS时钟分频器电路使用两个匹配的触发器，其被外部接线作为二分频设备。一致门与触发器的输出耦合以产生期望的分频和分频输出信号，使得每个路径中的信号通过基本上相同的电路组件。因此，任何延迟遇到的电路路径都相同。以这种方式，二分之一和一分之一时钟信号的边沿之间的偏差显着降低。

2. 发明授权

US4659944A High voltage detection circuit 失效
标题翻译：高电压检测电路
公开(公告)号：US4659944A
公开(公告)日：1987-04-21
申请号：US720789
申请日：1985-04-08
申请人： James A. Miller, Sr. , Robert N. Allgood , Richard W. Ulmer
发明人： James A. Miller, Sr. , Robert N. Allgood , Richard W. Ulmer
IPC分类号： H03K17/30 , H03K17/687 , H03K5/153
CPC分类号： H03K17/6872 , H03K17/302
摘要： A voltage detecting circuit is provided for generating an output signal when an input signal exceeds the power supply voltage by a predetermined amount. A reference current is established by an output stage using a first current mirror. A second current mirror is connected to the output stage and detects the input voltage level by forcing a greater or lesser amount of current through the output stage to provide a high or low level output voltage.
摘要翻译：提供电压检测电路，用于当输入信号超过电源电压预定量时产生输出信号。通过使用第一电流镜的输出级建立参考电流。第二电流镜连接到输出级，并且通过迫使输出级中的或多或少的电流来提供高电平或低电平的输出电压来检测输入电压电平。

3. 发明授权

US4383223A CMOS Operational amplifier employing push-pull output stage 失效
标题翻译： CMOS采用推挽输出级的运算放大器
公开(公告)号：US4383223A
公开(公告)日：1983-05-10
申请号：US138968
申请日：1980-04-10
申请人： Richard W. Ulmer
发明人： Richard W. Ulmer
IPC分类号： H03F3/30 , H03F3/45 , H03F3/26
CPC分类号： H03F3/45183 , H03F3/3001
摘要： A CMOS operational amplifier includes a biasing scheme for supplying current to a differential stage. A push-pull output stage includes a current sinking transistor which is coupled to a first output of the differential stage. A current mirror is coupled between a second output of the differential stage and the gate electrode of a current sourcing device in the output stage.
摘要翻译： CMOS运算放大器包括用于向差分级提供电流的偏置方案。推挽输出级包括耦合到差分级的第一输出的电流吸收晶体管。电流镜耦合在差分级的第二输出和输出级中的电流源装置的栅电极之间。

4. 发明授权

US4370632A Multiple function operational amplifier circuit 失效
标题翻译：多功能运算放大器电路
公开(公告)号：US4370632A
公开(公告)日：1983-01-25
申请号：US261848
申请日：1981-05-08
申请人： Robert N. Allgood , Stephen H. Kelley , Richard W. Ulmer , Henry Wurzburg
发明人： Robert N. Allgood , Stephen H. Kelley , Richard W. Ulmer , Henry Wurzburg
IPC分类号： H03F1/34 , H03F1/30 , H03H19/00 , H03M1/12 , H03H11/12
CPC分类号： H03F1/303 , H03H19/004
摘要： An operational amplifier capable of selectively performing a variety of circuit functions is provided. A single operational amplifier utilizes switched capacitors for sampling and holding an input signal, for establishing a low frequency pole, for applying the sample to an output capacitance to charge the capacitance and for comparing the input signal with a reference. The multi-function circuit provides a large savings in circuit area and permits versatility of circuit applications. One embodiment of the invention is to utilize a companding DAC having a capacitor array which may be used as the output capacitance of the operational amplifier circuit. The DAC provided utilizes an R ladder DAC coupled directly to a C DAC and has a switching structure that is simpler than comparable prior art circuits. The DAC is asynchronous and has programmable A-and Mu-255 law PCM conversion capability. Coupled directly to the C DAC is an operational amplifier receive filter circuit which utilizes the C DAC as an input capacitor thereby eliminating the need for a buffer amplifier and allowing the DAC to be used for both analog to digital and digital to analog conversion.
摘要翻译：提供能够选择性地执行各种电路功能的运算放大器。单个运算放大器利用开关电容器来采样和保持输入信号，用于建立低频极点，用于将采样施加到输出电容以对电容充电并将输入信号与参考值进行比较。多功能电路可大大节省电路面积，从而实现电路应用的多功能化。本发明的一个实施例是利用可以用作运算放大器电路的输出电容的电容器阵列的压扩DAC。提供的DAC使用直接耦合到C DAC的R梯形DAC，并且具有比可比现有技术电路简单的开关结构。 DAC是异步的，具有可编程的A和Mu-255法律PCM转换能力。直接耦合到C DAC是一个运算放大器接收滤波电路，它利用C DAC作为输入电容，从而无需使用缓冲放大器，并允许DAC用于模数转换和数模转换。

5. 发明授权

US4143362A High resolution auto-zero circuit for analog-to-digital converter 失效
标题翻译：用于模拟数字转换器的高分辨率自动调零电路
公开(公告)号：US4143362A
公开(公告)日：1979-03-06
申请号：US801112
申请日：1977-05-27
申请人： Richard W. Ulmer
发明人： Richard W. Ulmer
IPC分类号： H03M1/00 , H03K13/20
CPC分类号： H03M1/1019 , H03M1/52
摘要： An analog-to-digital converter includes an integrator which includes an amplifier having an offset voltage. A counter is responsive to a counter clock signal for counting during the duration of a first integration and transferring its count at the end of the first integration to a storage circuit. The counter is then reset. It then counts during the duration of a second integration. Coincidence circuitry is provided which causes the counter to be reset during the second integration when its count matches the count stored in the storage circuit. The counter then continues counting until the end of the second integration. The uncertainty associated with the count stored in the counter at the end of the second integration is improved by provision of a circuit responsive to the comparison signal and first and second clock signals for producing the counter clock signal. The counter clock signal is produced such that it is in phase with the first clock signal if the comparison signal at the end of the first integration occurred before the beginning of a subsequent pulse of the second clock signal. Otherwise, the third clock signal is delayed so that it is temporarily in phase with the second clock signal.

6. 发明授权

US5065042A Self-configuring clock interface circuit 失效
标题翻译：自配时钟接口电路
公开(公告)号：US5065042A
公开(公告)日：1991-11-12
申请号：US562064
申请日：1990-08-01
申请人： Joseph A. Thomsen , Richard W. Ulmer
发明人： Joseph A. Thomsen , Richard W. Ulmer
IPC分类号： H03K5/26
CPC分类号： H03K5/26
摘要： A self-configuring clock interface circuit automatically configures itself according to the type of clock input signals applied to two input terminals interconnected with the interface circuit. The system includes a pair of counters connected to the input terminals and having their outputs connected to the two inputs of an Exclusive NOR gate which acts as a control device for the system. The output of the exclusive NOR gate is coupled to a 2:1 multiplex to control the interconnection of one or the other of two inputs to the multiplex circuit with a clock output for the interface circuit.
摘要翻译：自配置时钟接口电路根据应用于与接口电路互连的两个输入端子的时钟输入信号的类型自动配置。该系统包括连接到输入端子的一对计数器，并且其输出端连接到作为该系统的控制装置的“异或”门的两个输入端。异或门的输出耦合到2：1多路复用，以便通过接口电路的时钟输出来控制多路复用电路的两个输入中的一个或另一个的互连。

7. 发明授权

US4477737A Voltage generator circuit having compensation for process and temperature variation 失效
标题翻译：电压发生器电路具有工艺和温度变化的补偿
公开(公告)号：US4477737A
公开(公告)日：1984-10-16
申请号：US398033
申请日：1982-07-14
申请人： Richard W. Ulmer , Roger A. Whatley
发明人： Richard W. Ulmer , Roger A. Whatley
IPC分类号： G05F3/24 , G05F1/58 , H03L1/04
CPC分类号： G05F3/245
摘要： An on-chip voltage generator circuit is disclosed having an output voltage which is reduced by a predetermined amount from a supply voltage. The output voltage is proportional to the gate-to-source voltages of two complementary transistors and varies with temperature and processing in a similar manner with digital circuitry on the chip for which the output voltage may be used to operate. A current source is used to provide a known current to the two complementary transistors and a buffer is used to provide a low impedance output.
摘要翻译：公开了具有从电源电压减小预定量的输出电压的片上电压发生器电路。输出电压与两个互补晶体管的栅极 - 源极电压成比例，并以与输出电压可用于操作的芯片上的数字电路类似的方式随温度和处理而变化。电流源用于向两个互补晶体管提供已知电流，并且使用缓冲器来提供低阻抗输出。

8. 发明授权

US4385245A MOS Power-on reset circuit 失效
标题翻译： MOS上电复位电路
公开(公告)号：US4385245A
公开(公告)日：1983-05-24
申请号：US269165
申请日：1981-06-01
申请人： Richard W. Ulmer
发明人： Richard W. Ulmer
IPC分类号： H03K17/22 , H03K5/153 , H03K17/284 , H03K17/687
CPC分类号： H03K17/223
摘要： A power-on reset circuit which deletes the need for resistors uses a current source transistor and a capacitor to provide a minimum time for the power-on reset signal. A load transistor replaces a resistor in a portion of the circuit which provides a reference.
摘要翻译：上电复位电路消除对电阻的需要使用电流源晶体管和电容器为上电复位信号提供最小时间。负载晶体管代替提供参考电路的一部分中的电阻。

9. 发明授权

US4311988A Programmable A-law and .mu.-law DAC 失效
标题翻译：可编程A律和μ-DAC DAC
公开(公告)号：US4311988A
公开(公告)日：1982-01-19
申请号：US27421
申请日：1979-04-05
申请人： Stephen H. Kelley , Richard W. Ulmer
发明人： Stephen H. Kelley , Richard W. Ulmer
IPC分类号： H03M1/00 , H03K13/02
CPC分类号： H03M1/68
摘要： A companded stacked DAC is provided which can be used in an A-law or .mu.-law conversion merely by selection. The companded DAC is inherently monotonic and can be integrated with field effect transistors. The current sources of the DAC are switched to only one of two buses. The stacked DAC includes a chord DAC and a step DAC. The two buses which the chord DAC is connected to are maintained at approximately equal voltages by the use of a reference amplifier. The companded DAC uses successive approximation when converting.
摘要翻译：提供了一个压电堆叠式DAC，可以仅通过选择在A律或μ-变换中使用。压缩DAC本质上是单调的，可以与场效应晶体管集成。 DAC的电流源仅切换为两条总线中的一条。堆叠DAC包括和弦DAC和步进DAC。弦DAC连接的两条总线通过使用参考放大器保持在大致相等的电压。压缩DAC在转换时使用逐次逼近。

10. 发明授权

US4278929A Regulated negative voltage supply 失效
标题翻译：调节负电压供应
公开(公告)号：US4278929A
公开(公告)日：1981-07-14
申请号：US96274
申请日：1979-11-21
申请人： Robert D. Lee , Richard W. Ulmer
发明人： Robert D. Lee , Richard W. Ulmer
IPC分类号： G05F1/46 , G05F3/20 , G05F1/40
CPC分类号： G05F3/205 , G05F1/46
摘要： A single chip MOS regulated negative power supply is comprised of first, second and third strings of field effect transistors and first and second amplifiers. The first string in conjunction with the zener diode develops a reference voltage which then passes through a voltage to current converter comprised of a first amplifier, the second string and an output transistor. The current thus produced passes through a third string of field effect transistors which is referenced to ground. The second amplifier provides negative feedback to the third string to produce the regulated output.
摘要翻译：单片MOS调节负电源由第一，第二和第三串场效应晶体管和第一和第二放大器组成。与齐纳二极管结合的第一串产生参考电压，然后将参考电压通过包括第一放大器，第二串和输出晶体管的电压转换电流转换器。所产生的电流通过参考地的第三串场效应晶体管。第二放大器向第三串提供负反馈以产生调节输出。

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