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1. 发明授权

US06779056B2 Direct data placement and message reassembly 失效
标题翻译：直接数据放置和消息重新组装
公开(公告)号：US06779056B2
公开(公告)日：2004-08-17
申请号：US09897044
申请日：2001-07-03
申请人： Eugene O'Neill , Richard A Gahan
发明人： Eugene O'Neill , Richard A Gahan
IPC分类号： G06F300
CPC分类号： H04L49/9094 , H04L49/90 , H04L49/9063 , H04L69/12 , H04L69/16 , H04L69/161 , H04L69/163
摘要： A direct data placement implementation for a data reassembly process. Data within a protocol data unit is placed directly in preassigned application buffers. The network interface card has buffer space into which message headers, segment headers and indicators of escaped data and size of escaped data are placed. A single buffer can contain this information for a complete PDU (or message) and is handed over to enable the next process to run on a per message basis.
摘要翻译：数据重组过程的直接数据放置实现。协议数据单元中的数据直接放置在预先分配的应用程序缓冲区中。网络接口卡具有缓冲空间，消息头，段头和转义数据的指示符以及转义数据的大小被放置到其中。单个缓冲区可以包含用于完整PDU（或消息）的该信息，并且被移交以使下一个进程能够在每个消息的基础上运行。

2. 发明授权

US07420968B2 High-speed switch architecture 有权
标题翻译：高速交换架构
公开(公告)号：US07420968B2
公开(公告)日：2008-09-02
申请号：US10456702
申请日：2003-06-06
申请人： Bryan J. Donoghue , Richard A. Gahan , Kam Choi , Edele O'Malley , Eugene O'Neill
发明人： Bryan J. Donoghue , Richard A. Gahan , Kam Choi , Edele O'Malley , Eugene O'Neill
IPC分类号： H04L12/50 , H04Q11/00
CPC分类号： H04L49/1515
摘要： A system of switch modules contains input demultiplexers connected to ports on each of the modules and output multiplexers connected to each of the modules. Each module has output and input interfaces for mesh links and at least one output interface is looped back to an input interface on the same module. The arrangement reduces module-to-module traffic and corresponding increases the transmit bandwidth of a module.
摘要翻译：开关模块的系统包括连接到每个模块上的端口的输入解复用器和连接到每个模块的输出多路复用器。每个模块都具有用于网格链接的输出和输入接口，并且至少一个输出接口循环回相同模块上的输入接口。该装置减少了模块到模块的流量，并且相应地增加了模块的传输带宽。

3. 发明授权

US06804804B2 Calculation and transmission of error check codes 失效
标题翻译：错误检查代码的计算和传输
公开(公告)号：US06804804B2
公开(公告)日：2004-10-12
申请号：US09909756
申请日：2001-07-23
申请人： Richard A Gahan , Eugene O'Neill
发明人： Richard A Gahan , Eugene O'Neill
IPC分类号： G08C2502
CPC分类号： H04L69/16 , H04L1/1874 , H04L69/169
摘要： A method of transmitting data (1) generated in an upper layer protocol such as iSCSI in a transport protocol such as TCP or SCTP, without requiring separate reads for check code generation and transmission. The upper layer protocol data is read into a transmission engine (5) that calculates the error check codes and inserts them into the transport protocol transmission. To prevent having to recalculate error codes in the event of loss of transmitted data and a retransmission request, the engine preferably also writes the error check codes into the memory so that the can be retrieved if retransmission is necessary.
摘要翻译：在诸如TCP或SCTP的传输协议中发送在诸如iSCSI的上层协议（诸如iSCSI）中生成的数据（1）的方法，而不需要用于校验码生成和传输的单独读取。将上层协议数据读入传输引擎（5），该传输引擎计算错误校验码并将其插入到传输协议传输中。为了防止在丢失发送数据和重发请求的情况下重新计算错误代码，引擎优选还将错误校验码写入存储器，以便如果需要重传则可以检索该错误代码。

4. 发明授权

US5600814A Data processing unit for transferring data between devices supporting different word length 失效
标题翻译：用于在支持不同字长的设备之间传送数据的数据处理单元
公开(公告)号：US5600814A
公开(公告)日：1997-02-04
申请号：US421509
申请日：1995-04-26
申请人： Richard A. Gahan , Eugene O'Neill
发明人： Richard A. Gahan , Eugene O'Neill
IPC分类号： G06F12/04 , G06F13/40 , G06F13/10
CPC分类号： G06F13/4018
摘要： A data processing system comprising a main memory 10 with a 32-bit longword data bus 11 and an address bus 12, and a link unit 20 using 16-bit shortwords. The link unit has two shortword memories 26 and 28 for descriptor and message shortwords. Descriptor shortwords are exchange individually with the memory 10, residing in the lower halves of longword locations; message shortwords are exchanged with the memory 10 through a concatenation and deconcatenation unit 40 so that they are stored in pairs in longword locations. Unit 20 passes descriptor addresses (with top bit 1) from a register 25 and message addresses (with top bit 0) from a register 27 to the main memory through address processing means 36, which comprises a multiplexer 43 with its two data inputs fed with two versions of the address with a 1-bit shift between them. The top address bit controls the multiplexer, so that the main memory address steps by 1 for every step of a descriptor address or every second step of a message word address.
摘要翻译：一种数据处理系统，包括具有32位长字数据总线11和地址总线12的主存储器10以及使用16位快捷键的链接单元20。链接单元具有用于描述符和消息短语的两个短语存储器26和28。描述符短语与存储器10单独交换，位于长字位置的下半部分; 消息短消息通过级联和解吸单元40与存储器10交换，使得它们成对存储在长字位置中。单元20通过地址处理装置36将来自寄存器25的描述符地址（与顶部位1）和从寄存器27的消息地址（顶部位0）传递到主存储器，地址处理装置36包括其两个数据输入馈送的多路复用器43 两个版本的地址之间有1位移位。顶部地址位控制多路复用器，使得主存储器地址对于描述符地址的每个步骤或消息字地址的每第二步骤逐步地为1。

5. 发明授权

US08879444B2 Cascade system for network units 有权
标题翻译：级联系统为网络单元
公开(公告)号：US08879444B2
公开(公告)日：2014-11-04
申请号：US13526251
申请日：2012-06-18
申请人： Bryan J Donoghue , Quang T Tran , Eugene O'Neill , David J Law , Paul J Moran , Edele O'Malley , Jerome Nolan , Kam Choi , Maurice A Goodfellow
发明人： Bryan J Donoghue , Quang T Tran , Eugene O'Neill , David J Law , Paul J Moran , Edele O'Malley , Jerome Nolan , Kam Choi , Maurice A Goodfellow
IPC分类号： H04B7/00 , H04L12/433
CPC分类号： H04L12/433
摘要： In one embodiment, a method is described for detecting an operational failure between the network unit and an adjacent network unit in the stack; controlling the switching engine to redirect packets which would otherwise be sent from a particular port to the adjacent network unit to be forwarded from another port to be sent to a different network unit in the stack; and entering the switching engine into a bypass mode in response to control data indicating an operational failure between at least two other network units in the stack to cause packets to be forwarded without being re-directed by the switching engine.
摘要翻译：在一个实施例中，描述了一种用于检测网络单元和堆叠中的相邻网络单元之间的操作故障的方法; 控制交换引擎将否则将从特定端口发送到相邻网络单元的分组，以从要发送到堆栈中的不同网络单元的另一端口转发; 以及响应于指示所述堆叠中的至少两个其他网络单元之间的操作故障的控制数据，将所述交换引擎进入旁路模式，以使转发引擎不重新引导分组。

6. 发明授权

US07701941B2 Network switch with mutually coupled look-up engine and network processor 有权
标题翻译：网络交换机具有相互耦合的查找引擎和网络处理器
公开(公告)号：US07701941B2
公开(公告)日：2010-04-20
申请号：US09818670
申请日：2001-03-28
申请人： Sorcha O'Callaghan , Neil O Fanning , Kevin Jennings , Eugene O'Neill , Joseph N Butler
发明人： Sorcha O'Callaghan , Neil O Fanning , Kevin Jennings , Eugene O'Neill , Joseph N Butler
IPC分类号： H04L12/28
CPC分类号： H04L49/3009 , H04L12/4641 , H04L49/309 , H04L49/354
摘要： A network switch includes a look-up engine for obtaining associated data in response to a header portion of a packet and an interlinked network processor such as a RISC for performing a processing function on the header portion or the associated data. Both look-up engine and the network processor may modify a destination port bitmask. The network processor may implement additional packet header processing required for replication or server load balancing.
摘要翻译：网络交换机包括用于响应于分组的报头部分获取相关联的数据的查找引擎和诸如用于在报头部分或相关联的数据上执行处理功能的诸如RISC的互连网络处理器。查找引擎和网络处理器都可以修改目标端口位掩码。网络处理器可以实现复制或服务器负载平衡所需的附加数据包头处理。

7. 发明授权

US07522589B2 Network units for use in and organisation of cascade systems 有权
标题翻译：用于级联系统的网络单元和组织
公开(公告)号：US07522589B2
公开(公告)日：2009-04-21
申请号：US10337299
申请日：2003-01-07
申请人： Eugene O'Neill , Kam Choi , Edele O'Malley , Maurice A Goodfellow
发明人： Eugene O'Neill , Kam Choi , Edele O'Malley , Maurice A Goodfellow
IPC分类号： H04L12/28
CPC分类号： H04L45/02 , H04L45/26 , H04L45/742 , H04L49/201 , H04L49/30 , H04L49/3009 , H04L49/351
摘要： A multi-port network unit for use in a cascade system of network units sends from a cascade port a packet including a special header having a source port ID, a destination port ID and a ‘destination port known’ field. The port IDs identify both a unit and a port within a unit. A routing database is set up, optionally by a discovery protocol, in terms of ports and either destination units (within the cascade) or source units (within the cascade). The database includes a mesh table, indicating from which cascade port a packet with a known destination port ID should be forwarded, without needing a fresh look-up. The database also includes a multicast exclusion table which allows ingress of packets with source unit IDs matched to an ingress port. The scheme allows a general mesh type of cascade while dynamically preventing closed loops.
摘要翻译：用于网络级联系统的多端口网络单元从级联端口发送包括具有源端口ID，目的端口ID和“目的端口已知”字段的特殊报头的分组。端口ID标识单元中的单元和端口。根据端口和目标单元（级联）或源单元（级联内），路由数据库可选地由发现协议来设置。数据库包括网格表，指示哪个级联端口具有应该转发具有已知目的地端口ID的分组，而不需要新的查找。该数据库还包括一个组播排除表，允许进入与进入端口匹配的源单元ID的数据包。该方案允许一般网格类型的级联，同时动态地防止闭环。

8. 发明授权

US07167441B2 Cascade control system for network units 有权
标题翻译：网络单元级联控制系统
公开(公告)号：US07167441B2
公开(公告)日：2007-01-23
申请号：US10067965
申请日：2002-02-08
申请人： Bryan J Donoghue , Eugene O'Neill , Edele O'Malley , Paul J Moran , Kam Choi , Jerome Nolan
发明人： Bryan J Donoghue , Eugene O'Neill , Edele O'Malley , Paul J Moran , Kam Choi , Jerome Nolan
IPC分类号： H04L12/28 , H04L12/56 , H04J3/00
CPC分类号： H04L12/433
摘要： Cascade control logic for use in a switch or other network unit that can be used in a cascaded stack can maintain normally a point-to-point half-duplex connection for control data with each of the next preceding and next succeeding units in the cascade. Each cascade logic device is organised so that for one direction, conveniently called the up direction, a device is a master and in the other direction the device is a slave in respect of the control path. A control device will generate master control frames in the up direction and deliver slave control frames in the down direction. The control device is organised so that in the absence of reception of valid control frames on a control link control data which would otherwise be sent out on that link is looped back within the control device. In this manner the control device can maintain under normal circumstances two virtual control channels which can ‘self-heal’ notwithstanding the failure or powering-down of a unit in the cascade.Status information represented by the control frames can be used to control a switching engine to provide self healing of the data path in the cascade.
摘要翻译：用于在级联堆叠中使用的交换机或其他网络单元中的级联控制逻辑可以正常地维护级联中的下一个前一个和后续单元中的每一个的控制数据的点对点半双工连接。每个级联逻辑器件被组织成使得对于一个方向，方便地称为向上方向，器件是主器件，并且在另一方向上，器件是关于控制路径的从器件。控制装置将沿向上方向产生主控制帧，并向下传送从控制帧。控制装置被组织成使得在没有接收到控制链路上的有效控制帧的情况下，否则将在该链路上发送的控制数据环回到控制装置内。以这种方式，控制装置可以在正常情况下维持两个虚拟控制通道，即使在级联中的单元发生故障或断电，它们也可“自愈”。由控制帧表示的状态信息可用于控制切换引擎以提供级联中的数据路径的自愈。

9. 发明授权

US6163545A System and method for data transfer across multiple clock domains 失效
标题翻译：跨多个时钟域进行数据传输的系统和方法
公开(公告)号：US6163545A
公开(公告)日：2000-12-19
申请号：US7802
申请日：1998-01-15
申请人： Paul Flood , Eugene O'Neill
发明人： Paul Flood , Eugene O'Neill
IPC分类号： H04L7/02 , H04L25/05 , H04J3/16
CPC分类号： H04L7/02 , H04L25/05
摘要： A system for converting data in one clock domain to a second clock domain comprises a multiplexer which has a select control which is synchronous with a first frequency and is coupled to two bistable registers of which a first is clock controlled in accordance with the first frequency and a second is clock controlled by the second frequency. The data output of the first register is looped back to the second data input of the multiplexer. The select signal operates to couple a data input to the first register whereupon the multiplexer then serves to couple the data output of the first register back to the data input thereof. The arrangement ensures availability of data at the first clock frequency beyond a transition of the second clock frequency. Thus data, preferably multi-bit address data, can be transferred from one clock domain to another with less delay than in customary systems.
摘要翻译：用于将一个时钟域中的数据转换为第二时钟域的系统包括多路复用器，其具有与第一频率同步的选择控制，并且耦合到两个双稳态寄存器，其中第一个是根据第一频率进行时钟控制的; 第二个是由第二个频率控制的时钟。第一个寄存器的数据输出环回到多路复用器的第二个数据输入端。选择信号用于将数据输入耦合到第一寄存器，于是多路复用器然后用于将第一寄存器的数据输出耦合回其数据输入。该布置确保在第二时钟频率的转变之后的第一时钟频率的数据的可用性。因此，数据，优选多位地址数据可以从一个时钟域传输到另一个时钟域，而不是传统系统中的延迟。

10. 发明授权

US08331404B2 Signature checking using deterministic finite state machines 有权
标题翻译：使用确定性有限状态机进行签名检查
公开(公告)号：US08331404B2
公开(公告)日：2012-12-11
申请号：US11923869
申请日：2007-10-25
申请人： David Law , Edele O'Malley , Daniel Martin O'Keeffe , Eugene O'Neill
发明人： David Law , Edele O'Malley , Daniel Martin O'Keeffe , Eugene O'Neill
IPC分类号： H04J1/02
CPC分类号： H04L69/16 , H04L63/0236 , H04L63/0245 , H04L63/0263 , H04L63/1416 , H04L69/161 , H04L69/22
摘要： The occurrence of false positives and the post-processing of digital streams subjected to examination by a deterministic finite state machine for character strings are reduced by combining location-based pattern matching, e.g. on packet headers, and content-based pattern matching, e.g. on payloads of packets. One scheme allows automatic transition from a header match state into an initial state of a content matching machine. Another scheme is based on a rules graph defining strings of match states and the examination of a list of match states (rather than characters) which have been previously determined, for example by means of header matching and content matching. The latter is also capable of comparing offset and depth values associated with the match states with offset and depth criteria.
摘要翻译：通过组合基于位置的模式匹配，例如，通过组合基于位置的模式匹配来减少误报的发生和经过用于字符串的确定性有限状态机检查的数字流的后处理。分组报头和基于内容的模式匹配，例如，在包的有效载荷上。一种方案允许从头匹配状态自动转换到内容匹配机器的初始状态。另一种方案是基于定义匹配状态串的规则图，并且例如通过标题匹配和内容匹配来检查先前确定的匹配状态（而不是字符）的列表。后者还能够将与匹配状态相关联的偏移和深度值与偏移和深度标准进行比较。

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