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1. 发明授权

US6166956A Fast flash EPROM programming and pre-programming circuit design 有权
标题翻译：快速闪存EPROM编程和预编程电路设计
公开(公告)号：US6166956A
公开(公告)日：2000-12-26
申请号：US303153
申请日：1999-04-30
申请人： Tom Dang-Hsing Yiu , Ray L. Wan , Ling-Wen Hsiao , Tien-Ler Lin , Fuchia Shone
发明人： Tom Dang-Hsing Yiu , Ray L. Wan , Ling-Wen Hsiao , Tien-Ler Lin , Fuchia Shone
IPC分类号： G11C16/10 , G11C16/12 , G11C16/16 , G11C16/24 , G11C7/00
CPC分类号： G11C16/12 , G11C16/10 , G11C16/16 , G11C16/24
摘要： A circuit for speeding up the pre-programming of floating gate storage transistors such as FLASH EPROMS, and particularly speeding up the pre-programming of a block or array of floating gate storage transistors includes a controllable voltage source that supplies gate programming potential across the control gate and source of the FLASH EPROM transistor cells to be programmed. A control circuit is provided that controls the voltage source to vary the gate programming potential during a programming interval as a function of time in order to decrease the time required for a given amount of charge movement to program the selected floating gate transistors. The wordline voltages are varied, while the source voltage is held constant. By starting at a lower wordline voltage, and increasing during the programming interval to a high wordline voltage, the programming speed is increased, and the high final turn-on threshold voltage for the programmed floating gate storage transistors is achieved. In addition, in order to speed up pre-programming, a programming potential is applied to four wordlines in parallel during a single programming interval. Further, the load on cells being programmed is adjusted to improve programming speed.
摘要翻译：用于加速浮动存储晶体管（例如FLASH EPROMS）的预编程的电路，并且特别是加速块或阵列的浮置栅极存储晶体管的预编程包括可控电压源，其提供跨控制的栅极编程电位要编程的FLASH EPROM晶体管单元的栅极和源极。提供控制电路，其控制电压源以在编程间隔期间作为时间的函数改变栅极编程电位，以便减少给定量的电荷移动对所选择的浮置栅极晶体管进行编程所需的时间。字线电压是变化的，而源电压保持恒定。通过以较低的字线电压开始，并且在编程间隔期间增加到高字线电压，编程速度增加，并且实现了编程浮栅存储晶体管的高最终导通阈值电压。另外，为了加速预编程，在单个编程间隔期间，编程电位并行应用于四个字线。此外，调整正在编程的单元上的负载以提高编程速度。

2. 发明授权

US5627838A Automatic test circuitry with non-volatile status write 失效
标题翻译：具有非易失性状态写入的自动测试电路
公开(公告)号：US5627838A
公开(公告)日：1997-05-06
申请号：US129419
申请日：1993-09-30
申请人： Tien-Ler Lin , Tom D. Yiu , Ray L. Wan , Kong-Mou Liou
发明人： Tien-Ler Lin , Tom D. Yiu , Ray L. Wan , Kong-Mou Liou
IPC分类号： G11C17/00 , G11C29/00 , G11C29/02 , G11C29/44 , G11C29/48
CPC分类号： G11C29/44 , G11C29/48
摘要： An integrated circuit (IC) includes a functional module such as FLASH memory with automatic program and erase circuits, test circuitry coupled with the functional module which executes a test of the functional module and generates status information as a result of the test, and non-volatile status write circuitry coupled with the test circuitry on the chip. A circuit in the non-volatile status write circuitry is responsive to the test of the functional circuitry to write the status information to the non-volatile memory. A port on the integrated circuit is coupled to the non-volatile memory through which the status information stored in the non-volatile memory is accessible in a test read mode to external devices. In a FLASH EPROM embodiment, the IC includes an array of FLASH EPROM memory cells, a test set of FLASH EPROM memory cells, and a port through which data in the array is accessible by external devices. Program and erase circuitry, coupled to the array, has a test mode to exercise the program and erase circuitry to generate status information indicating results of the test and test read mode to read out the status information. Non-volatile status write circuitry is coupled to the program and erase circuitry and the test set, and writes the status information to the test set. The program and erase circuits include retry counts with programmable thresholds for reducing the test times of the devices.
摘要翻译：集成电路（IC）包括诸如具有自动编程和擦除电路的闪速存储器的功能模块，与功能模块耦合的测试电路，其执行功能模块的测试并且作为测试的结果生成状态信息，与芯片上的测试电路耦合的易失性状态写入电路。非易失性状态写入电路中的电路响应于功能电路的测试以将状态信息写入非易失性存储器。集成电路上的端口耦合到非易失性存储器，通过该非易失性存储器，存储在非易失性存储器中的状态信息可以以测试读取模式访问到外部设备。在FLASH EPROM实施例中，IC包括闪存EPROM存储器单元的阵列，FLASH EPROM存储器单元的测试组以及阵列中的数据可由外部设备访问的端口。耦合到阵列的编程和擦除电路具有运行程序和擦除电路的测试模式，以产生指示测试结果的状态信息和测试读取模式以读出状态信息。非易失性状态写入电路耦合到程序和擦除电路和测试集，并将状态信息写入测试集。程序和擦除电路包括具有可编程阈值的重试计数，以减少器件的测试时间。

3. 发明授权

US5615153A Fast flash EPROM programming and pre-programming circuit design 失效
标题翻译：快速闪存EPROM编程和预编程电路设计
公开(公告)号：US5615153A
公开(公告)日：1997-03-25
申请号：US444314
申请日：1995-05-18
申请人： Tom D. Yiu , Ray L. Wan , Ling-Wen Hsiao , Tien-Ler Lin , Fuchia Shone
发明人： Tom D. Yiu , Ray L. Wan , Ling-Wen Hsiao , Tien-Ler Lin , Fuchia Shone
IPC分类号： G11C16/10 , G11C16/12 , G11C16/16 , G11C16/24 , G11C16/04
CPC分类号： G11C16/12 , G11C16/10 , G11C16/16 , G11C16/24
摘要： A circuit for speeding up the pre-programming of floating gate storage transistors such as FLASH EPROMS, and particularly speeding up the pre-programming of a block or array of floating gate storage transistors includes a controllable voltage source that supplies gate programming potential across the control gate and source of the FLASH EPROM transistor cells to be programmed. A control circuit is provided that controls the voltage source to vary the gate programming potential during a programming interval as a function of time in order to decrease the time required for a given amount of charge movement to program the selected floating gate transistors. The wordline voltages are varied, while the source voltage is held constant. By starting at a lower wordline voltage, and increasing during the programming interval to a high wordline voltage, the programming speed is increased, and the high final turn-on threshold voltage for the programmed floating gate storage transistors is achieved. In addition, in order to speed up pre-programming, a programming potential is applied to four wordlines in parallel during a single programming interval. Further, the load on cells being programmed is adjusted to improve programming speed.
摘要翻译：用于加速浮动存储晶体管（例如FLASH EPROMS）的预编程的电路，并且特别是加速块或阵列的浮置栅极存储晶体管的预编程包括可控电压源，其提供跨控制的栅极编程电位要编程的FLASH EPROM晶体管单元的栅极和源极。提供控制电路，其控制电压源以在编程间隔期间作为时间的函数改变栅极编程电位，以便减少给定量的电荷移动对所选择的浮置栅极晶体管进行编程所需的时间。字线电压是变化的，而源电压保持恒定。通过以较低的字线电压开始，并且在编程间隔期间增加到高字线电压，编程速度增加，并且实现了编程浮栅存储晶体管的高最终导通阈值电压。另外，为了加速预编程，在单个编程间隔期间，编程电位并行应用于四个字线。此外，调整正在编程的单元上的负载以提高编程速度。

4. 发明授权

US5526307A Flash EPROM integrated circuit architecture 失效
标题翻译：闪存EPROM集成电路架构
公开(公告)号：US5526307A
公开(公告)日：1996-06-11
申请号：US325467
申请日：1994-10-26
申请人： Tom D. Yiu , Fuchia Shone , Tien-Ler Lin , Ray L. Wan
发明人： Tom D. Yiu , Fuchia Shone , Tien-Ler Lin , Ray L. Wan
IPC分类号： G08G1/017 , G11C16/04 , H01L21/8247 , H01L27/115 , H01L29/788
CPC分类号： G08G1/017 , G11C16/0491 , H01L27/115 , H01L27/11519 , H01L27/11521
摘要： Contactless flash EPROM cell and array designs, and methods for fabricating the same result in a dense, segmentable flash EPROM chip. The flash EPROM cell is based on a drain-source-drain configuration, in which the single source diffusion is shared by two columns of transistors. The module includes a memory array having at least M rows and 2N columns of flash EPROM cells. M word lines, each coupled to the flash EPROM cells in one of the M rows of the flash EPROM cells, and N global bit lines are included. Data in and out circuitry is coupled to the N global bit lines which provide for reading and writing data in the memory array. Selector circuitry, coupled to the 2N columns of flash EPROM cells, and to the N global bit lines, provides for selective connection of two columns of the 2N columns to each of the N global bit lines so that access to the 2N columns of flash EPROM cells by the data in and out circuitry is provided across N global bit lines. The semiconductor substrate has a first conductivity type, a first well in the substrate of a second conductivity type, and a second well of the first conductivity type in the first well. The flash EPROM cells are made in the second well to allow application of a negative potential to at least one of the source and drain during an operation to charge the floating gate in the cells.
摘要翻译： PCT No.PCT / US94 / 10331 Sec。 371日期：1994年10月26日 102（e）1994年10月26日PCT 1994年9月13日提交PCT无连接闪存EPROM单元和阵列设计及其制造方法产生密集的可分割闪存EPROM芯片。闪存EPROM单元基于漏 - 源 - 漏配置，其中单个源扩散由两列晶体管共享。该模块包括具有至少M行和2N列闪存EPROM单元的存储器阵列。 M字线各自耦合到闪存EPROM单元的M行之一中的闪存EPROM单元和N个全局位线。数据输入和输出电路耦合到提供在存储器阵列中读取和写入数据的N个全局位线。耦合到2N列的闪存EPROM单元和N个全局位线的选择器电路提供了将2N列的两列选择性地连接到N个全局位线中的每一个，使得访问闪存EPROM的2N列通过数据输入和输出电路的单元被提供在N个全局位线之间。半导体衬底具有第一导电类型，第二导电类型的衬底中的第一阱和第一阱中第一导电类型的第二阱。闪存EPROM单元在第二阱中制造，以允许在对单元中的浮置栅极充电的操作期间向源极和漏极中的至少一个施加负电位。

5. 发明授权

US5818848A Automatic test circuitry with non-volatile status write 失效
标题翻译：具有非易失性状态写入的自动测试电路
公开(公告)号：US5818848A
公开(公告)日：1998-10-06
申请号：US770479
申请日：1996-12-20
申请人： Tien-Ler Lin , Tom Dang-Hsing Yiu , Ray L. Wan , Kong-Mou Liou
发明人： Tien-Ler Lin , Tom Dang-Hsing Yiu , Ray L. Wan , Kong-Mou Liou
IPC分类号： G11C17/00 , G11C29/00 , G11C29/02 , G11C29/44 , G11C29/48
CPC分类号： G11C29/44 , G11C29/48
摘要： An integrated circuit comprises a functional module such as a FLASH memory with automatic program and erase circuits, test circuitry coupled with the functional module which executes a test of the functional module and generates status information as a result of the test, and non-volatile status write circuitry coupled with the test circuitry on the chip. A circuit in the non-volatile status write circuitry is responsive to the test of the functional circuitry to write the status information to the non-volatile memory. A port is provided on the integrated circuit coupled to the non-volatile memory through which the status information stored in the non-volatile memory is accessible in a test read mode to external devices. In a FLASH EPROM embodiment, the IC includes an array of FLASH EPROM memory cells and a port through which data in the array is accessible by external devices. A test set of FLASH EPROM memory cells is provided in the array. Program and erase circuitry, coupled to the array, has a test mode to exercise the program and erase circuitry to generate status information indicating results of the test and test read mode to read out the status information. Non-volatile status write circuitry, is coupled to the program and erase circuitry and the test set, and writes the status information to the test set. The program and erase circuits include retry counts with programmable thresholds for reducing the test times of the devices.
摘要翻译：集成电路包括诸如具有自动编程和擦除电路的闪存的功能模块，与功能模块耦合的测试电路，其执行功能模块的测试并且作为测试的结果生成状态信息，以及非易失性状态写入电路与芯片上的测试电路耦合。非易失性状态写入电路中的电路响应于功能电路的测试以将状态信息写入非易失性存储器。在与非易失性存储器耦合的集成电路上提供端口，通过该端口，存储在非易失性存储器中的状态信息可以以测试读取模式访问到外部设备。在FLASH EPROM实施例中，IC包括闪存EPROM存储器单元阵列和阵列中的数据可由外部设备访问的端口。阵列中提供了一组FLASH EPROM存储单元。耦合到阵列的编程和擦除电路具有运行程序和擦除电路的测试模式，以产生指示测试结果的状态信息和测试读取模式以读出状态信息。非易失性状态写入电路耦合到程序和擦除电路和测试仪，并将状态信息写入测试仪。程序和擦除电路包括具有可编程阈值的重试计数，以减少器件的测试时间。

6. 发明授权

US5596530A Flash EPROM with block erase flags for over-erase protection 失效
标题翻译：闪存EPROM具有块擦除标志，用于过擦除保护
公开(公告)号：US5596530A
公开(公告)日：1997-01-21
申请号：US383726
申请日：1995-02-02
申请人： Tien-Ler Lin , Ray L. Wan , Ling-Wen Hsiao , Gilbert Sung
发明人： Tien-Ler Lin , Ray L. Wan , Ling-Wen Hsiao , Gilbert Sung
IPC分类号： G11C16/16 , G11C16/34 , G11C7/00 , G11C16/00
CPC分类号： G11C16/3445 , G11C16/16 , G11C16/344
摘要： A FLASH EPROM device includes a memory array organized into a plurality of blocks of memory cells. An energizing circuit applies energizing voltages to the blocks of memory cells to read and program addressed cells, and to erase selected blocks or the whole memory array. An erase verify circuit separately verifies erasure of blocks in the plurality of block memory cells. Control logic controls the energizing circuit to re-erase blocks which fail erase verify. The control logic includes a plurality of block erase flags which correspond to respective blocks of memory cells in the array. The erase verify is responsive to the block erase flags to verify only those blocks having a set block erase flag. If the block passes erase verify, then the block erase flag is reset. Only those blocks having a set block erase flag after the erase verify operation are re-erased. To support this operation, the circuit also includes the capability of erasing only a block of the memory array at a time.
摘要翻译： FLASH EPROM装置包括组织成多个存储单元块的存储器阵列。激励电路向存储器单元的块施加通电电压以读取和编程寻址单元，并擦除所选择的块或整个存储器阵列。擦除验证电路分别验证多个块存储器单元中的块的擦除。控制逻辑控制通电电路重新擦除擦除验证失败的块。控制逻辑包括与阵列中的存储器单元的相应块对应的多个块擦除标志。擦除验证响应于块擦除标志以仅验证具有设置块擦除标志的那些块。如果块通过擦除验证，则块擦除标志被复位。在擦除验证操作之后，仅具有设置块擦除标志的块被重新擦除。为了支持这种操作，该电路还包括一次仅擦除存储器阵列的能力。

7. 发明授权

US5563823A Fast FLASH EPROM programming and pre-programming circuit design 失效
标题翻译：快速FLASH EPROM编程和预编程电路设计
公开(公告)号：US5563823A
公开(公告)日：1996-10-08
申请号：US393243
申请日：1995-02-23
申请人： Tom D. Yiu , Ray L. Wan , Ling-Wen Hsiao , Tien-Ler Lin , Fuchia Shone
发明人： Tom D. Yiu , Ray L. Wan , Ling-Wen Hsiao , Tien-Ler Lin , Fuchia Shone
IPC分类号： G11C16/10 , G11C16/12 , G11C16/16 , G11C16/24 , G11C7/00
CPC分类号： G11C16/12 , G11C16/10 , G11C16/16 , G11C16/24
摘要： A circuit for speeding up the pre-programming of floating gate storage transistors such as FLASH EPROMS, and particularly speeding up the pre-programming of a block or array of floating gate storage transistors includes a controllable voltage source that supplies gate programming potential across the control gate and source of the FLASH EPROM transistor cells to be programmed. A control circuit is provided that controls the voltage source to vary the gate programming potential during a programming interval as a function of time in order to decrease the time required for a given amount of charge movement to program the selected floating gate transistors. The wordline voltages are varied, while the source voltage is held constant. By starting at a lower wordline voltage, and increasing during the programming interval to a high wordline voltage, the programming speed is increased, and the high final turn-on threshold voltage for the programmed floating gate storage transistors is achieved. In addition, in order to speed up pre-programming, a programming potential is applied to four wordlines in parallel during a single programming interval. Further, the load on cells being programmed is adjusted to improve programming speed.
摘要翻译：用于加速浮动存储晶体管（例如FLASH EPROMS）的预编程的电路，并且特别是加速块或阵列的浮置栅极存储晶体管的预编程包括可控电压源，其提供跨控制的栅极编程电位要编程的FLASH EPROM晶体管单元的栅极和源极。提供控制电路，其控制电压源以在编程间隔期间作为时间的函数改变栅极编程电位，以便减少给定量的电荷移动对所选择的浮置栅极晶体管进行编程所需的时间。字线电压是变化的，而源电压保持恒定。通过以较低的字线电压开始，并且在编程间隔期间增加到高字线电压，编程速度增加，并且实现了编程浮栅存储晶体管的高最终导通阈值电压。另外，为了加速预编程，在单个编程间隔期间，编程电位并行应用于四个字线。此外，调整正在编程的单元上的负载以提高编程速度。

8. 发明授权

US5539688A Fast pre-programming circuit for floating gate memory 失效
标题翻译：快速预编程电路用于浮动栅极存储器
公开(公告)号：US5539688A
公开(公告)日：1996-07-23
申请号：US444313
申请日：1995-05-18
申请人： Tom D. Yiu , Ray L. Wan , Ling-Wen Hsiao , Tien-Ler Lin , Fuchia Shone
发明人： Tom D. Yiu , Ray L. Wan , Ling-Wen Hsiao , Tien-Ler Lin , Fuchia Shone
IPC分类号： G11C16/10 , G11C16/12 , G11C16/16 , G11C16/24 , G11C16/06
CPC分类号： G11C16/12 , G11C16/10 , G11C16/16 , G11C16/24
摘要： A circuit for speeding up the pre-programming of floating gate storage transistors such as FLASH EPROMS, and particularly speeding up the pre-programming of a block or array of floating gate storage transistors includes a controllable voltage source that supplies gate programming potential across the control gate and source of the FLASH EPROM transistor cells to be programmed. A control circuit is provided that controls the voltage source to vary the gate programming potential during a programming interval as a function of time in order to decrease the time required for a given amount of charge movement to program the selected floating gate transistors. The wordline voltages are varied, while the source voltage is held constant. By starting at a lower wordline voltage, and increasing during the programming interval to a high wordline voltage, the programming speed is increased, and the high final turn-on threshold voltage for the programmed floating gate storage transistors is achieved. In addition, in order to speed up pre-programming, a programming potential is applied to four wordlines in parallel during a single programming interval. Further, the load on cells being programmed is adjusted to improve programming speed.
摘要翻译：用于加速浮动存储晶体管（例如FLASH EPROMS）的预编程的电路，并且特别是加速块或阵列的浮置栅极存储晶体管的预编程包括可控电压源，其提供跨控制的栅极编程电位要编程的FLASH EPROM晶体管单元的栅极和源极。提供控制电路，其控制电压源以在编程间隔期间作为时间的函数改变栅极编程电位，以便减少给定量的电荷移动对所选择的浮置栅极晶体管进行编程所需的时间。字线电压是变化的，而源电压保持恒定。通过以较低的字线电压开始，并且在编程间隔期间增加到高字线电压，编程速度增加，并且实现了编程浮栅存储晶体管的高最终导通阈值电压。另外，为了加速预编程，在单个编程间隔期间，编程电位并行应用于四个字线。此外，调整正在编程的单元上的负载以提高编程速度。

9. 发明授权

US5821909A Fast flash EPROM programming and pre-programming circuit design 失效
公开(公告)号：US5821909A
公开(公告)日：1998-10-13
申请号：US700587
申请日：1996-08-14
申请人： Tom Dang-Hsing Yiu , Ray L. Wan , Ling-Wen Hsiao , Tien-Ler Lin , Fuchia Shone
发明人： Tom Dang-Hsing Yiu , Ray L. Wan , Ling-Wen Hsiao , Tien-Ler Lin , Fuchia Shone
IPC分类号： G11C16/10 , G11C16/12 , G11C16/16 , G11C16/24 , G11C16/02
CPC分类号： G11C16/12 , G11C16/10 , G11C16/16 , G11C16/24
摘要： A circuit for speeding up the pre-programming of floating gate storage transistors such as FLASH EPROMS, and particularly speeding up the pre-programming of a block or array of floating gate storage transistors includes a controllable voltage source that supplies gate programming potential across the control gate and source of the FLASH EPROM transistor cells to be programmed. A control circuit is provided that controls the voltage source to vary the gate programming potential during a programming interval as a function of time in order to decrease the time required for a given amount of charge movement to program the selected floating gate transistors. The wordline voltages are varied, while the source voltage is held constant. By starting at a lower wordline voltage, and increasing during the programming interval to a high wordline voltage, the programming speed is increased, and the high final turn-on threshold voltage for the programmed floating gate storage transistors is achieved. In addition, in order to speed up pre-programming, a programming potential is applied to four wordlines in parallel during a single programming interval. Further, the load on cells being programmed is adjusted to improve programming speed.

10. 发明授权

US5563822A Fast flash EPROM programming and pre-programming circuit design 失效
公开(公告)号：US5563822A
公开(公告)日：1996-10-08
申请号：US444315
申请日：1995-05-18
申请人： Tom D. Yiu , Ray L. Wan , Ling-Wen Hsiao , Tien-Ler Lin , Fuchia Shone
发明人： Tom D. Yiu , Ray L. Wan , Ling-Wen Hsiao , Tien-Ler Lin , Fuchia Shone
IPC分类号： G11C16/10 , G11C16/12 , G11C16/16 , G11C16/24 , G11C13/00
CPC分类号： G11C16/12 , G11C16/10 , G11C16/16 , G11C16/24
摘要： A circuit for speeding up the pre-programming of floating gate storage transistors such as FLASH EPROMS, and particularly speeding up the pre-programming of a block or array of floating gate storage transistors includes a controllable voltage source that supplies gate programming potential across the control gate and source of the FLASH EPROM transistor cells to be programmed. A control circuit is provided that controls the voltage source to vary the gate programming potential during a programming interval as a function of time in order to decrease the time required for a given amount of charge movement to program the selected floating gate transistors. The wordline voltages are varied, while the source voltage is held constant. By starting at a lower wordline voltage, and increasing during the programming interval to a high wordline voltage, the programming speed is increased, and the high final turn-on threshold voltage for the programmed floating gate storage transistors is achieved. In addition, in order to speed up pre-programming, a programming potential is applied to four wordlines in parallel during a single programming interval. Further, the load on cells being programmed is adjusted to improve programming speed.

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