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1. 发明授权

US5563823A Fast FLASH EPROM programming and pre-programming circuit design 失效
标题翻译：快速FLASH EPROM编程和预编程电路设计
公开(公告)号：US5563823A
公开(公告)日：1996-10-08
申请号：US393243
申请日：1995-02-23
申请人： Tom D. Yiu , Ray L. Wan , Ling-Wen Hsiao , Tien-Ler Lin , Fuchia Shone
发明人： Tom D. Yiu , Ray L. Wan , Ling-Wen Hsiao , Tien-Ler Lin , Fuchia Shone
IPC分类号： G11C16/10 , G11C16/12 , G11C16/16 , G11C16/24 , G11C7/00
CPC分类号： G11C16/12 , G11C16/10 , G11C16/16 , G11C16/24
摘要： A circuit for speeding up the pre-programming of floating gate storage transistors such as FLASH EPROMS, and particularly speeding up the pre-programming of a block or array of floating gate storage transistors includes a controllable voltage source that supplies gate programming potential across the control gate and source of the FLASH EPROM transistor cells to be programmed. A control circuit is provided that controls the voltage source to vary the gate programming potential during a programming interval as a function of time in order to decrease the time required for a given amount of charge movement to program the selected floating gate transistors. The wordline voltages are varied, while the source voltage is held constant. By starting at a lower wordline voltage, and increasing during the programming interval to a high wordline voltage, the programming speed is increased, and the high final turn-on threshold voltage for the programmed floating gate storage transistors is achieved. In addition, in order to speed up pre-programming, a programming potential is applied to four wordlines in parallel during a single programming interval. Further, the load on cells being programmed is adjusted to improve programming speed.
摘要翻译：用于加速浮动存储晶体管（例如FLASH EPROMS）的预编程的电路，并且特别是加速块或阵列的浮置栅极存储晶体管的预编程包括可控电压源，其提供跨控制的栅极编程电位要编程的FLASH EPROM晶体管单元的栅极和源极。提供控制电路，其控制电压源以在编程间隔期间作为时间的函数改变栅极编程电位，以便减少给定量的电荷移动对所选择的浮置栅极晶体管进行编程所需的时间。字线电压是变化的，而源电压保持恒定。通过以较低的字线电压开始，并且在编程间隔期间增加到高字线电压，编程速度增加，并且实现了编程浮栅存储晶体管的高最终导通阈值电压。另外，为了加速预编程，在单个编程间隔期间，编程电位并行应用于四个字线。此外，调整正在编程的单元上的负载以提高编程速度。

2. 发明授权

US5539688A Fast pre-programming circuit for floating gate memory 失效
标题翻译：快速预编程电路用于浮动栅极存储器
公开(公告)号：US5539688A
公开(公告)日：1996-07-23
申请号：US444313
申请日：1995-05-18
申请人： Tom D. Yiu , Ray L. Wan , Ling-Wen Hsiao , Tien-Ler Lin , Fuchia Shone
发明人： Tom D. Yiu , Ray L. Wan , Ling-Wen Hsiao , Tien-Ler Lin , Fuchia Shone
IPC分类号： G11C16/10 , G11C16/12 , G11C16/16 , G11C16/24 , G11C16/06
CPC分类号： G11C16/12 , G11C16/10 , G11C16/16 , G11C16/24
摘要： A circuit for speeding up the pre-programming of floating gate storage transistors such as FLASH EPROMS, and particularly speeding up the pre-programming of a block or array of floating gate storage transistors includes a controllable voltage source that supplies gate programming potential across the control gate and source of the FLASH EPROM transistor cells to be programmed. A control circuit is provided that controls the voltage source to vary the gate programming potential during a programming interval as a function of time in order to decrease the time required for a given amount of charge movement to program the selected floating gate transistors. The wordline voltages are varied, while the source voltage is held constant. By starting at a lower wordline voltage, and increasing during the programming interval to a high wordline voltage, the programming speed is increased, and the high final turn-on threshold voltage for the programmed floating gate storage transistors is achieved. In addition, in order to speed up pre-programming, a programming potential is applied to four wordlines in parallel during a single programming interval. Further, the load on cells being programmed is adjusted to improve programming speed.
摘要翻译：用于加速浮动存储晶体管（例如FLASH EPROMS）的预编程的电路，并且特别是加速块或阵列的浮置栅极存储晶体管的预编程包括可控电压源，其提供跨控制的栅极编程电位要编程的FLASH EPROM晶体管单元的栅极和源极。提供控制电路，其控制电压源以在编程间隔期间作为时间的函数改变栅极编程电位，以便减少给定量的电荷移动对所选择的浮置栅极晶体管进行编程所需的时间。字线电压是变化的，而源电压保持恒定。通过以较低的字线电压开始，并且在编程间隔期间增加到高字线电压，编程速度增加，并且实现了编程浮栅存储晶体管的高最终导通阈值电压。另外，为了加速预编程，在单个编程间隔期间，编程电位并行应用于四个字线。此外，调整正在编程的单元上的负载以提高编程速度。

3. 发明授权

US5563822A Fast flash EPROM programming and pre-programming circuit design 失效
公开(公告)号：US5563822A
公开(公告)日：1996-10-08
申请号：US444315
申请日：1995-05-18
申请人： Tom D. Yiu , Ray L. Wan , Ling-Wen Hsiao , Tien-Ler Lin , Fuchia Shone
发明人： Tom D. Yiu , Ray L. Wan , Ling-Wen Hsiao , Tien-Ler Lin , Fuchia Shone
IPC分类号： G11C16/10 , G11C16/12 , G11C16/16 , G11C16/24 , G11C13/00
CPC分类号： G11C16/12 , G11C16/10 , G11C16/16 , G11C16/24
摘要： A circuit for speeding up the pre-programming of floating gate storage transistors such as FLASH EPROMS, and particularly speeding up the pre-programming of a block or array of floating gate storage transistors includes a controllable voltage source that supplies gate programming potential across the control gate and source of the FLASH EPROM transistor cells to be programmed. A control circuit is provided that controls the voltage source to vary the gate programming potential during a programming interval as a function of time in order to decrease the time required for a given amount of charge movement to program the selected floating gate transistors. The wordline voltages are varied, while the source voltage is held constant. By starting at a lower wordline voltage, and increasing during the programming interval to a high wordline voltage, the programming speed is increased, and the high final turn-on threshold voltage for the programmed floating gate storage transistors is achieved. In addition, in order to speed up pre-programming, a programming potential is applied to four wordlines in parallel during a single programming interval. Further, the load on cells being programmed is adjusted to improve programming speed.

4. 发明授权

US5615153A Fast flash EPROM programming and pre-programming circuit design 失效
标题翻译：快速闪存EPROM编程和预编程电路设计
公开(公告)号：US5615153A
公开(公告)日：1997-03-25
申请号：US444314
申请日：1995-05-18
申请人： Tom D. Yiu , Ray L. Wan , Ling-Wen Hsiao , Tien-Ler Lin , Fuchia Shone
发明人： Tom D. Yiu , Ray L. Wan , Ling-Wen Hsiao , Tien-Ler Lin , Fuchia Shone
IPC分类号： G11C16/10 , G11C16/12 , G11C16/16 , G11C16/24 , G11C16/04
CPC分类号： G11C16/12 , G11C16/10 , G11C16/16 , G11C16/24
摘要： A circuit for speeding up the pre-programming of floating gate storage transistors such as FLASH EPROMS, and particularly speeding up the pre-programming of a block or array of floating gate storage transistors includes a controllable voltage source that supplies gate programming potential across the control gate and source of the FLASH EPROM transistor cells to be programmed. A control circuit is provided that controls the voltage source to vary the gate programming potential during a programming interval as a function of time in order to decrease the time required for a given amount of charge movement to program the selected floating gate transistors. The wordline voltages are varied, while the source voltage is held constant. By starting at a lower wordline voltage, and increasing during the programming interval to a high wordline voltage, the programming speed is increased, and the high final turn-on threshold voltage for the programmed floating gate storage transistors is achieved. In addition, in order to speed up pre-programming, a programming potential is applied to four wordlines in parallel during a single programming interval. Further, the load on cells being programmed is adjusted to improve programming speed.
摘要翻译：用于加速浮动存储晶体管（例如FLASH EPROMS）的预编程的电路，并且特别是加速块或阵列的浮置栅极存储晶体管的预编程包括可控电压源，其提供跨控制的栅极编程电位要编程的FLASH EPROM晶体管单元的栅极和源极。提供控制电路，其控制电压源以在编程间隔期间作为时间的函数改变栅极编程电位，以便减少给定量的电荷移动对所选择的浮置栅极晶体管进行编程所需的时间。字线电压是变化的，而源电压保持恒定。通过以较低的字线电压开始，并且在编程间隔期间增加到高字线电压，编程速度增加，并且实现了编程浮栅存储晶体管的高最终导通阈值电压。另外，为了加速预编程，在单个编程间隔期间，编程电位并行应用于四个字线。此外，调整正在编程的单元上的负载以提高编程速度。

5. 发明授权

US5526307A Flash EPROM integrated circuit architecture 失效
标题翻译：闪存EPROM集成电路架构
公开(公告)号：US5526307A
公开(公告)日：1996-06-11
申请号：US325467
申请日：1994-10-26
申请人： Tom D. Yiu , Fuchia Shone , Tien-Ler Lin , Ray L. Wan
发明人： Tom D. Yiu , Fuchia Shone , Tien-Ler Lin , Ray L. Wan
IPC分类号： G08G1/017 , G11C16/04 , H01L21/8247 , H01L27/115 , H01L29/788
CPC分类号： G08G1/017 , G11C16/0491 , H01L27/115 , H01L27/11519 , H01L27/11521
摘要： Contactless flash EPROM cell and array designs, and methods for fabricating the same result in a dense, segmentable flash EPROM chip. The flash EPROM cell is based on a drain-source-drain configuration, in which the single source diffusion is shared by two columns of transistors. The module includes a memory array having at least M rows and 2N columns of flash EPROM cells. M word lines, each coupled to the flash EPROM cells in one of the M rows of the flash EPROM cells, and N global bit lines are included. Data in and out circuitry is coupled to the N global bit lines which provide for reading and writing data in the memory array. Selector circuitry, coupled to the 2N columns of flash EPROM cells, and to the N global bit lines, provides for selective connection of two columns of the 2N columns to each of the N global bit lines so that access to the 2N columns of flash EPROM cells by the data in and out circuitry is provided across N global bit lines. The semiconductor substrate has a first conductivity type, a first well in the substrate of a second conductivity type, and a second well of the first conductivity type in the first well. The flash EPROM cells are made in the second well to allow application of a negative potential to at least one of the source and drain during an operation to charge the floating gate in the cells.
摘要翻译： PCT No.PCT / US94 / 10331 Sec。 371日期：1994年10月26日 102（e）1994年10月26日PCT 1994年9月13日提交PCT无连接闪存EPROM单元和阵列设计及其制造方法产生密集的可分割闪存EPROM芯片。闪存EPROM单元基于漏 - 源 - 漏配置，其中单个源扩散由两列晶体管共享。该模块包括具有至少M行和2N列闪存EPROM单元的存储器阵列。 M字线各自耦合到闪存EPROM单元的M行之一中的闪存EPROM单元和N个全局位线。数据输入和输出电路耦合到提供在存储器阵列中读取和写入数据的N个全局位线。耦合到2N列的闪存EPROM单元和N个全局位线的选择器电路提供了将2N列的两列选择性地连接到N个全局位线中的每一个，使得访问闪存EPROM的2N列通过数据输入和输出电路的单元被提供在N个全局位线之间。半导体衬底具有第一导电类型，第二导电类型的衬底中的第一阱和第一阱中第一导电类型的第二阱。闪存EPROM单元在第二阱中制造，以允许在对单元中的浮置栅极充电的操作期间向源极和漏极中的至少一个施加负电位。

6. 发明授权

US5453391A Method for manufacturing a contactless floating gate transistor array 失效
标题翻译：非接触式浮栅晶体管阵列的制造方法
公开(公告)号：US5453391A
公开(公告)日：1995-09-26
申请号：US67519
申请日：1993-05-25
申请人： Tom D. Yiu , Fuchia Shone , Tien-Ler Lin , Ling Chen
发明人： Tom D. Yiu , Fuchia Shone , Tien-Ler Lin , Ling Chen
IPC分类号： G11C16/04 , H01L21/8247 , H01L27/115
CPC分类号： H01L27/11519 , G11C16/0491 , H01L27/115 , H01L27/11521
摘要： An improved contactless EPROM array, EPROM cell design, and method for fabricating the same is based on a unique drain-source-drain configuration, in which a single source diffusion is shared by two columns of transistors. An elongated first drain diffusion region, an elongated source diffusion region, and an elongated second drain diffusion region, are formed in a semi-conductor substrate along essentially parallel lines. Field oxide regions are grown on opposite sides of the first and second drain diffusion regions. Floating gates and control gate wordlines are formed orthogonal to the drain-source-drain structure to establish two columns of storage cells having a shared source region. The shared source region is coupled through a bottom block select transistor to a virtual ground terminal. Each drain diffusion region is coupled through a top block select transistor to global bitline. The cell structure uses two metal global bitlines which extend essentially parallel to the drain, source and drain diffusion regions, and a virtual ground conductor which couples a plurality of columns of transistors to a virtual ground terminal through a horizontal conductor, such as a buried diffusion line.
摘要翻译：改进的非接触式EPROM阵列，EPROM单元设计及其制造方法基于唯一的漏极 - 源极 - 漏极配置，其中单个源极扩散由两列晶体管共享。沿着基本上平行的线，在半导体衬底中形成细长的第一漏极扩散区域，细长源极扩散区域和细长的第二漏极扩散区域。场氧化物区域在第一和第二漏极扩散区域的相对侧上生长。浮置栅极和控制栅极字线与漏极 - 源极 - 漏极结构正交形成，以建立具有共享源极区域的两列存储单元。共享源极区域通过底部块选择晶体管耦合到虚拟接地端子。每个漏极扩散区域通过顶部块选择晶体管耦合到全局位线。电池结构使用两个基本平行于漏极，源极和漏极扩散区域延伸的金属全局位线，以及通过水平导体（例如埋入扩散）将多个晶体管列耦合到虚拟接地端子的虚拟接地导体线。

7. 发明授权

US5821909A Fast flash EPROM programming and pre-programming circuit design 失效
公开(公告)号：US5821909A
公开(公告)日：1998-10-13
申请号：US700587
申请日：1996-08-14
申请人： Tom Dang-Hsing Yiu , Ray L. Wan , Ling-Wen Hsiao , Tien-Ler Lin , Fuchia Shone
发明人： Tom Dang-Hsing Yiu , Ray L. Wan , Ling-Wen Hsiao , Tien-Ler Lin , Fuchia Shone
IPC分类号： G11C16/10 , G11C16/12 , G11C16/16 , G11C16/24 , G11C16/02
CPC分类号： G11C16/12 , G11C16/10 , G11C16/16 , G11C16/24
摘要： A circuit for speeding up the pre-programming of floating gate storage transistors such as FLASH EPROMS, and particularly speeding up the pre-programming of a block or array of floating gate storage transistors includes a controllable voltage source that supplies gate programming potential across the control gate and source of the FLASH EPROM transistor cells to be programmed. A control circuit is provided that controls the voltage source to vary the gate programming potential during a programming interval as a function of time in order to decrease the time required for a given amount of charge movement to program the selected floating gate transistors. The wordline voltages are varied, while the source voltage is held constant. By starting at a lower wordline voltage, and increasing during the programming interval to a high wordline voltage, the programming speed is increased, and the high final turn-on threshold voltage for the programmed floating gate storage transistors is achieved. In addition, in order to speed up pre-programming, a programming potential is applied to four wordlines in parallel during a single programming interval. Further, the load on cells being programmed is adjusted to improve programming speed.

8. 发明授权

US6166956A Fast flash EPROM programming and pre-programming circuit design 有权
标题翻译：快速闪存EPROM编程和预编程电路设计
公开(公告)号：US6166956A
公开(公告)日：2000-12-26
申请号：US303153
申请日：1999-04-30
申请人： Tom Dang-Hsing Yiu , Ray L. Wan , Ling-Wen Hsiao , Tien-Ler Lin , Fuchia Shone
发明人： Tom Dang-Hsing Yiu , Ray L. Wan , Ling-Wen Hsiao , Tien-Ler Lin , Fuchia Shone
IPC分类号： G11C16/10 , G11C16/12 , G11C16/16 , G11C16/24 , G11C7/00
CPC分类号： G11C16/12 , G11C16/10 , G11C16/16 , G11C16/24
摘要： A circuit for speeding up the pre-programming of floating gate storage transistors such as FLASH EPROMS, and particularly speeding up the pre-programming of a block or array of floating gate storage transistors includes a controllable voltage source that supplies gate programming potential across the control gate and source of the FLASH EPROM transistor cells to be programmed. A control circuit is provided that controls the voltage source to vary the gate programming potential during a programming interval as a function of time in order to decrease the time required for a given amount of charge movement to program the selected floating gate transistors. The wordline voltages are varied, while the source voltage is held constant. By starting at a lower wordline voltage, and increasing during the programming interval to a high wordline voltage, the programming speed is increased, and the high final turn-on threshold voltage for the programmed floating gate storage transistors is achieved. In addition, in order to speed up pre-programming, a programming potential is applied to four wordlines in parallel during a single programming interval. Further, the load on cells being programmed is adjusted to improve programming speed.
摘要翻译：用于加速浮动存储晶体管（例如FLASH EPROMS）的预编程的电路，并且特别是加速块或阵列的浮置栅极存储晶体管的预编程包括可控电压源，其提供跨控制的栅极编程电位要编程的FLASH EPROM晶体管单元的栅极和源极。提供控制电路，其控制电压源以在编程间隔期间作为时间的函数改变栅极编程电位，以便减少给定量的电荷移动对所选择的浮置栅极晶体管进行编程所需的时间。字线电压是变化的，而源电压保持恒定。通过以较低的字线电压开始，并且在编程间隔期间增加到高字线电压，编程速度增加，并且实现了编程浮栅存储晶体管的高最终导通阈值电压。另外，为了加速预编程，在单个编程间隔期间，编程电位并行应用于四个字线。此外，调整正在编程的单元上的负载以提高编程速度。

9. 发明授权

US5691938A Non-volatile memory cell and array architecture 失效
标题翻译：非易失性存储单元和阵列架构
公开(公告)号：US5691938A
公开(公告)日：1997-11-25
申请号：US237226
申请日：1994-05-03
申请人： Tom Dang-Hsing Yiu , Fuchia Shone , Tien-Ler Lin , Ling Chen
发明人： Tom Dang-Hsing Yiu , Fuchia Shone , Tien-Ler Lin , Ling Chen
IPC分类号： G11C16/04 , H01L21/8247 , H01L27/115 , G11C16/06
CPC分类号： H01L27/11519 , G11C16/0491 , H01L27/115 , H01L27/11521
摘要： An improved contactless EPROM array, EPROM cell design, and method for fabricating the same is based on a unique drain-source-drain configuration, in which a single source diffusion is shared by two columns of transistors. An elongated first drain diffusion region, an elongated source diffusion region, and an elongated second drain diffusion region, are formed in a semi-conductor substrate along essentially parallel lines. Field oxide regions are grown on opposite sides of the first and second drain diffusion regions. Floating gates and control gate wordlines are formed orthogonal to the drain-source-drain structure to establish two columns of storage cells having a shared source region. The shared source region is coupled through a bottom block select transistor to a virtual ground terminal. Each drain diffusion region is-coupled through a top block select transistor to global bitline. The cell structure uses two metal global bitlines which extend essentially parallel to the drain, source and drain diffusion regions, and a virtual ground conductor which couples a plurality of columns of transistors to a virtual ground terminal through a horizontal conductor, such as a buried diffusion line.
摘要翻译：改进的非接触式EPROM阵列，EPROM单元设计及其制造方法基于唯一的漏极 - 源极 - 漏极配置，其中单个源极扩散由两列晶体管共享。沿着基本上平行的线，在半导体衬底中形成细长的第一漏极扩散区域，细长源极扩散区域和细长的第二漏极扩散区域。场氧化物区域在第一和第二漏极扩散区域的相对侧上生长。浮置栅极和控制栅极字线与漏极 - 源极 - 漏极结构正交形成，以建立具有共享源极区域的两列存储单元。共享源极区域通过底部块选择晶体管耦合到虚拟接地端子。每个漏极扩散区域通过顶部块选择晶体管耦合到全局位线。电池结构使用两个基本平行于漏极，源极和漏极扩散区域延伸的金属全局位线，以及通过水平导体（例如埋入扩散）将多个晶体管列耦合到虚拟接地端子的虚拟接地导体线。

10. 发明授权

US5618742A Method of making flash EPROM with conductive sidewall spacer contacting floating gate 失效
标题翻译：制造具有导电侧壁间隔物接触浮动栅极的闪速EPROM的方法
公开(公告)号：US5618742A
公开(公告)日：1997-04-08
申请号：US329487
申请日：1994-10-26
申请人： Fuchia Shone , Tom D.-H. Yiu , Tien-Ler Lin
发明人： Fuchia Shone , Tom D.-H. Yiu , Tien-Ler Lin
IPC分类号： G08G1/017 , G11C16/04 , H01L21/8247 , H01L27/115
CPC分类号： H01L27/11519 , G08G1/017 , G11C16/0491 , H01L27/115 , H01L27/11521
摘要： Contactless flash EPROM cell and array designs, and methods for fabricating the same result in dense, segmentable flash EPROM chips. Also, an extended floating gate structure, and method for manufacturing the extended floating gate allow for higher capacitive coupling ratios in flash EPROM circuitry with very small design rules. The floating gates are extended in a symmetrical fashion in a drain-source-drain architecture, so that each pair of columns of cells has a floating gate which is extended in opposite directions from one another. This allows one to take advantage of the space on the cell normally consumed by the isolation regions, to extend the floating gates without increasing the layouts of the cells. Also, an easily scalable design is based on establishing conductive spacers on the sides of floating gate deposition layers which are used for self-alignment of the source and drain. According to this structure, a floating gate deposition is first laid down and used for establishing self-aligned source and drain diffusion regions. After deposition of the source and drain, conductive spacers are deposited on the sides of the first floating gate structure. These conductive spacers can be deposited in a symmetrical fashion, and are easily scalable to large scale arrays of flash EPROM designs.
摘要翻译：非接触式闪存EPROM单元和阵列设计及其制造方法产生致密的，可分割的闪存EPROM芯片。此外，扩展浮动栅极结构和用于制造扩展浮栅的方法允许具有非常小的设计规则的闪存EPROM电路中的较高的电容耦合比。浮置栅极以排列 - 源极 - 漏极结构中的对称方式延伸，使得每对单元电池具有彼此相反方向延伸的浮动栅极。这允许人们利用通常由隔离区域消耗的单元上的空间来扩展浮动栅极而不增加单元的布局。此外，易于扩展的设计是基于在用于源极和漏极的自对准的浮栅沉积层的侧面上建立导电间隔物。根据该结构，首先放置浮置栅极沉积并用于建立自对准的源极和漏极扩散区域。在沉积源极和漏极之后，导电间隔物沉积在第一浮栅结构的侧面上。这些导电间隔物可以以对称的方式沉积，并且易于扩展到闪存EPROM设计的大规模阵列。

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