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1. 发明授权

US5627838A Automatic test circuitry with non-volatile status write 失效
标题翻译：具有非易失性状态写入的自动测试电路
公开(公告)号：US5627838A
公开(公告)日：1997-05-06
申请号：US129419
申请日：1993-09-30
申请人： Tien-Ler Lin , Tom D. Yiu , Ray L. Wan , Kong-Mou Liou
发明人： Tien-Ler Lin , Tom D. Yiu , Ray L. Wan , Kong-Mou Liou
IPC分类号： G11C17/00 , G11C29/00 , G11C29/02 , G11C29/44 , G11C29/48
CPC分类号： G11C29/44 , G11C29/48
摘要： An integrated circuit (IC) includes a functional module such as FLASH memory with automatic program and erase circuits, test circuitry coupled with the functional module which executes a test of the functional module and generates status information as a result of the test, and non-volatile status write circuitry coupled with the test circuitry on the chip. A circuit in the non-volatile status write circuitry is responsive to the test of the functional circuitry to write the status information to the non-volatile memory. A port on the integrated circuit is coupled to the non-volatile memory through which the status information stored in the non-volatile memory is accessible in a test read mode to external devices. In a FLASH EPROM embodiment, the IC includes an array of FLASH EPROM memory cells, a test set of FLASH EPROM memory cells, and a port through which data in the array is accessible by external devices. Program and erase circuitry, coupled to the array, has a test mode to exercise the program and erase circuitry to generate status information indicating results of the test and test read mode to read out the status information. Non-volatile status write circuitry is coupled to the program and erase circuitry and the test set, and writes the status information to the test set. The program and erase circuits include retry counts with programmable thresholds for reducing the test times of the devices.
摘要翻译：集成电路（IC）包括诸如具有自动编程和擦除电路的闪速存储器的功能模块，与功能模块耦合的测试电路，其执行功能模块的测试并且作为测试的结果生成状态信息，与芯片上的测试电路耦合的易失性状态写入电路。非易失性状态写入电路中的电路响应于功能电路的测试以将状态信息写入非易失性存储器。集成电路上的端口耦合到非易失性存储器，通过该非易失性存储器，存储在非易失性存储器中的状态信息可以以测试读取模式访问到外部设备。在FLASH EPROM实施例中，IC包括闪存EPROM存储器单元的阵列，FLASH EPROM存储器单元的测试组以及阵列中的数据可由外部设备访问的端口。耦合到阵列的编程和擦除电路具有运行程序和擦除电路的测试模式，以产生指示测试结果的状态信息和测试读取模式以读出状态信息。非易失性状态写入电路耦合到程序和擦除电路和测试集，并将状态信息写入测试集。程序和擦除电路包括具有可编程阈值的重试计数，以减少器件的测试时间。

2. 发明授权

US5818848A Automatic test circuitry with non-volatile status write 失效
标题翻译：具有非易失性状态写入的自动测试电路
公开(公告)号：US5818848A
公开(公告)日：1998-10-06
申请号：US770479
申请日：1996-12-20
申请人： Tien-Ler Lin , Tom Dang-Hsing Yiu , Ray L. Wan , Kong-Mou Liou
发明人： Tien-Ler Lin , Tom Dang-Hsing Yiu , Ray L. Wan , Kong-Mou Liou
IPC分类号： G11C17/00 , G11C29/00 , G11C29/02 , G11C29/44 , G11C29/48
CPC分类号： G11C29/44 , G11C29/48
摘要： An integrated circuit comprises a functional module such as a FLASH memory with automatic program and erase circuits, test circuitry coupled with the functional module which executes a test of the functional module and generates status information as a result of the test, and non-volatile status write circuitry coupled with the test circuitry on the chip. A circuit in the non-volatile status write circuitry is responsive to the test of the functional circuitry to write the status information to the non-volatile memory. A port is provided on the integrated circuit coupled to the non-volatile memory through which the status information stored in the non-volatile memory is accessible in a test read mode to external devices. In a FLASH EPROM embodiment, the IC includes an array of FLASH EPROM memory cells and a port through which data in the array is accessible by external devices. A test set of FLASH EPROM memory cells is provided in the array. Program and erase circuitry, coupled to the array, has a test mode to exercise the program and erase circuitry to generate status information indicating results of the test and test read mode to read out the status information. Non-volatile status write circuitry, is coupled to the program and erase circuitry and the test set, and writes the status information to the test set. The program and erase circuits include retry counts with programmable thresholds for reducing the test times of the devices.
摘要翻译：集成电路包括诸如具有自动编程和擦除电路的闪存的功能模块，与功能模块耦合的测试电路，其执行功能模块的测试并且作为测试的结果生成状态信息，以及非易失性状态写入电路与芯片上的测试电路耦合。非易失性状态写入电路中的电路响应于功能电路的测试以将状态信息写入非易失性存储器。在与非易失性存储器耦合的集成电路上提供端口，通过该端口，存储在非易失性存储器中的状态信息可以以测试读取模式访问到外部设备。在FLASH EPROM实施例中，IC包括闪存EPROM存储器单元阵列和阵列中的数据可由外部设备访问的端口。阵列中提供了一组FLASH EPROM存储单元。耦合到阵列的编程和擦除电路具有运行程序和擦除电路的测试模式，以产生指示测试结果的状态信息和测试读取模式以读出状态信息。非易失性状态写入电路耦合到程序和擦除电路和测试仪，并将状态信息写入测试仪。程序和擦除电路包括具有可编程阈值的重试计数，以减少器件的测试时间。

3. 发明授权

US5748535A Advanced program verify for page mode flash memory 失效
标题翻译：高级程序验证页面模式闪存
公开(公告)号：US5748535A
公开(公告)日：1998-05-05
申请号：US612968
申请日：1996-03-04
申请人： Tien-Ler Lin , Kota Soejima , Jun Takahashi , Chun-Hsiung Hung , Kong-Mou Liou , Ray-Lin Wan
发明人： Tien-Ler Lin , Kota Soejima , Jun Takahashi , Chun-Hsiung Hung , Kong-Mou Liou , Ray-Lin Wan
IPC分类号： G11C16/04 , G11C16/32 , G11C16/34 , G11C7/00
CPC分类号： G11C16/3436 , G11C16/0491 , G11C16/32 , G11C16/3445 , G11C16/3459
摘要： Flash EEPROM cell and array designs, and methods for programming the same result in efficient and accurate programming of a flash EEPROM chip. The flash EEPROM chip comprises a memory array including at least M rows and N columns of flash EEPROM cells. M word lines are each coupled to the flash EEPROM cells in one of the M rows of flash EEPROM cells. A plurality of bit lines are each coupled to the flash EEPROM cells in one of the N columns of flash EEPROM cells. A page buffer coupled to the plurality of bit lines supplies input data to N columns of flash EEPROM cells. Write control circuitry supplies programming voltages for programming input data to the flash EEPROM cells in response to the input data stored in the data input buffer. Verify circuitry automatically verifies programming of the page by resetting bits in the page buffer for each cell which passes.
摘要翻译： PCT No.PCT / US95 / 00077 Sec。 371日期：1996年3月4日 102（e）1996年3月4日PCT PCT 1995年1月5日PCT公布。公开号WO96 / 21227 日期1996年7月11日闪存EEPROM单元和阵列设计以及用于编程相同结果的快速EEPROM芯片的高效准确编程的方法。快闪EEPROM芯片包括至少包括M行和N列快闪EEPROM单元的存储器阵列。 M个字线各自耦合到M行的快闪EEPROM单元之一中的快闪EEPROM单元。多个位线各自耦合到快速EEPROM单元的N列之一中的快闪EEPROM单元。耦合到多个位线的页缓冲器将快速EEPROM单元的输入数据提供给N列。响应于存储在数据输入缓冲器中的输入数据，写控制电路提供用于将输入数据编程到闪存EEPROM单元的编程电压。验证电路通过复位通过的每个单元的页面缓冲区中的位来自动验证页面的编程。

4. 发明授权

US5691945A Technique for reconfiguring a high density memory 失效
标题翻译：重构高密度存储器的技术
公开(公告)号：US5691945A
公开(公告)日：1997-11-25
申请号：US605100
申请日：1996-03-01
申请人： Kong-Mou Liou , Tom Dang-Hsing Yiu , Ray-Lin Wan , Yao-Wu Cheng , Chun-Hsiung Hung , Ting-Chung Hu , Tien-Ler Lin
发明人： Kong-Mou Liou , Tom Dang-Hsing Yiu , Ray-Lin Wan , Yao-Wu Cheng , Chun-Hsiung Hung , Ting-Chung Hu , Tien-Ler Lin
IPC分类号： G11C8/08 , G11C8/10 , G11C8/12 , G11C29/00 , G11C7/00
CPC分类号： G11C29/76 , G11C8/08 , G11C8/10 , G11C8/12
摘要： A flexible technique for improving yield of manufacturing of high density of memory devices, such as flash EEPROM, involves reconfiguring an integrated circuit memory array having a plurality of sectors selected by an address decoder in response to an N bit field in an address. If defective sectors are detected in the array, it is partitioned to disable defective sectors by configuring a sector decoder to prevent access to the defective sectors while maintaining sequential addressing remaining sectors in the array. The step of partitioning includes configuring the sector decoder to replace a defective sector in one half of the array by another sector in the other half of the array having N-m of the N address bits in common with the defective sector when m is between 1 and N-1.
摘要翻译： PCT No.PCT / US95 / 06990第 371日期1996年3月1日 102（e）1996年3月1日PCT 1995年5月31日PCT PCT。公开号WO96 / 38845 日期1996年12月5日用于提高高密度存储器件（例如闪存EEPROM）的制造成品率的灵活技术涉及重新配置具有由地址解码器选择的多个扇区的集成电路存储器阵列，以响应于N位字段一个地址如果在阵列中检测到有缺陷的扇区，则通过配置扇区解码器以防止对阵列中的剩余扇区的顺序寻址，同时对阵列解码器进行划分以禁用缺陷扇区。分割步骤包括配置扇区解码器以在阵列的另一半中的另外一个扇区替换阵列的一半中的缺陷扇区，其中，当m在1和N之间时，具有与缺陷扇区相同的N个地址位的Nm -1。

5. 发明授权

US06400634B1 Technique for increasing endurance of integrated circuit memory 有权
标题翻译：提高集成电路存储器耐久性的技术
公开(公告)号：US06400634B1
公开(公告)日：2002-06-04
申请号：US09029952
申请日：1999-06-18
申请人： Kong-Mou Liou , Ting-Chung Hu , Ray-Lin Wan , Fuchia Shone
发明人： Kong-Mou Liou , Ting-Chung Hu , Ray-Lin Wan , Fuchia Shone
IPC分类号： G11C800
CPC分类号： G11C16/3495 , G11C16/08
摘要： A method increases endurance of an array of memory cells which have an endurance specified according to the number of change cycles that the memory cell can endure within a performance tolerance. The method is based on arranging the array into a plurality of sectors, and assigning a subset of addresses for storage of data structure expected to change a number of times that is sufficient to exceed the specified endurance of the memory cell in the array. A record is maintained indicating one of the plurality of sectors as a current sector, directing accesses using the subset of addresses to the current sector, counting changes executed to memory cells identified by the subset of addresses for the current sector, and changing the current sector to another one of the plurality of sectors when the count of changes exceeds the threshold.
摘要翻译：一种方法提高了存储器单元阵列的耐久性，其具有根据存储器单元在性能容限内可以承受的变化周期的数量来指定的耐久性。该方法基于将阵列布置成多个扇区，并且分配用于存储数据结构的地址的子集，其预期将改变足以超过阵列中的存储器单元的指定耐久性的次数。保持指示多个扇区中的一个作为当前扇区的记录，将使用地址子集的访问定向到当前扇区，对对当前扇区的地址子集标识的存储器单元进行计数改变，以及改变当前扇区当变化的计数超过阈值时，到多个扇区中的另一个扇区。

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