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1. 发明授权

US08700874B2 Digital counter segmented into short and long access time memory 有权
标题翻译：数字计数器分为短和长访问时间存储器
公开(公告)号：US08700874B2
公开(公告)日：2014-04-15
申请号：US12890479
申请日：2010-09-24
申请人： Edmund G. Chen , Brian Alleyne , Robert Hathaway , Ranjit J. Rozario , Todd D. Basso
发明人： Edmund G. Chen , Brian Alleyne , Robert Hathaway , Ranjit J. Rozario , Todd D. Basso
IPC分类号： G06F12/00
CPC分类号： H03K21/38 , H03K21/16
摘要： A method performed in a memory controller for maintaining segmented counters split into primary and secondary memories, the primary memory faster. Events occur that require incrementing one of the segmented counters and the memory controller responds by incrementing a corresponding primary part in the primary memory. Each time a primary part is rolling over the memory controller determines that a secondary part should be updated. Also, the memory controller periodically determines that the secondary part of a segmented counter should be opportunistically updated. The opportunistic update is based on a probability function and a random number. The secondary part includes at least all of bits of the segmented counter not in the primary part and is stored in the secondary memory. Each time an update to the secondary part occurs, both the secondary part and primary part of the segmented counter must be updated.
摘要翻译：一种在存储器控制器中执行的方法，用于将分段计数器分为主存储器和次存储器，主存储器更快。发生需要增加分段计数器之一并且存储器控制器通过增加主存储器中的相应主要部分来进行响应的事件。每次主要部件在内存控制器上滚动时，都会确定应该更新次要部件。此外，存储器控制器周期性地确定分段计数器的次要部分应该被机会性地更新。机会更新是基于概率函数和随机数。辅助部分至少包括不在主要部分中的分段计数器的所有位，并存储在辅助存储器中。每次发生对次要部件的更新时，分段计数器的辅助部件和主要部件都必须更新。

2. 发明授权

US07254651B2 Scheduler for a direct memory access device having multiple channels 有权
标题翻译：具有多个通道的直接存储器访问设备的调度器
公开(公告)号：US07254651B2
公开(公告)日：2007-08-07
申请号：US09740669
申请日：2000-12-18
申请人： Ranjit J. Rozario , Ravikrishna Cherukuri
发明人： Ranjit J. Rozario , Ravikrishna Cherukuri
IPC分类号： G06F3/00
CPC分类号： G06F3/0659 , G06F3/061 , G06F3/0674 , G06F13/28
摘要： A scheduler configured to schedule multiple channels of a Direct Memory Access (DMA) device includes a shift structure having entries corresponding to the multiple channels to be scheduled. Each entry in the shift structure includes multiple fields. Each entry also includes a weight that is determined based on these multiple fields. The scheduler also includes a comparison-logic circuit that is configured to then sort the entries based on their respective weights.
摘要翻译：被配置为调度直接存储器访问（DMA）设备的多个通道的调度器包括具有对应于要调度的多个信道的条目的移位结构。移位结构中的每个条目包括多个字段。每个条目还包括基于这些多个字段确定的权重。调度器还包括比较逻辑电路，其被配置为基于它们各自的权重对条目进行排序。

3. 发明授权

US06618793B2 Free memory manager scheme and cache 有权
公开(公告)号：US06618793B2
公开(公告)日：2003-09-09
申请号：US09740670
申请日：2000-12-18
申请人： Ranjit J. Rozario , Ravikrishna Cherukuri
发明人： Ranjit J. Rozario , Ravikrishna Cherukuri
IPC分类号： G06F1202
CPC分类号： G06F12/023 , G06F12/0875
摘要： Free memory can be managed by creating a free list having entries with address of free memory location. A portion of this free list can then be cached in a cache that includes an upper threshold and a lower threshold. Additionally, a plurality of free lists are created for a plurality of memory banks in a plurality of memory channels. A free list is created for each memory bank in each memory channel. Entries from these free lists are written to a global cache. The entries written to the global cache are distributed between the memory channels and memory banks.

4. 发明授权

US5745732A Computer system including system controller with a write buffer and plural read buffers for decoupled busses 失效
标题翻译：包括具有写入缓冲器的系统控制器和用于解耦总线的多个读取缓冲器的计算机系统
公开(公告)号：US5745732A
公开(公告)日：1998-04-28
申请号：US340132
申请日：1994-11-15
申请人： Ravikrishna V. Cherukuri , Ranjit J. Rozario
发明人： Ravikrishna V. Cherukuri , Ranjit J. Rozario
IPC分类号： G06F12/08 , G06F13/00
CPC分类号： G06F12/0835
摘要： A computer system includes a processor having a cache memory and coupled to a system controller through a processor bus, a main memory coupled to the system controller through a dedicated memory bus, and a local bus master coupled to the system controller through a local bus. The system controller includes a write register and a read register that form a first path for coupling bus signals between the processor bus and main memory, and the system controller also includes a second read register that with the write buffer forms a second path to the main memory for coupling bus signals between the local bus and main memory. The first and second paths of the system controller decouple the processor and local buses, allowing processor-cache operations to proceed concurrently with operations between the local bus master and main memory. The first and second read buffers are fully snooped and implement replacement schemes that allow them to function as caches for the the processor and the local bus master, respectively, and a snoop tag register in the system controller stores recently snooped main memory addresses to eliminate redundant snoop cycles to the processor.
摘要翻译：计算机系统包括具有高速缓存存储器并通过处理器总线耦合到系统控制器的处理器，通过专用存储器总线耦合到系统控制器的主存储器，以及通过本地总线耦合到系统控制器的本地总线主机。系统控制器包括形成用于在处理器总线和主存储器之间耦合总线信号的第一路径的写寄存器和读寄存器，并且系统控制器还包括第二读寄存器，其与写缓冲器形成到主存储器的第二路径用于在本地总线和主存储器之间耦合总线信号的存储器。系统控制器的第一和第二路径使处理器和本地总线分离，允许处理器 - 高速缓存操作与本地总线主机和主存储器之间的操作同时进行。第一个和第二个读取缓冲区被完全窥探并实现了允许它们分别用作处理器和本地总线主机的高速缓存的替换方案，并且系统控制器中的监听标签寄存器存储最近被窥探的主存储器地址以消除冗余窥探循环到处理器。

5. 发明申请

US20120079228A1 DIGITAL COUNTER SEGMENTED INTO SHORT AND LONG ACCESS TIME MEMORY 有权
标题翻译：数字计数器分为短暂和长时间访问时间记忆
公开(公告)号：US20120079228A1
公开(公告)日：2012-03-29
申请号：US12890479
申请日：2010-09-24
申请人： EDMUND G. CHEN , BRIAN ALLEYNE , ROBERT HATHAWAY , RANJIT J. ROZARIO , TODD D. BASSO
发明人： EDMUND G. CHEN , BRIAN ALLEYNE , ROBERT HATHAWAY , RANJIT J. ROZARIO , TODD D. BASSO
IPC分类号： G06F12/00
CPC分类号： H03K21/38 , H03K21/16
摘要： A method performed in a memory controller for maintaining segmented counters split into primary and secondary memories, the primary memory faster. Events occur that require incrementing one of the segmented counters and the memory controller responds by incrementing a corresponding primary part in the primary memory. Each time a primary part is rolling over the memory controller determines that a secondary part should be updated. Also, the memory controller periodically determines that the secondary part of a segmented counter should be opportunistically updated. The opportunistic update is based on a probability function and a random number. The secondary part includes at least all of bits of the segmented counter not in the primary part and is stored in the secondary memory. Each time an update to the secondary part occurs, both the secondary part and primary part of the segmented counter must be updated.
摘要翻译：一种在存储器控制器中执行的方法，用于将分段计数器分为主存储器和次存储器，主存储器更快。发生需要增加分段计数器之一并且存储器控制器通过增加主存储器中的相应主要部分来进行响应的事件。每次主要部件在内存控制器上滚动时，都会确定应该更新次要部件。此外，存储器控制器周期性地确定分段计数器的次要部分应该被机会性地更新。机会更新是基于概率函数和随机数。辅助部分至少包括不在主要部分中的分段计数器的所有位，并存储在辅助存储器中。每次发生对次要部件的更新时，分段计数器的辅助部件和主要部件都必须更新。

6. 发明授权

US06345328B1 Gear box for multiple clock domains 有权
标题翻译：多个时钟域的变速箱
公开(公告)号：US06345328B1
公开(公告)日：2002-02-05
申请号：US09328940
申请日：1999-06-09
申请人： Ranjit J. Rozario , Sridhar P. Subramanian , Ravikrishna Cherukuri
发明人： Ranjit J. Rozario , Sridhar P. Subramanian , Ravikrishna Cherukuri
IPC分类号： G06F1314
CPC分类号： G06F13/4059
摘要： A gear box module or circuit can act as an interface for transferring data from a first clock domain to a second clock domain. The gear box circuit uses a level sensitive memory element coupled to an input selection circuit to receive data from logic in the first clock domain and provide the data to logic in the second clock domain. An input selection signal causes the selection circuit to select the input source for the level sensitive memory element, thereby allowing the proper signal to be provided as output to logic in the second clock domain. Additionally, the gear box can provide the proper output signal for logic in the second domain using circuitry to alternately mask the gear box output. The gear box receives control signals, including for example the input selection signal, from control circuitry. The logic in each clock domain does not have to be aware of the clock frequency on the other side of the gear box, nor does it need to be aware of the ratio of clock frequencies between clock domains. Consequently, the logic in each domain is simplified, the gear box circuit itself can be independent of the gear ratio (i.e., the ratio of clock frequencies), timing delays can be reduced, and metastability can be avoided.
摘要翻译：齿轮箱模块或电路可以用作将数据从第一时钟域传送到第二时钟域的接口。齿轮箱电路使用耦合到输入选择电路的电平敏感存储器元件来从第一时钟域中的逻辑接收数据，并将数据提供给第二时钟域中的逻辑。输入选择信号使选择电路选择电平敏感存储元件的输入源，从而允许适当的信号作为第二时钟域中逻辑的输出。此外，齿轮箱可以使用电路交替地掩蔽齿轮箱输出来为第二域中的逻辑提供适当的输出信号。齿轮箱从控制电路接收控制信号，包括例如输入选择信号。每个时钟域中的逻辑不需要知道齿轮箱另一侧的时钟频率，也不需要注意时钟域之间的时钟频率比。因此，每个领域的逻辑被简化，齿轮箱电路本身可以独立于传动比（即，时钟频率的比率），可以减少定时延迟，并且可以避免亚稳态。

7. 发明授权

US06253262B1 Arbitrating FIFO implementation which positions input request in a buffer according to its status 有权
标题翻译：仲裁FIFO实现，它根据其状态将输入请求定位在缓冲器中
公开(公告)号：US06253262B1
公开(公告)日：2001-06-26
申请号：US09151862
申请日：1998-09-11
申请人： Ranjit J. Rozario , Scott Waldron , Ravikrishna Cherukuri
发明人： Ranjit J. Rozario , Scott Waldron , Ravikrishna Cherukuri
IPC分类号： G06F1318
CPC分类号： G06F13/18
摘要： A system (100) for automatically ordering a request for access to a system memory (14) is disclosed. The system (100) includes a re-ordering buffer (102) having a data input (120) and a data output (122) and an input request position identifier (104) associated with the re-ordering buffer (102). The input request position identifier (104) indicates a position of the data input (120) in the re-ordering buffer (102) for the new request based on a status of the request. A method (230) of ordering a request for access to a system memory (14) in a buffer (102) is also disclosed and includes initiating a request (232) for access to the system memory (14), wherein the request contains a status indicating a priority of the request. The status of the request is evaluated (234) to determine whether the request is a high priority request or a low priority request and a location for inputting the access request into the buffer (102) is identified (236) in response to the evaluation. One or more previously requested access requests are then shifted (240) within the buffer if necessary to make room for the access request at the identified location and the new access request is inserted into the buffer at the identified location (242).
摘要翻译：公开了一种用于自动排序访问系统存储器（14）的请求的系统（100）。系统（100）包括具有与重新排序缓冲器（102）相关联的数据输入（120）和数据输出（122）以及输入请求位置标识符（104）的重排序缓冲器（102）。输入请求位置标识符（104）基于请求的状态来指示重新排序缓冲器（102）中针对新请求的数据输入（120）的位置。还公开了排序对缓冲器（102）中的系统存储器（14）的访问请求的方法（230），并且包括发起用于访问系统存储器（14）的请求（232），其中该请求包含表示请求的优先级的状态。评估请求的状态（234）以确定请求是高优先级请求还是低优先级请求，并且响应于评估识别用于将访问请求输入缓冲器（102）的位置（236）。如果需要，一个或多个先前请求的访问请求在缓冲器内被移位（240），以便为所识别的位置处的访问请求腾出空间，并且新的访问请求被插入到所识别的位置处的缓冲器中（242）。

8. 发明授权

US06961822B2 Free memory manager scheme and cache 有权
标题翻译：免费内存管理器方案和缓存
公开(公告)号：US06961822B2
公开(公告)日：2005-11-01
申请号：US10650317
申请日：2003-08-27
申请人： Ranjit J. Rozario , Ravikrishna Cherukuri
发明人： Ranjit J. Rozario , Ravikrishna Cherukuri
IPC分类号： G06F12/02
CPC分类号： G06F12/023 , G06F12/0875
摘要： Free memory can be managed by creating a free list having entries with address of free memory location. A portion of this free list can then be cached in a cache that includes an upper threshold and a lower threshold. Additionally, a plurality of free lists are created for a plurality of memory banks in a plurality of memory channels. A free list is created for each memory bank in each memory channel. Entries from these free lists are written to a global cache. The entries written to the global cache are distributed between the memory channels and memory banks.
摘要翻译：可以通过创建一个具有空闲内存地址的条目的空闲列表来管理可用内存。然后，这个空闲列表的一部分可以被缓存在包括上限阈值和下限阈值的缓存中。此外，为多个存储器通道中的多个存储体创建多个空闲列表。为每个存储器通道中的每个存储体创建一个空闲列表。这些免费列表中的条目将写入全局缓存。写入全局缓存的条目分布在存储器通道和存储体之间。

9. 发明授权

US06173378B2 Method for ordering a request for access to a system memory using a reordering buffer or FIFO 有权
标题翻译：使用重新排序缓冲区或FIFO排序访问系统存储器的请求的方法
公开(公告)号：US06173378B2
公开(公告)日：2001-01-09
申请号：US09151861
申请日：1998-09-11
申请人： Ranjit J. Rozario , Sridhar P. Subramanian , Ravikrishna Cherukuri
发明人： Ranjit J. Rozario , Sridhar P. Subramanian , Ravikrishna Cherukuri
IPC分类号： G06F1200
CPC分类号： G06F13/18
摘要： A method (320) of implementing a set of ordering rules for executing requests for access to a system memory (14) includes the steps of identifying a request status (322) for a new request for access to the system memory (14) and assigning a tag to the new access request (324) based on the status of the new request. A control circuit (106) inserts the new access request (340) into one of a read buffer (302) or a write buffer (304) at a specified location within one or the read or write buffers (302, 304) based on the status of the new access request. When the new access request is enqueued (342) and sent to an arbitration circuit (306), the requests are executed in an order with another access request (344) from the other of the read or write buffer based on the request status and the tag of the new request.
摘要翻译：实现用于执行对系统存储器（14）的访问的请求的一组排序规则的方法（320）包括以下步骤：识别用于访问系统存储器（14）的新请求的请求状态（322）和分配基于新请求的状态的新的访问请求（324）的标签。控制电路（106）基于所述新的访问请求（340）将所述新的访问请求（340）插入在一个或所述读取或写入缓冲器（302,304）内的指定位置处的读取缓冲器（302）或写入缓冲器（304）新访问请求的状态。当新的访问请求入队（342）并发送到仲裁电路（306）时，根据请求状态和从读取或写入缓冲器中的另一个的另一访问请求（344）的顺序执行请求，标签的新请求。

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