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1. 发明授权

US08347040B2 Latency reduction for cache coherent bus-based cache 有权
标题翻译：缓存相关总线缓存的延迟降低
公开(公告)号：US08347040B2
公开(公告)日：2013-01-01
申请号：US13089050
申请日：2011-04-18
申请人： Brian P. Lilly , Sridhar P. Subramanian , Ramesh Gunna
发明人： Brian P. Lilly , Sridhar P. Subramanian , Ramesh Gunna
IPC分类号： G06F12/00
CPC分类号： G06F12/0831 , G06F12/084
摘要： In one embodiment, a system comprises a plurality of agents coupled to an interconnect and a cache coupled to the interconnect. The plurality of agents are configured to cache data. A first agent of the plurality of agents is configured to initiate a transaction on the interconnect by transmitting a memory request, and other agents of the plurality of agents are configured to snoop the memory request from the interconnect. The other agents provide a response in a response phase of the transaction on the interconnect. The cache is configured to detect a hit for the memory request and to provide data for the transaction to the first agent prior to the response phase and independent of the response.
摘要翻译：在一个实施例中，系统包括耦合到互连的多个代理和耦合到互连的高速缓存。多个代理被配置为高速缓存数据。多个代理的第一代理被配置为通过发送存储器请求来在互连上发起事务，并且多个代理中的其他代理被配置为从互连窥探存储器请求。其他代理在交互的响应阶段提供响应。高速缓存被配置为检测存储器请求的命中，并且在响应阶段之前将事务的数据提供给第一代理，并且独立于响应。

2. 发明申请

US20120017135A1 Combined Single Error Correction/Device Kill Detection Code 有权
标题翻译：组合单错误纠正/设备杀毒检测码
公开(公告)号：US20120017135A1
公开(公告)日：2012-01-19
申请号：US13246736
申请日：2011-09-27
申请人： Brian P. Lilly , Robert Gries , Sridhar P. Subramanian , Sukalpa Biswas , Hao Chen
发明人： Brian P. Lilly , Robert Gries , Sridhar P. Subramanian , Sukalpa Biswas , Hao Chen
IPC分类号： H03M13/09 , G06F11/08
CPC分类号： H03M13/09 , G06F11/1004
摘要： In one embodiment, an apparatus includes a check/correct circuit coupled to a control circuit. The check/correct circuit is coupled to receive a block of data and corresponding check bits. The block of data is received as N transmissions, each transmission including M data bits and L check bits. The check/correct circuit is configured to detect one or more errors in each of a plurality of non-overlapping windows of K bits in the M data bits, responsive to the M data bits and the L check bits. The control circuit is configured to record which of the plurality of windows have had errors detected and, if a given window of the plurality of windows has had errors detected in each of the N transmissions of the block, the control circuit is configured to signal a device failure. Each of K, L, M, and N are integers greater than one.
摘要翻译：在一个实施例中，装置包括耦合到控制电路的检查/校正电路。检查/校正电路被耦合以接收数据块和相应的校验位。数据块作为N个传输被接收，每个传输包括M个数据位和L个校验位。检查/校正电路被配置为响应于M个数据位和L个校验位来检测M个数据位中K位的多个非重叠窗口中的每一个中的一个或多个错误。控制电路被配置为记录多个窗口中哪一个具有检测到的错误，并且如果多个窗口的给定窗口在块的N个传输中的每一个中都检测到错误，则控制电路被配置为发信号设备故障 K，L，M和N中的每一个是大于1的整数。

3. 发明授权

US07991928B2 Retry mechanism 有权
标题翻译：重试机制
公开(公告)号：US07991928B2
公开(公告)日：2011-08-02
申请号：US12408410
申请日：2009-03-20
申请人： James B. Keller , Sridhar P. Subramanian , Ramesh Gunna
发明人： James B. Keller , Sridhar P. Subramanian , Ramesh Gunna
IPC分类号： G06F3/00 , G06F15/167
CPC分类号： G06F12/0831 , G06F13/362 , G06F13/4213 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： An interface unit may comprise a buffer configured to store requests that are to be transmitted on an interconnect and a control unit coupled to the buffer. In one embodiment, the control unit is coupled to receive a retry response from the interconnect during a response phase of a first transaction for a first request stored in the buffer. The control unit is configured to record an identifier supplied on the interconnect with the retry response that identifies a second transaction that is in progress on the interconnect. The control unit is configured to inhibit reinitiation of the first transaction at least until detecting a second transmission of the identifier. In another embodiment, the control unit is configured to assert a retry response during a response phase of a first transaction responsive to a snoop hit of the first transaction on a first request stored in the buffer for which a second transaction is in progress on the interconnect. The control unit is further configured to provide an identifier of the second transaction with the retry response.
摘要翻译：接口单元可以包括被配置为存储要在互连上发送的请求的缓冲器和耦合到缓冲器的控制单元。在一个实施例中，控制单元被耦合以在对于存储在缓冲器中的第一请求的第一事务的响应阶段期间从互连接收重试响应。控制单元被配置为记录在互连上提供的标识符，该重试响应标识互连上正在进行的第二事务。控制单元被配置为至少在检测到标识符的第二次传输之前禁止第一事务的重新发起。在另一个实施例中，控制单元被配置为在第一事务的响应阶段响应第一事务的窥探命中在存储在第二事务在互连上的第二事务的缓冲器中的第一请求时断言重试响应。控制单元还被配置为提供具有重试响应的第二事务的标识符。

4. 发明申请

US20100235675A1 Non-blocking Address Switch with Shallow Per Agent Queues 有权
标题翻译：非阻塞地址交换机与每个代理队列相邻
公开(公告)号：US20100235675A1
公开(公告)日：2010-09-16
申请号：US12787865
申请日：2010-05-26
申请人： Sridhar P. Subramanian , James B. Keller , Ruchi Wadhawan , George Kong Yiu , Ramesh Gunna
发明人： Sridhar P. Subramanian , James B. Keller , Ruchi Wadhawan , George Kong Yiu , Ramesh Gunna
IPC分类号： G06F13/14 , G06F1/04 , G06F13/362
CPC分类号： G06F13/362 , G06F13/4022
摘要： In one embodiment, a switch is configured to be coupled to an interconnect. The switch comprises a plurality of storage locations and an arbiter control circuit coupled to the plurality of storage locations. The plurality of storage locations are configured to store a plurality of requests transmitted by a plurality of agents. The arbiter control circuit is configured to arbitrate among the plurality of requests stored in the plurality of storage locations. A selected request is the winner of the arbitration, and the switch is configured to transmit the selected request from one of the plurality of storage locations onto the interconnect. In another embodiment, a system comprises a plurality of agents, an interconnect, and the switch coupled to the plurality of agents and the interconnect. In another embodiment, a method is contemplated.
摘要翻译：在一个实施例中，开关被配置为耦合到互连。开关包括多个存储位置和耦合到多个存储位置的仲裁器控制电路。多个存储位置被配置为存储由多个代理发送的多个请求。仲裁器控制电路被配置为在存储在多个存储位置中的多个请求之间进行仲裁。所选择的请求是仲裁的赢家，并且交换机被配置为将所选择的请求从多个存储位置之一发送到互连上。在另一个实施例中，系统包括多个代理，互连和耦合到多个代理和互连的开关。在另一个实施例中，预期了一种方法。

5. 发明申请

US20080307168A1 Latency Reduction for Cache Coherent Bus-Based Cache 有权
标题翻译：缓存相干总线缓存的延迟降低
公开(公告)号：US20080307168A1
公开(公告)日：2008-12-11
申请号：US11758219
申请日：2007-06-05
申请人： Brian P. Lilly , Sridhar P. Subramanian , Ramesh Gunna
发明人： Brian P. Lilly , Sridhar P. Subramanian , Ramesh Gunna
IPC分类号： G06F12/00
CPC分类号： G06F12/0831 , G06F12/084
摘要： In one embodiment, a system comprises a plurality of agents coupled to an interconnect and a cache coupled to the interconnect. The plurality of agents are configured to cache data. A first agent of the plurality of agents is configured to initiate a transaction on the interconnect by transmitting a memory request, and other agents of the plurality of agents are configured to snoop the memory request from the interconnect. The other agents provide a response in a response phase of the transaction on the interconnect. The cache is configured to detect a hit for the memory request and to provide data for the transaction to the first agent prior to the response phase and independent of the response.
摘要翻译：在一个实施例中，系统包括耦合到互连的多个代理和耦合到互连的高速缓存。多个代理被配置为高速缓存数据。多个代理的第一代理被配置为通过发送存储器请求来在互连上发起事务，并且多个代理中的其他代理被配置为从互连窥探存储器请求。其他代理在交互的响应阶段提供响应。高速缓存被配置为检测存储器请求的命中，并且在响应阶段之前将事务的数据提供给第一代理，并且独立于响应。

6. 发明授权

US07461190B2 Non-blocking address switch with shallow per agent queues 有权
标题翻译：非阻塞地址切换，每个代理队列较浅
公开(公告)号：US07461190B2
公开(公告)日：2008-12-02
申请号：US11201581
申请日：2005-08-11
申请人： Sridhar P. Subramanian , James B. Keller , Ruchi Wadhawan , George Kong Yiu , Ramesh Gunna
发明人： Sridhar P. Subramanian , James B. Keller , Ruchi Wadhawan , George Kong Yiu , Ramesh Gunna
IPC分类号： G06F13/00
CPC分类号： G06F13/362 , G06F13/4022
摘要： In one embodiment, a switch is configured to be coupled to an interconnect. The switch comprises a plurality of storage locations and an arbiter control circuit coupled to the plurality of storage locations. The plurality of storage locations are configured to store a plurality of requests transmitted by a plurality of agents. The arbiter control circuit is configured to arbitrate among the plurality of requests stored in the plurality of storage locations. A selected request is the winner of the arbitration, and the switch is configured to transmit the selected request from one of the plurality of storage locations onto the interconnect. In another embodiment, a system comprises a plurality of agents, an interconnect, and the switch coupled to the plurality of agents and the interconnect. In another embodiment, a method is contemplated.
摘要翻译：在一个实施例中，开关被配置为耦合到互连。开关包括多个存储位置和耦合到多个存储位置的仲裁器控制电路。多个存储位置被配置为存储由多个代理发送的多个请求。仲裁器控制电路被配置为在存储在多个存储位置中的多个请求之间进行仲裁。所选择的请求是仲裁的赢家，并且交换机被配置为将所选择的请求从多个存储位置之一发送到互连上。在另一个实施例中，系统包括多个代理，互连和耦合到多个代理和互连的开关。在另一个实施例中，预期了一种方法。

7. 发明申请

US20080195884A1 Oversampling-Based Scheme for Synchronous Interface Communication 有权
标题翻译：基于过采样的同步接口通信方案
公开(公告)号：US20080195884A1
公开(公告)日：2008-08-14
申请号：US11740452
申请日：2007-04-26
申请人： Sridhar P. Subramanian , Sukalpa Biswas , Vincent R. von Kaenel , Priya Ananthanarayanan
发明人： Sridhar P. Subramanian , Sukalpa Biswas , Vincent R. von Kaenel , Priya Ananthanarayanan
IPC分类号： G06F1/00
CPC分类号： G06F1/04
摘要： In one embodiment, an apparatus to synchronously communicate on an interface that has an associated interface clock for a circuit that has an internal clock used internal to the circuit comprises a control circuit coupled to receive the internal clock and the interface clock. The control circuit is configured to sample the interface clock multiple times per clock cycle of the internal clock and to detect a phase difference, to a granularity of the samples, between the internal clock and the interface clock. The apparatus comprises a data path that is configured to transport data between an internal clock domain and an interface clock domain. The data path is configured to provide at least two different timings on the transported data relative to the internal clock. The control circuit is coupled to the data path and is configured to select one of the timings responsive to a detected phase difference.
摘要翻译：在一个实施例中，在具有用于电路内部使用的内部时钟的电路的相关接口时钟的接口上同步通信的装置包括耦合以接收内部时钟和接口时钟的控制电路。控制电路被配置为在内部时钟的每个时钟周期多次对接口时钟进行采样，并且在内部时钟和接口时钟之间检测到采样的粒度的相位差。该装置包括被配置为在内部时钟域和接口时钟域之间传送数据的数据路径。数据路径被配置为在传送的数据上相对于内部时钟提供至少两个不同的定时。控制电路耦合到数据路径，并且被配置为响应于检测到的相位差来选择定时之一。

8. 发明授权

US07398361B2 Combined buffer for snoop, store merging, load miss, and writeback operations 有权
标题翻译：组合缓冲区，用于侦听，存储合并，加载错误和回写操作
公开(公告)号：US07398361B2
公开(公告)日：2008-07-08
申请号：US11215604
申请日：2005-08-30
申请人： Ramesh Gunna , Po-Yung Chang , Sridhar P. Subramanian , James B. Keller , Tse-Yuh Yeh
发明人： Ramesh Gunna , Po-Yung Chang , Sridhar P. Subramanian , James B. Keller , Tse-Yuh Yeh
IPC分类号： G06F13/00
CPC分类号： G06F12/0831
摘要： In one embodiment, an interface unit comprises an address buffer and a control unit coupled to the address buffer. The address buffer is configured to store addresses of processor core requests generated by a processor core and addresses of snoop requests received from an interconnect. The control unit is configured to maintain a plurality of queues, wherein at least a first queue of the plurality of queues is dedicated to snoop requests and at least a second queue of the plurality of queues is dedicated to processor core requests. Responsive to a first snoop request received by the interface unit from the interconnect, the control unit is configured to allocate a first address buffer entry of the address buffer to store the first snoop request and to store a first pointer to the first address buffer entry in the first queue. Responsive to a first processor core request received by the interface unit from the processor core, the control unit is configured to allocate a second address buffer entry of the address buffer to store the first processor core request and to store a second pointer to the second address buffer entry in the second queue.
摘要翻译：在一个实施例中，接口单元包括地址缓冲器和耦合到地址缓冲器的控制单元。地址缓冲器被配置为存储由处理器核心产生的处理器核心请求的地址和从互连接收的窥探请求的地址。所述控制单元被配置为维护多个队列，其中所述多个队列中的至少第一队列专用于窥探请求，并且所述多个队列中的至少第二队列专用于处理器核心请求。响应于接口单元从互连接收到的第一窥探请求，控制单元被配置为分配地址缓冲器的第一地址缓冲器条目以存储第一窥探请求，并且将第一指针存储到第一地址缓冲器条目中第一个队列。响应于接口单元从处理器核心接收到的第一处理器核心请求，控制单元被配置为分配地址缓冲器的第二地址缓冲器条目以存储第一处理器核心请求并将第二指针存储到第二地址第二个队列中的缓冲区条目。

9. 发明授权

US08359414B2 Retry mechanism 有权
标题翻译：重试机制
公开(公告)号：US08359414B2
公开(公告)日：2013-01-22
申请号：US13165235
申请日：2011-06-21
申请人： James B. Keller , Sridhar P. Subramanian , Ramesh Gunna
发明人： James B. Keller , Sridhar P. Subramanian , Ramesh Gunna
IPC分类号： G06F3/00 , G06F15/167
CPC分类号： G06F12/0831 , G06F13/362 , G06F13/4213 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： An interface unit may comprise a buffer configured to store requests that are to be transmitted on an interconnect and a control unit coupled to the buffer. In one embodiment, the control unit is coupled to receive a retry response from the interconnect during a response phase of a first transaction for a first request stored in the buffer. The control unit is configured to record an identifier supplied on the interconnect with the retry response that identifies a second transaction that is in progress on the interconnect. The control unit is configured to inhibit reinitiation of the first transaction at least until detecting a second transmission of the identifier. In another embodiment, the control unit is configured to assert a retry response during a response phase of a first transaction responsive to a snoop hit of the first transaction on a first request stored in the buffer for which a second transaction is in progress on the interconnect. The control unit is further configured to provide an identifier of the second transaction with the retry response.
摘要翻译：接口单元可以包括被配置为存储要在互连上发送的请求的缓冲器和耦合到缓冲器的控制单元。在一个实施例中，控制单元被耦合以在对于存储在缓冲器中的第一请求的第一事务的响应阶段期间从互连接收重试响应。控制单元被配置为记录在互连上提供的标识符，该重试响应标识互连上正在进行的第二事务。控制单元被配置为至少在检测到标识符的第二次传输之前禁止第一事务的重新发起。在另一个实施例中，控制单元被配置为在第一事务的响应阶段响应第一事务的窥探命中在存储在第二事务在互连上的第二事务的缓冲器中的第一请求时断言重试响应。控制单元还被配置为提供具有重试响应的第二事务的标识符。

10. 发明授权

US08086915B2 Memory controller with loopback test interface 有权
标题翻译：带环回测试接口的内存控制器
公开(公告)号：US08086915B2
公开(公告)日：2011-12-27
申请号：US12909073
申请日：2010-10-21
申请人： Luka Bodrozic , Sukalpa Biswas , Hao Chen , Sridhar P. Subramanian , James B. Keller
发明人： Luka Bodrozic , Sukalpa Biswas , Hao Chen , Sridhar P. Subramanian , James B. Keller
IPC分类号： G01R31/28 , G11C29/00 , G06F11/00
CPC分类号： G01R31/31716
摘要： In one embodiment, an apparatus comprises an interconnect; at least one processor coupled to the interconnect; and at least one memory controller coupled to the interconnect. The memory controller is programmable by the processor into a loopback test mode of operation and, in the loopback test mode, the memory controller is configured to receive a first write operation from the processor over the interconnect. The memory controller is configured to route write data from the first write operation through a plurality of drivers and receivers connected to a plurality of data pins that are capable of connection to one or more memory modules. The memory controller is further configured to return the write data as read data on the interconnect for a first read operation received from the processor on the interconnect.
摘要翻译：在一个实施例中，一种装置包括互连; 耦合到所述互连的至少一个处理器; 以及耦合到所述互连的至少一个存储器控制器。存储器控制器可由处理器编程为环回测试操作模式，并且在环回测试模式中，存储器控制器被配置为通过互连从处理器接收第一写入操作。存储器控制器被配置为将来自第一写入操作的写入数据路由到连接到能够连接到一个或多个存储器模块的多个数据引脚的多个驱动器和接收器。所述存储器控制器还被配置为将所述写入数据作为所述互连上的读取数据返回，用于从所述互连处从所述处理器接收的第一读取操作。

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