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1. 发明授权

US08402248B2 Explicitly regioned memory organization in a network element 失效
标题翻译：在网络元素中明确区分的内存组织
公开(公告)号：US08402248B2
公开(公告)日：2013-03-19
申请号：US12983130
申请日：2010-12-31
申请人： Stephan Meier , Robert Hathaway , Evan Gewirtz , Brian Alleyne , Edward Ho
发明人： Stephan Meier , Robert Hathaway , Evan Gewirtz , Brian Alleyne , Edward Ho
IPC分类号： G06F12/10
CPC分类号： G06F12/1009 , G06F2213/0038 , Y02D10/13
摘要： A network element that includes multiple memory types and memory sizes translates a logical memory address into a physical memory address. A memory access request is received for a data structure with a logical memory address that includes a region identifier that identifies a region that is mapped to one or more memories and is associated with a set of one or more region attributes whose values are based on processing requirements provided by a software programmer and the available memories of the network element. The network element accesses the region mapping table entry corresponding to the region identifier and, using the region attributes that are associated with the region, determines an access target for the request, determines a physical memory address offset within the access target, and generates a physical memory address. The access target includes a target class of memory, an instance within the class of memory, and a particular physical address space of the instance within the class of memory. The physical memory address includes a network routing information portion that includes information to route the physical memory address to the target instance, and includes an address payload portion that includes information to identify the physical address space identified by the subtarget and the physical memory address offset.
摘要翻译：包含多种存储器类型和存储器大小的网络元件将逻辑存储器地址转换为物理存储器地址。接收到具有逻辑存储器地址的数据结构的存储器访问请求，逻辑存储器地址包括标识映射到一个或多个存储器的区域的区域标识符，并且与其值基于处理的一个或多个区域属性的集合相关联由软件程序员提供的要求和网元的可用存储器。网元访问对应于区域标识符的区域映射表条目，并且使用与该区域相关联的区域属性来确定该请求的访问目标，确定访问目标内的物理内存地址偏移量，并且生成物理内存地址。访问目标包括目标类别的存储器，存储器类内的实例以及存储器类内的实例的特定物理地址空间。物理存储器地址包括网络路由信息部分，其包括用于将物理存储器地址路由到目标实例的信息，并且包括地址有效载荷部分，其包括用于识别由子目标识别的物理地址空间的信息和物理存储器地址偏移。

2. 发明申请

US20110276784A1 HIERARCHICAL MULTITHREADED PROCESSING 审中-公开
标题翻译：分层多元处理
公开(公告)号：US20110276784A1
公开(公告)日：2011-11-10
申请号：US12777087
申请日：2010-05-10
申请人： Evan Gewirtz , Robert Hathaway , Stephan Meier , Edward Ho
发明人： Evan Gewirtz , Robert Hathaway , Stephan Meier , Edward Ho
IPC分类号： G06F9/312 , G06F9/30
CPC分类号： G06F9/3851 , G06F9/3802
摘要： In one embodiment, a current candidate thread is selected from each of multiple first groups of threads using a low granularity selection scheme, where each of the first groups includes multiple threads and first groups are mutually exclusive. A second group of threads is formed comprising the current candidate thread selected from each of the first groups of threads. A current winning thread is selected from the second group of threads using a high granularity selection scheme. An instruction is fetched from a memory based on a fetch address for a next instruction of the current winning thread. The instruction is then dispatched to one of the execution units for execution, whereby execution stalls of the execution units are reduced by fetching instructions based on the low granularity and high granularity selection schemes.
摘要翻译：在一个实施例中，使用低粒度选择方案从多个第一组线程中选择当前候选线程，其中每个第一组包括多个线程，并且第一组是互斥的。形成第二组线程，包括从第一组线程中选择的当前候选线程。使用高粒度选择方案从第二组线程中选择当前获胜线程。基于当前获胜线程的下一条指令的获取地址从存储器中取出指令。然后将指令分派到一个执行单元进行执行，由此通过基于低粒度和高粒度选择方案获取指令来减少执行单元的执行停顿。

3. 发明授权

US08051227B1 Programmable queue structures for multiprocessors 有权
标题翻译：多处理器的可编程队列结构
公开(公告)号：US08051227B1
公开(公告)日：2011-11-01
申请号：US12777084
申请日：2010-05-10
申请人： Evan Gewirtz , Robert Hathaway , Stephan Meier
发明人： Evan Gewirtz , Robert Hathaway , Stephan Meier
IPC分类号： G06F3/00 , G06F13/00
CPC分类号： G06F9/544 , G06F9/52
摘要： A command is received from a first agent via a first predetermined memory-mapped register, the first agent being one of multiple agents representing software processes, each being executed by one of processor cores of a network processor in a network element. A first queue associated with the command is identified based on the first predetermined memory-mapped register. A pointer is atomically read from a first hardware-based queue state register associated with the first queue. Data is atomically accessed at a memory location of the memory based on the pointer. The pointer stored in the first hardware-based queue state register is atomically updated, including incrementing the pointer of the first hardware-based queue state register, reading a queue size of the queue from a first hardware-based configuration register associated with the first queue, and wrapping around the pointer if the pointer reaches an end of the first queue based on the queue size.
摘要翻译：经由第一预定存储器映射寄存器从第一代理接收到命令，第一代理是表示软件进程的多个代理之一，每个由代理网络元件中的网络处理器的处理器核心之一执行。基于第一预定存储器映射寄存器来识别与命令相关联的第一队列。从与第一队列相关联的第一基于硬件的队列状态寄存器中原子地读取指针。基于指针，数据在存储器的存储器位置被原子访问。存储在第一基于硬件的队列状态寄存器中的指针被原子地更新，包括增加第一基于硬件的队列状态寄存器的指针，从与第一队列相关联的第一基于硬件的配置寄存器读取队列的队列大小并且如果指针基于队列大小到达第一队列的末尾，则环绕指针。

4. 发明授权

US07305492B2 Content service aggregation system 有权
标题翻译：内容服务聚合系统
公开(公告)号：US07305492B2
公开(公告)日：2007-12-04
申请号：US10191742
申请日：2002-07-08
申请人： Mark Bryers , Elango Ganesan , Frederick Gruner , David Hass , Robert Hathaway , Ramesh Panwar , Ricardo Ramirez , Abbas Rashid , Mark Vilas , Nazar Zaidi , Yen Lee , Chau Anh Ngoc Nguyen , John Phillips , Yuhong Andy Zhou , Gregory G. Spurrier , Sankar Ramanoorthi , Michael Freed
发明人： Mark Bryers , Elango Ganesan , Frederick Gruner , David Hass , Robert Hathaway , Ramesh Panwar , Ricardo Ramirez , Abbas Rashid , Mark Vilas , Nazar Zaidi , Yen Lee , Chau Anh Ngoc Nguyen , John Phillips , Yuhong Andy Zhou , Gregory G. Spurrier , Sankar Ramanoorthi , Michael Freed
IPC分类号： G06F15/16
CPC分类号： H04L47/125 , H04L29/06 , H04L63/0485
摘要： A network content service apparatus includes a set of compute elements adapted to perform a set of network services; and a switching fabric coupling compute elements in said set of compute elements. The set of network services includes firewall protection, Network Address Translation, Internet Protocol forwarding, bandwidth management, Secure Sockets Layer operations, Web caching, Web switching, and virtual private networking. Code operable on the compute elements enables the network services, and the compute elements are provided on blades which further include at least one input/output port.
摘要翻译：网络内容服务设备包括适于执行一组网络服务的一组计算元件; 以及耦合所述一组计算元件中的计算元件的交换结构。该组网络服务包括防火墙保护，网络地址转换，互联网协议转发，带宽管理，安全套接字层操作，Web缓存，Web交换和虚拟专用网络。在计算元件上可操作的代码实现了网络服务，并且在还包括至少一个输入/输出端口的刀片上提供计算元件。

5. 发明申请

US20070254530A1 Plug assembly including integral printed circuit board 有权
标题翻译：插头组件包括集成印刷电路板
公开(公告)号：US20070254530A1
公开(公告)日：2007-11-01
申请号：US11416367
申请日：2006-05-01
申请人： Mark Martich , Robert Hathaway
发明人： Mark Martich , Robert Hathaway
IPC分类号： H01R24/00
CPC分类号： H01R13/6658 , H01R13/73 , H01R24/64 , Y10S439/941
摘要： An electrical plug is defined by a plug housing and an upper portion of a printed circuit board. The plug housing defines a region within which the upper portion of the printed circuit board is adapted to be positioned. Stepped side walls may be provided to facilitate sliding introduction and support of the upper portion of the printed circuit board. A locking structure, e.g., a deflectable locking tooth, is associated with the plug housing for engaging a locking aperture on the upper portion of the printed circuit board. A plurality of exposed contacts are provided on the upper portion of the printed circuit board that align with channels formed in the plug housing. The exposed contacts communicate with traces on the printed circuit board and are available for electrical communication with an associated jack. The electrical plug may be associated with an access point, including an access point that includes a plurality of printed circuit boards, only one of which extends into the plug housing to define an electrical plug as described above.
摘要翻译：电插头由插头壳体和印刷电路板的上部限定。插头壳体限定了其中印刷电路板的上部适于定位的区域。可以设置步进侧壁以便于印刷电路板的上部的滑动引入和支撑。诸如可偏转的锁定齿的锁定结构与插头壳体相关联，用于接合印刷电路板的上部上的锁定孔。多个暴露的触点设置在印刷电路板的与形成在插头壳体中的通道对准的上部。暴露的触点与印刷电路板上的迹线通信，并且可用于与相关插孔的电气通信。电插头可以与接入点相关联，包括包括多个印刷电路板的接入点，其中仅一个接入点延伸到插头壳体中以限定如上所述的电插头。

6. 发明申请

US20060246784A1 Electrically isolated shielded connector system 审中-公开
标题翻译：电隔离屏蔽连接器系统
公开(公告)号：US20060246784A1
公开(公告)日：2006-11-02
申请号：US11119116
申请日：2005-04-29
申请人： Robert Aekins , Robert Hathaway
发明人： Robert Aekins , Robert Hathaway
IPC分类号： H01R24/00
CPC分类号： H01R13/518 , H01R4/2433 , H01R13/506 , H01R13/5213 , H01R13/6461 , H01R13/6586 , H01R13/659 , H01R13/6599 , H01R13/6658 , H01R13/7193 , H01R13/748 , H01R24/64 , H05K1/0228
摘要： The present disclosure is related to a multiport adapter for a telecommunication connector system that is designed to reduce EMI from outside sources, as well as, between adjacent ports by electrical isolation design. The reduction of EMI is done by non-conventional methods of connecting hardware shielding techniques. The shield design surrounds all the internal pairs within the plug housing to reduce the transmitted signals EM radiation during transmission and it does not make contact with the modular connector plug, horizontal cable or the plastic support adapter housing. By isolating each component in the interface system, the coupled radiated noise from each port to port shield is individually controlled.
摘要翻译：本公开涉及用于电信连接器系统的多端口适配器，其被设计为通过电隔离设计来减少来自外部源以及相邻端口之间的EMI。 EMI的降低通过连接硬件屏蔽技术的非常规方法来完成。屏蔽设计包围插头外壳内的所有内部对，以减少传输过程中传输的信号EM辐射，并且不会与模块化连接器插头，水平电缆或塑料支架适配器外壳接触。通过隔离接口系统中的每个组件，从每个端口到端口屏蔽层的耦合辐射噪声被单独控制。

7. 发明申请

US20060144609A1 Discrete access point mounting system 审中-公开
标题翻译：离散式接入点安装系统
公开(公告)号：US20060144609A1
公开(公告)日：2006-07-06
申请号：US11321296
申请日：2005-12-27
申请人： Robert Hathaway
发明人： Robert Hathaway
IPC分类号： H01H13/04
CPC分类号： H02G3/123
摘要： A discrete access point mounting system is provided that is configured to be mounted to a wall or other like mounting surface. The discrete access point mounting system provides for the consolidation of one or more receptacle connections behind a single mounting plate to enhance the functionality and aesthetic appearance of access points. Moreover, the system enhances the protection of cable from a connector jack to one or more receptacles from damage and contamination. The discrete access point mounting system includes a surface mounting plate suitable for being mounted or connected to a wall or other like mounting surface. The surface mounting plate defines a frame having at least one receptacle opening suitable for mounting at least one connector receptacle and further including at least one wall mounting feature. The wall mounting feature supports the weight of the discrete access point mounting system, the weight of an access point, or a combination thereof. A jack mounting plate is operatively connected to the surface mounting plate and defines a frame having a jack opening suitable for mounting at least one connector jack. The area between the surface mounting plate and the jack mounting plate defines a cord storage area suitable for storing a length of cord connecting a connector jack and at least one connector receptacle.
摘要翻译：提供了一种离散的接入点安装系统，其被配置为安装到壁或其它相似的安装表面。离散接入点安装系统提供了在单个安装板后面的一个或多个插座连接的合并，以增强接入点的功能和美学外观。此外，该系统增强了电缆从连接器插头到一个或多个插座的保护，免受损坏和污染。离散接入点安装系统包括适于安装或连接到壁或其它类似安装表面的表面安装板。表面安装板限定了具有适于安装至少一个连接器插座的至少一个插座开口的框架，并且还包括至少一个壁挂安装特征。墙壁安装特征支持离散接入点安装系统的重量，接入点的重量或其组合。插座安装板可操作地连接到表面安装板并且限定具有适于安装至少一个连接器插孔的插座开口的框架。表面安装板和插座安装板之间的区域限定了适合于存储连接连接器插孔和至少一个连接器插座的一段电缆的绳索存储区域。

8. 发明授权

US06901482B2 Managing ownership of a full cache line using a store-create operation 有权
标题翻译：使用存储创建操作管理完整高速缓存行的所有权
公开(公告)号：US06901482B2
公开(公告)日：2005-05-31
申请号：US10106925
申请日：2002-03-25
申请人： Fred Gruner , David Hass , Robert Hathaway , Ramesh Panwar , Ricardo Ramirez , Nazar Zaidi
发明人： Fred Gruner , David Hass , Robert Hathaway , Ramesh Panwar , Ricardo Ramirez , Nazar Zaidi
IPC分类号： G06F12/00 , G06F12/08 , H04L12/56 , G06F13/00
CPC分类号： H04L47/10 , G06F12/0813 , G06F12/0831 , G06F12/084 , H04L47/12 , H04L47/20 , H04L47/2441 , H04L47/765 , H04L47/805 , H04L47/822
摘要： A system includes a plurality of processing clusters and a snoop controller. A first processing cluster in the plurality of processing clusters includes a first tier cache memory coupled to a second tier cache memory. The system employs a store-create operation to obtain sole ownership of a full cache line memory location for the first processing cluster, without retrieving the memory location from other processing clusters. The system issues the store-create operation for the memory location to the first tier cache. The first tier cache forwards a memory request including the store-create operation command to the second tier cache. The second tier cache determines whether the second tier cache has sole ownership of the memory location. If the second tier cache does not have sole ownership of the memory location, ownership of the memory location is relinquished by the other processing clusters with any ownership of the memory location.
摘要翻译：系统包括多个处理群集和窥探控制器。多个处理群集中的第一处理群集包括耦合到第二层高速缓冲存储器的第一层高速缓冲存储器。系统采用存储创建操作来获得用于第一处理集群的完整高速缓存行存储器位置的唯一所有权，而不从其他处理集群检索存储器位置。系统会将内存位置的存储创建操作发布到第一层缓存。第一层缓存将包含store-create操作命令的内存请求转发到第二层缓存。第二层缓存确定第二层缓存是否具有对存储器位置的唯一所有权。如果第二层缓存不具有对存储器位置的唯一所有权，则存储器位置的所有权由具有存储器位置的任何所有权的其他处理集群放弃。

9. 发明授权

US06839808B2 Processing cluster having multiple compute engines and shared tier one caches 有权
标题翻译：具有多个计算引擎和共享一级缓存的处理集群
公开(公告)号：US06839808B2
公开(公告)日：2005-01-04
申请号：US09900481
申请日：2001-07-06
申请人： Fred Gruner , David Hass , Robert Hathaway , Ramesh Penwar , Ricardo Ramirez , Nazar Zaidi
发明人： Fred Gruner , David Hass , Robert Hathaway , Ramesh Penwar , Ricardo Ramirez , Nazar Zaidi
IPC分类号： G06F12/00 , G06F12/08 , H04L12/56
CPC分类号： H04L47/10 , G06F12/0813 , G06F12/0831 , G06F12/084 , H04L47/12 , H04L47/20 , H04L47/2441 , H04L47/765 , H04L47/805 , H04L47/822
摘要： A multi-processor includes multiple processing clusters for performing assigned applications. Each cluster includes a set of compute engines, with each compute engine coupled to a set of cache memory. A compute engine includes a central processing unit and a coprocessor with a set of application engines. The central processing unit and coprocessor are coupled to the compute engine's associated cache memory. The sets of cache memory within a cluster are also coupled to one another.

10. 发明授权

US08914581B2 Method and apparatus for accessing cache memory 有权
标题翻译：用于访问高速缓冲存储器的方法和装置
公开(公告)号：US08914581B2
公开(公告)日：2014-12-16
申请号：US12784276
申请日：2010-05-20
申请人： Robert Hathaway , Evan Gewirtz
发明人： Robert Hathaway , Evan Gewirtz
IPC分类号： G06F12/12 , G06F12/08
CPC分类号： G06F12/0888 , G06F12/12
摘要： A request for reading data from a memory location of a main memory is received, the memory location being identified by a physical memory address. In response to the request, a cache memory is accessed based on the physical memory address to determine whether the cache memory contains the data being requested. The data associated with the request is returned from the cache memory without accessing the memory location if there is a cache hit. The data associated is returned from the main memory if there is a cache miss. In response to the cache miss, it is determined whether there have been a number of accesses within a predetermined period of time. A cache entry is allocated from the cache memory to cache the data if there have been a predetermined number of accesses within the predetermined period of time.
摘要翻译：接收到从主存储器的存储器位置读取数据的请求，存储器位置由物理存储器地址标识。响应于该请求，基于物理存储器地址访问高速缓存存储器，以确定高速缓冲存储器是否包含正被请求的数据。如果存在高速缓存命中，与请求相关联的数据从高速缓冲存储器返回，而不访问存储器位置。如果存在高速缓存未命中，则从主存储器返回相关的数据。响应于高速缓存未命中，确定在预定时间段内是否存在多个访问。如果在预定时间段内已经存在预定数量的访问，则从高速缓冲存储器分配高速缓存条目以缓存数据。

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