专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

WO2010077885A3 EXTENDING CACHE COHERENCY PROTOCOLS TO SUPPORT LOCALLY BUFFERED DATA 审中-公开
标题翻译：扩展缓存协议来支持本地缓存数据
公开(公告)号：WO2010077885A3
公开(公告)日：2010-10-07
申请号：PCT/US2009068121
申请日：2009-12-15
申请人： INTEL CORP , SHEAFFER GAD , RAIKIN SHLOMO , BASSIN VADIM , COHEN EHUD , MARGULIS OLEG , SADE RAANAN
发明人： SHEAFFER GAD , RAIKIN SHLOMO , BASSIN VADIM , COHEN EHUD , MARGULIS OLEG , SADE RAANAN
IPC分类号： G06F9/06 , G06F5/00 , G06F9/46 , G06F12/00
CPC分类号： G06F9/3834 , G06F9/467 , G06F12/0831 , G06F12/084
摘要： A method and apparatus for extending cache coherency to hold buffered data to support transactional execution is herein described. A transactional store operation referencing an address associated with a data item is performed in a buffered manner. Here, the coherency state associated with cache lines to hold the data item are transitioned to a buffered state. In response to local requests for the buffered data item, the data item is provided to ensure internal transactional sequential ordering. However, in response to external access requests, a miss response is provided to ensure the transactionally updated data item is not made globally visible until commit. Upon commit, the buffered lines are transitioned to a modified state to make the data item globally visible.
摘要翻译：这里描述了用于扩展高速缓存一致性以保存缓冲数据以支持事务执行的方法和装置。以缓冲的方式执行引用与数据项相关联的地址的事务存储操作。这里，与保存数据项的高速缓存行相关联的一致性状态被转换到缓冲状态。响应缓冲数据项的本地请求，提供数据项以确保内部事务顺序排序。然而，响应于外部访问请求，提供了错误响应以确保事务更新的数据项在提交之前不会被全局可见。一旦提交，缓存的行将转换到修改状态，使数据项全局可见。

2. 发明申请

WO2010077842A2 METAPHYSICAL ADDRESS SPACE FOR HOLDING LOSSY METADATA IN HARDWARE 审中-公开
标题翻译：用于在硬件中保存损失元数据的地形空间
公开(公告)号：WO2010077842A2
公开(公告)日：2010-07-08
申请号：PCT/US2009067983
申请日：2009-12-15
申请人： INTEL CORP , SHAEFFER GAD , RAIKIN SHLOMO , BASSIN VADIM , SADE RAANAN , COHEN EHUD , MARGULIS OLEG
发明人： SHAEFFER GAD , RAIKIN SHLOMO , BASSIN VADIM , SADE RAANAN , COHEN EHUD , MARGULIS OLEG
IPC分类号： G06F9/06 , G06F9/46 , G06F12/00
CPC分类号： G06F12/0615 , G06F9/467 , G06F12/0842 , G06F12/1027
摘要： A method and apparatus for metaphysical address space for holding lossy metadata is herein described. An explicit or implicit metadata access operation referencing data address of a data item is encountered. Hardware modifies the data address to a metadata address including a metaphysical extension. The metaphysical extension overlays one or more metaphysical address space(s) on the data address space. A portion of the metadata address including the metaphysical extension is utilized to search a tag array of the cache memory holding the data item. As a result, metadata access operations only hit metadata entries of the cache based on the metadata address extension. However, as the metadata is held within the cache, the metadata potentially competes with data for space within the cache.
摘要翻译：这里描述用于保存有损元数据的形而上学地址空间的方法和装置。遇到引用数据项的数据地址的显式或隐式元数据访问操作。硬件将数据地址修改为包括形而上学扩展的元数据地址。形而上学扩展覆盖了数据地址空间上的一个或多个形而上学地址空间。使用包括形而上学扩展的元数据地址的一部分来搜索保存数据项的高速缓冲存储器的标签阵列。因此，元数据访问操作仅基于元数据地址扩展名来命中高速缓存的元数据条目。然而，随着元数据被保存在高速缓存中，元数据可能与高速缓存中的空间的数据竞争。

3. 发明申请

WO2013101213A1 METHOD AND APPARATUS FOR CUTTING SENIOR STORE LATENCY USING STORE PREFETCHING 审中-公开
标题翻译：使用商店预购切割高级商店的方法和装置
公开(公告)号：WO2013101213A1
公开(公告)日：2013-07-04
申请号：PCT/US2011/068208
申请日：2011-12-30
申请人： INTEL CORPORATION , SHWARTSMAN, Stanislav , OZGUL, Melih , HILY, Sebastien , RAIKIN, Shlomo , SADE, Raanan , SHALEV, Ron
发明人： SHWARTSMAN, Stanislav , OZGUL, Melih , HILY, Sebastien , RAIKIN, Shlomo , SADE, Raanan , SHALEV, Ron
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/3814 , G06F9/383 , G06F9/3834 , G06F9/3861 , G06F12/0808 , G06F12/0862 , G06F2212/6028 , G06F2212/62
摘要： In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for cutting senior store latency using store prefetching. For example, in one embodiment, such means may include an integrated circuit or an out of order processor means that processes out of order instructions and enforces in-order requirements for a cache. Such an integrated circuit or out of order processor means further includes means for receiving a store instruction; means for performing address generation and translation for the store instruction to calculate a physical address of the memory to be accessed by the store instruction; and means for executing a pre-fetch for a cache line based on the store instruction and the calculated physical address before the store instruction retires.
摘要翻译：根据本文公开的实施例，提供了使用商店预取来切割高级商店延迟的方法，系统，机制，技术和装置。例如，在一个实施例中，这样的装置可以包括集成电路或乱序处理器装置，其处理不一致的指令并对高速缓存执行按顺序的要求。这样的集成电路或不按顺序的处理器装置还包括用于接收存储指令的装置; 用于执行所述存储指令的地址生成和转换以计算由所述存储指令访问的存储器的物理地址的装置; 以及用于在存储指令退出之前基于所述存储指令和所计算的物理地址来执行用于高速缓存行的预取的装置。

4. 发明申请

WO2012040425A3 REGULATING ATOMIC MEMORY OPERATIONS TO PREVENT DENIAL OF SERVICE ATTACK 审中-公开
公开(公告)号：WO2012040425A3
公开(公告)日：2012-03-29
申请号：PCT/US2011/052696
申请日：2011-09-22
申请人： INTEL CORPORATION , BAIR, Michael, S. , ONG, Leslie, A. , TUCKNOTT, Michael, D. , BURNS, David, W. , RAGHUVANSHI, Pankaj , YANOVER, Igor , CHAPPELL, Robert, S. , RAIKIN, Shlomo , MATH, Prakash , SADE, Raanan
发明人： BAIR, Michael, S. , ONG, Leslie, A. , TUCKNOTT, Michael, D. , BURNS, David, W. , RAGHUVANSHI, Pankaj , YANOVER, Igor , CHAPPELL, Robert, S. , RAIKIN, Shlomo , MATH, Prakash , SADE, Raanan
IPC分类号： G06F15/76 , G06F13/14 , G06F12/00
摘要： In one embodiment, the present invention includes a method for identifying a termination sequence for an atomic memory operation executed by a first thread, associating a timer with the first thread, and preventing the first thread from execution of a memory cluster operation after completion of the atomic memory operation until a prevention window has passed. This method may be executed by regulation logic associated with a memory execution unit of a processor, in some embodiments. Other embodiments are described and claimed.

5. 发明申请

WO2010077885A2 EXTENDING CACHE COHERENCY PROTOCOLS TO SUPPORT LOCALLY BUFFERED DATA 审中-公开
标题翻译：扩展高速缓存一致性协议以支持本地缓冲数据
公开(公告)号：WO2010077885A2
公开(公告)日：2010-07-08
申请号：PCT/US2009/068121
申请日：2009-12-15
申请人： INTEL CORPORATION , SHEAFFER, Gad , RAIKIN, Shlomo , BASSIN, Vadim , COHEN, Ehud , MARGULIS, Oleg , SADE, Raanan
发明人： SHEAFFER, Gad , RAIKIN, Shlomo , BASSIN, Vadim , COHEN, Ehud , MARGULIS, Oleg , SADE, Raanan
IPC分类号： G06F9/06 , G06F9/46 , G06F12/00 , G06F5/00
CPC分类号： G06F9/3834 , G06F9/467 , G06F12/0831 , G06F12/084
摘要： A method and apparatus for extending cache coherency to hold buffered data to support transactional execution is herein described. A transactional store operation referencing an address associated with a data item is performed in a buffered manner. Here, the coherency state associated with cache lines to hold the data item are transitioned to a buffered state. In response to local requests for the buffered data item, the data item is provided to ensure internal transactional sequential ordering. However, in response to external access requests, a miss response is provided to ensure the transactionally updated data item is not made globally visible until commit. Upon commit, the buffered lines are transitioned to a modified state to make the data item globally visible.
摘要翻译：本文描述了用于扩展高速缓存一致性以保持缓冲数据以支持事务执行的方法和设备。引用与数据项相关联的地址的事务存储操作以缓存的方式执行。这里，与用于保存数据项的高速缓存行相关联的一致性状态被转换到缓冲状态。响应于缓存数据项的本地请求，提供数据项以确保内部事务顺序排序。但是，为了响应外部访问请求，提供未命中响应以确保事务更新的数据项在提交之前不会全局可见。提交后，缓冲行将转换为修改状态，以使数据项全局可见。

6. 发明申请

WO2010077850A3 READ AND WRITE MONITORING ATTRIBUTES IN TRANSACTIONAL MEMORY (TM) SYSTEMS 审中-公开
公开(公告)号：WO2010077850A3
公开(公告)日：2010-07-08
申请号：PCT/US2009/068004
申请日：2009-12-15
申请人： INTEL CORPORATION , SHAEFFER, Gad , RAIKIN, Shlomo , BASSIN, Vadim , SADE, Raanan , COHEN, Ehud , MARGULIS, Oleg
发明人： SHAEFFER, Gad , RAIKIN, Shlomo , BASSIN, Vadim , SADE, Raanan , COHEN, Ehud , MARGULIS, Oleg
IPC分类号： G06F12/00 , G06F11/30 , G06F13/16 , G06F12/08
摘要： A method and apparatus for monitoring memory accesses in hardware to support transactional execution is herein described. Attributes are monitor accesses to data items without regard for detection at physical storage structure granularity, but rather ensuring monitoring at least at data items granularity. As an example, attributes are added to state bits of a cache to enable new cache coherency states. Upon a monitored memory access to a data item, which may be selectively determined, coherency states associated with the data item are updated to a monitored state. As a result, invalidating requests to the data item are detected through combination of the request type and the monitored coherency state of the data item.

7. 发明申请

WO2010077842A3 METAPHYSICAL ADDRESS SPACE FOR HOLDING LOSSY METADATA IN HARDWARE 审中-公开
公开(公告)号：WO2010077842A3
公开(公告)日：2010-07-08
申请号：PCT/US2009/067983
申请日：2009-12-15
申请人： INTEL CORPORATION , SHAEFFER, Gad , RAIKIN, Shlomo , BASSIN, Vadim , SADE, Raanan , COHEN, Ehud , MARGULIS, Oleg
发明人： SHAEFFER, Gad , RAIKIN, Shlomo , BASSIN, Vadim , SADE, Raanan , COHEN, Ehud , MARGULIS, Oleg
IPC分类号： G06F9/06 , G06F9/46 , G06F12/00
摘要： A method and apparatus for metaphysical address space for holding lossy metadata is herein described. An explicit or implicit metadata access operation referencing data address of a data item is encountered. Hardware modifies the data address to a metadata address including a metaphysical extension. The metaphysical extension overlays one or more metaphysical address space(s) on the data address space. A portion of the metadata address including the metaphysical extension is utilized to search a tag array of the cache memory holding the data item. As a result, metadata access operations only hit metadata entries of the cache based on the metadata address extension. However, as the metadata is held within the cache, the metadata potentially competes with data for space within the cache.

8. 发明申请

WO2013095475A1 APPARATUS AND METHOD FOR MEMORY-HIERARCHY AWARE PRODUCER-CONSUMER INSTRUCTION 审中-公开
标题翻译：用于记忆级别生产者消费者指令的装置和方法
公开(公告)号：WO2013095475A1
公开(公告)日：2013-06-27
申请号：PCT/US2011/066674
申请日：2011-12-21
申请人： INTEL CORPORATION , RAIKIN, Shlomo , SADE, Raanan , VALENTINE, Robert , MANDELBLAT, Julius Yuli , SHALEV, Ron , NOVAKOVSKY, Larisa
发明人： RAIKIN, Shlomo , SADE, Raanan , VALENTINE, Robert , MANDELBLAT, Julius Yuli , SHALEV, Ron , NOVAKOVSKY, Larisa
IPC分类号： G06F13/14 , G06F13/38 , G06F9/30
CPC分类号： G06F12/0811 , G06F9/30043 , G06F9/30047 , G06F9/30087 , G06F9/3881 , G06F12/0866 , G06F13/1673 , G06F13/38 , G06T1/20 , G06T1/60 , G09G5/006
摘要： An apparatus and method are described for efficiently transferring data from a core of a central processing unit (CPU) to a graphics processing unit (GPU). For example, one embodiment of a method comprises: writing data to a buffer within the core of the CPU until a designated amount of data has been written; upon detecting that the designated amount of data has been written, responsively generating an eviction cycle, the eviction cycle causing the data to be transferred from the buffer to a cache accessible by both the core and the GPU; setting an indication to indicate to the GPU that data is available in the cache; and upon the GPU detecting the indication, providing the data to the GPU from the cache upon receipt of a read signal from the GPU.
摘要翻译：描述了一种有效地将数据从中央处理单元（CPU）的核心传输到图形处理单元（GPU）的装置和方法。例如，一种方法的一个实施例包括：将数据写入CPU的核心内的缓冲器，直到指定的数据量被写入为止; 在检测到指定量的数据已被写入时，响应地产生驱逐周期，驱逐循环使数据从缓冲器传送到可由核心和GPU访问的高速缓存; 设置指示以向GPU指示数据在高速缓存中可用; 并且在GPU检测到指示时，在从GPU接收到读取信号时，从高速缓存提供数据给GPU。

9. 发明申请

WO2012040425A2 REGULATING ATOMIC MEMORY OPERATIONS TO PREVENT DENIAL OF SERVICE ATTACK 审中-公开
标题翻译：规范原子内存操作以防止服务攻击拒绝
公开(公告)号：WO2012040425A2
公开(公告)日：2012-03-29
申请号：PCT/US2011052696
申请日：2011-09-22
申请人： INTEL CORP , BAIR MICHAEL S , ONG LESLIE A , TUCKNOTT MICHAEL D , BURNS DAVID W , RAGHUVANSHI PANKAJ , YANOVER IGOR , CHAPPELL ROBERT S , RAIKIN SHLOMO , MATH PRAKASH , SADE RAANAN
发明人： BAIR MICHAEL S , ONG LESLIE A , TUCKNOTT MICHAEL D , BURNS DAVID W , RAGHUVANSHI PANKAJ , YANOVER IGOR , CHAPPELL ROBERT S , RAIKIN SHLOMO , MATH PRAKASH , SADE RAANAN
IPC分类号： G06F15/76 , G06F12/00 , G06F13/14
CPC分类号： G06F9/526
摘要： In one embodiment, the present invention includes a method for identifying a termination sequence for an atomic memory operation executed by a first thread, associating a timer with the first thread, and preventing the first thread from execution of a memory cluster operation after completion of the atomic memory operation until a prevention window has passed. This method may be executed by regulation logic associated with a memory execution unit of a processor, in some embodiments. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括一种用于识别由第一线程执行的原子存储器操作的终止序列的方法，将定时器与第一线程相关联，并且在完成第一线程之后阻止第一线程执行存储器群集操作原子内存操作，直到预防窗口过去。在一些实施例中，该方法可以由与处理器的存储器执行单元相关联的调节逻辑来执行。描述并要求保护其他实施例。

10. 发明申请

WO2013095640A1 METHODS AND APPARATUS FOR EFFICIENT COMMUNICATION BETWEEN CACHES IN HIERARCHICAL CACHING DESIGN 审中-公开
标题翻译：用于分层缓存设计中的高速缓存之间的有效通信的方法和设备
公开(公告)号：WO2013095640A1
公开(公告)日：2013-06-27
申请号：PCT/US2011/067217
申请日：2011-12-23
申请人： INTEL CORPORATION , SHALEV, Ron , GILAD, Yiftach , RAIKIN, Shlomo , YANOVER, Igor , SHWARTSMAN, Stanislav , SADE, Raanan
发明人： SHALEV, Ron , GILAD, Yiftach , RAIKIN, Shlomo , YANOVER, Igor , SHWARTSMAN, Stanislav , SADE, Raanan
IPC分类号： G06F13/14 , G06F13/38 , G06F12/08
CPC分类号： G06F12/0811 , G06F12/08 , G06F12/0844 , G06F12/0897 , G06F13/14 , G06F13/38
摘要： In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for implementing efficient communication between caches in hierarchical caching design. For example, in one embodiment, such means may include an integrated circuit having a data bus; a lower level cache communicably interfaced with the data bus; a higher level cache communicably interfaced with the data bus; one or more data buffers and one or more dataless buffers. The data buffers in such an embodiment being communicably interfaced with the data bus, and each of the one or more data buffers having a buffer memory to buffer a full cache line, one or more control bits to indicate state of the respective data buffer, and an address associated with the full cache line. The dataless buffers in such an embodiment being incapable of storing a full cache line and having one or more control bits to indicate state of the respective dataless buffer and an address for an inter-cache transfer line associated with the respective dataless buffer. In such an embodiment, inter-cache transfer logic is to request the inter-cache transfer line from the higher level cache via the data bus and is to further write the inter-cache transfer line into the lower level cache from the data bus.
摘要翻译：根据本文公开的实施例，提供了用于在分级缓存设计中实现高速缓存之间的有效通信的方法，系统，机制，技术和装置。例如，在一个实施例中，这种装置可以包括具有数据总线的集成电路; 与数据总线可通信地接口的低级缓存; 与数据总线可通信地接口的更高级别的缓存; 一个或多个数据缓冲器和一个或多个无数据缓冲器。这种实施例中的数据缓冲器与数据总线可通信地接口，并且一个或多个数据缓冲器中的每一个具有缓冲存储器以缓冲全高速缓存线，一个或多个控制位以指示各个数据缓冲器的状态，以及与完整缓存行相关联的地址。在这种实施例中的无数据缓冲器不能存储完整的高速缓存行并且具有一个或多个控制位以指示相应无数据缓冲器的状态以及与相应无数据缓冲器相关联的高速缓存间传输线的地址。在这样的实施例中，高速缓存间传输逻辑是经由数据总线从高级缓存请求高速缓存间传输线，并且进一步将数据总线上的缓存间传输线写入低级缓存。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式