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1. 发明申请

WO2010057842A1 PREPARING A SURFACE OF A SAPPHIRE SUBSTRATE FOR FABRICATING HETEROSTRUCTURES 审中-公开
标题翻译：制备SAPPHIRE底物的表面以制备异体结构
公开(公告)号：WO2010057842A1
公开(公告)日：2010-05-27
申请号：PCT/EP2009/065202
申请日：2009-11-16
申请人： S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES , GAUDIN, Gweltaz , KENNARD, Mark , PICCIN, Matteo , RADU, Ionut , VAUFREDAZ, Alexandre
发明人： GAUDIN, Gweltaz , KENNARD, Mark , PICCIN, Matteo , RADU, Ionut , VAUFREDAZ, Alexandre
IPC分类号： H01L21/18 , H01L21/762
CPC分类号： H01L21/76256 , H01L21/187
摘要： The invention relates to a method of fabricating a heterostructure comprising at least a first substrate (120) made of sapphire and a second substrate (110) made of a material having a coefficient of thermal expansion that is different from that of the first substrate, the method including a step (S6) of molecular bonding the second substrate (110) on the first substrate (120) made of sapphire. In accordance with the invention, the method includes, prior to bonding the two substrates together, a step (S1) of stoving the first substrate (120) at a temperature that lies in the range 100°C to 500°C.
摘要翻译：本发明涉及一种制造异质结构的方法，该方法至少包括由蓝宝石制成的第一衬底（120）和由具有不同于第一衬底的热膨胀系数的材料制成的第二衬底（110）方法包括在由蓝宝石制成的第一衬底（120）上分层结合第二衬底（110）的步骤（S6）。根据本发明，该方法包括在将两个基板结合在一起之前，将步骤（S1）在位于100℃至500℃范围内的温度下烘烤第一基板（120）。

2. 发明申请

WO2011067276A1 HETEROSTRUCTURE FOR ELECTRONIC POWER COMPONENTS, OPTOELECTRONIC OR PHOTOVOLTAIC COMPONENTS 审中-公开
标题翻译：电子元件，光电或光伏组件的结构
公开(公告)号：WO2011067276A1
公开(公告)日：2011-06-09
申请号：PCT/EP2010/068614
申请日：2010-12-01
申请人： S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES , BETHOUX, Jean-Marc , LETERTRE, Fabrice , WERKHOVEN, Chris , RADU, Ionut , KONONCHUCK, Oleg
发明人： BETHOUX, Jean-Marc , LETERTRE, Fabrice , WERKHOVEN, Chris , RADU, Ionut , KONONCHUCK, Oleg
IPC分类号： H01L21/18 , H01L21/762 , H01L23/373 , H01L21/02
CPC分类号： H01L21/187 , H01L21/02389 , H01L21/02458 , H01L21/0254 , H01L21/02658 , H01L33/007 , H01L33/0079 , H01L2924/0002 , H01L2924/00
摘要： The invention relates to a heterostructure (1) for electronic power, optoelectronic or photovoltaic components, comprising: a support substrate (10) with an electrical resistivity less than 10 -3 ohm.cm and a thermal conductivity greater than 100 W.m -1 .K -1 , a bonding layer (2), a monocrystalline seed layer (3) in Al x ln y Ga (1-x-y) N, a crack-free monocrystalline active layer (4) of Al x ln y Ga (1-x-y) N presenting a thickness of between 3 and 100 micrometers, wherein: the specific contact resistance between the seed and the bonding layers is less than or equal to 0.1 ohm.cm 2 , the materials of the support substrate, the bonding layer and the seed layer are refractory above 750 °C, the lattice parameter difference between the seed and the active layers is less than 0.005 Å.
摘要翻译：本发明涉及一种用于电子功率，光电子或光伏组件的异质结构（1），其包括：电阻率小于10-3欧姆·厘米且热导率大于100Wm-1.K的支撑衬底（10） -1，AlxlnyGa（1-xy）N中的结合层（2），单晶种子层（3），AlxlnyGa（1-xy）N的无裂纹单晶有源层（4），其厚度介于3 和100微米，其中：种子和结合层之间的比接触电阻小于或等于0.1欧姆·厘米2，支撑基材，结合层和籽晶层的材料在750℃以上耐火，种子和活性层之间的晶格参数差小于0.005。

3. 发明申请

WO2009095380A8 METHOD FOR MANUFACTURING HETEROSTRUCTURES 审中-公开
标题翻译：制造异体结构的方法
公开(公告)号：WO2009095380A8
公开(公告)日：2009-11-05
申请号：PCT/EP2009050878
申请日：2009-01-27
申请人： SOITEC SILICON ON INSULATOR , RADU IONUT , KONONCHUK OLEG , BOURDELLE KONSTANTIN
发明人： RADU IONUT , KONONCHUK OLEG , BOURDELLE KONSTANTIN
IPC分类号： H01L21/20 , H01L21/762
CPC分类号： H01L21/76254 , H01L21/2007 , H01L21/76256
摘要： The invention relates to a method for manufacturing heterostructures for applications in the fields of electronics, optics or opto-electronics. This method is remarkable in that it consists of : - forming and/or depositing a silicon oxide Si?2 layer (3, 4) with a thickness of less than or equal to 25 nanometers on a donor substrate (1) and/or on a receiver substrate (2), - submitting this or these substrates (1, 2) to a treatment at a temperature comprised between 900°C and 1,200°C, under an atmosphere containing at least argon and/or hydrogen and no oxygen, in order to form in said silicon oxide layer (3, 4), trapping holes (30, 40), - bonding both substrates (1, 2), - carrying out annealing for reinforcing the bonding interface (5) at low temperature, said trapping holes (30, 40) being capable of retaining the gas species present at this interface, - transferring a portion (14) of the donor substrate (1), onto the receiver substrate (2).
摘要翻译：本发明涉及一种用于制造用于电子学，光学或光电子领域的异质结构的方法。该方法是显着的，其包括：在施主衬底（1）上和/或在其上形成和/或沉积厚度小于或等于25纳米的氧化硅Si 2层（3,4）接收器基板（2）， - 在至少包含氩和/或氢而不含氧的气氛下，将该基板或这些基板（1,2）在包含在900℃和1200℃之间的温度下进行处理在所述氧化硅层（3,4）中形成捕集孔（30,40）， - 结合两个基板（1,2）， - 在低温下执行用于加强所述接合界面（5）的退火，所述捕获孔（30,40）能够保留存在于该界面处的气体物质， - 将施主衬底（1）的一部分（14）转移到接收器基板（2）上。

4. 发明申请

WO2009095380A1 METHOD FOR MANUFACTURING HETEROSTRUCTURES 审中-公开
标题翻译：制造异体结构的方法
公开(公告)号：WO2009095380A1
公开(公告)日：2009-08-06
申请号：PCT/EP2009/050878
申请日：2009-01-27
申请人： S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES , RADU, Ionut , KONONCHUK, Oleg , BOURDELLE, Konstantin
发明人： RADU, Ionut , KONONCHUK, Oleg , BOURDELLE, Konstantin
IPC分类号： H01L21/20 , H01L21/762
CPC分类号： H01L21/76254 , H01L21/2007 , H01L21/76256
摘要： The invention relates to a method for manufacturing heterostructures for applications in the fields of electronics, optics or opto-electronics. This method is remarkable in that it consists of : - forming and/or depositing a silicon oxide Siθ2 layer (3, 4) with a thickness of less than or equal to 25 nanometers on a donor substrate (1) and/or on a receiver substrate (2), - submitting this or these substrates (1, 2) to a treatment at a temperature comprised between 9000C and 1,2000C, under an atmosphere containing at least argon and/or hydrogen and no oxygen, in order to form in said silicon oxide layer (3, 4), trapping holes (30, 40), - bonding both substrates (1, 2), - carrying out annealing for reinforcing the bonding interface (5) at low temperature, said trapping holes (30, 40) being capable of retaining the gas species present at this interface, - transferring a portion (14) of the donor substrate (1), onto the receiver substrate (2).
摘要翻译：本发明涉及一种用于制造用于电子学，光学或光电子领域的异质结构的方法。该方法是显着的，其包括：在施主衬底（1）上和/或在其上形成和/或沉积厚度小于或等于25纳米的氧化硅Si 2层（3,4）接收器基板（2），在含有至少氩气和/或氢气和不含氧气体的气氛下，将该基板或这些基板（1,2）置于950℃至1200℃的温度下进行处理，以便在所述氧化硅层（3,4）中形成捕集孔（30,40）， - 结合两个基板（1,2）， - 在低温下执行用于加强所述接合界面（5）的退火，所述捕集孔（ 30,40）能够保留存在于该界面处的气体种类， - 将施主衬底（1）的一部分（14）转移到接收衬底（2）上。

5. 发明申请

WO2009150503A1 METHOD FOR PREPARING HYDROPHOBIC SURFACES 审中-公开
标题翻译：制备疏水表面的方法
公开(公告)号：WO2009150503A1
公开(公告)日：2009-12-17
申请号：PCT/IB2009/005791
申请日：2009-05-28
申请人： S.O.I. TEC SILICON ON INSULATOR TECHNOLOGIES , PECLARD, Nicolas , RADOUANE, Khalid , GAUDIN, Gweltaz , RADU, Ionut , KERDILES, Sébastien
发明人： PECLARD, Nicolas , RADOUANE, Khalid , GAUDIN, Gweltaz , RADU, Ionut , KERDILES, Sébastien
IPC分类号： H01L21/306 , H01L21/762
CPC分类号： H01L21/02046 , H01L21/76254
摘要： The invention relates to a method for preparing hydrophobic surfaces which find their application in direct silicon bonding and strained material layer growth. The method comprises providing a substrate and subjecting the substrate to a mixed plasma treatment, wherein the mixed plasma comprises a reducing gas plasma, in particular H2, and an inert gas plasma, in particular Ar and/or He.
摘要翻译：本发明涉及一种用于制备疏水性表面的方法，其可用于直接硅键合和应变材料层生长。该方法包括提供衬底并对衬底进行混合等离子体处理，其中混合等离子体包括还原气体等离子体，特别是H2，以及惰性气体等离子体，特别是Ar和/或He。

6. 发明申请

WO2012131075A1 METHODS FOR BONDING SEMICONDUCTOR STRUCTURES INVOLVING ANNEALING PROCESSES, AND BONDED SEMICONDUCTOR STRUCTURES FORMED USING SUCH METHODS 审中-公开
标题翻译：用于结合涉及退火工艺的半导体结构的方法以及使用这种方法形成的结合的半导体结构
公开(公告)号：WO2012131075A1
公开(公告)日：2012-10-04
申请号：PCT/EP2012/055894
申请日：2012-03-30
申请人： SOITEC , COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES , SADAKA, Mariam , RADU, Ionut , LANDRU, Didier , DI CIOCCIO, Lea
发明人： SADAKA, Mariam , RADU, Ionut , LANDRU, Didier , DI CIOCCIO, Lea
IPC分类号： H01L21/60 , H01L23/485
CPC分类号： H01L24/03 , H01L23/481 , H01L24/05 , H01L24/08 , H01L24/80 , H01L2224/03452 , H01L2224/03464 , H01L2224/03466 , H01L2224/03845 , H01L2224/03848 , H01L2224/039 , H01L2224/03901 , H01L2224/05546 , H01L2224/08121 , H01L2224/08146 , H01L2224/0903 , H01L2224/80097 , H01L2224/80099 , H01L2224/80201 , H01L2224/80357 , H01L2224/80895 , H01L2224/80896 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01067 , H01L2924/01074 , H01L2924/01075 , H01L2924/01082 , H01L2224/034
摘要： Methods of bonding together semiconductor structures include annealing a first metal feature on a first semiconductor structure, bonding the first metal feature to a second metal feature of a second semiconductor structure to form a bonded metal structure that comprises the first metal feature and the second metal feature, and annealing the bonded metal structure. Annealing the first metal feature may comprise subjecting the first metal feature to a pre-bonding thermal budget, and annealing the bonded metal structure may comprise subjecting the bonded metal structure to a post-bonding thermal budget that is less than the pre-bonding thermal budget. Bonded semiconductor structures are fabricated using such methods.
摘要翻译：将半导体结构结合在一起的方法包括退火第一半导体结构上的第一金属特征，将第一金属特征结合到第二半导体结构的第二金属特征，以形成包含第一金属特征和第二金属特征，并对结合的金属结构进行退火。退火第一金属特征可以包括使第一金属特征经受预结合热预算，并且对接合的金属结构进行退火可以包括使结合的金属结构经受低于预粘合热预算的后粘合热预算。使用这种方法制造粘合的半导体结构。

7. 发明申请

WO2010049497A1 METHOD OF DETACHING SEMI-CONDUCTOR LAYERS AT LOW TEMPERATURE 审中-公开
标题翻译：在低温下分离半导体层的方法
公开(公告)号：WO2010049497A1
公开(公告)日：2010-05-06
申请号：PCT/EP2009/064308
申请日：2009-10-29
申请人： S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES , LANDRU, Didier , RADU, Ionut , VINCENT, Sébastien
发明人： LANDRU, Didier , RADU, Ionut , VINCENT, Sébastien
IPC分类号： H01L21/762
CPC分类号： H01L21/187 , H01L21/76251
摘要： The invention relates to a method for producing UTBOX type structures comprising: a) the assembly of a substrate, known as "donor" substrate (1), with a substrate, known as "receiver" substrate (2), at least one of the two substrates comprising an insulating layer (3) of thickness less than 50 nm, b) a first heat treatment for reinforcing the assembly between the two substrates, at temperature below 400°C, carried out during the assembly and/or after assembly, to reinforce said assembly, c) a second heat treatment at temperature above 900°C, the exposure time between 400°C and 900°C being less than 1 minute or 30 seconds.
摘要翻译：本发明涉及一种用于生产UTBOX型结构的方法，包括：a）将称为“供体”衬底（1）的衬底与称为“接收器”衬底（2）的衬底的组装，至少一个包括厚度小于50nm的绝缘层（3）的两个基板，b）在组装和/或组装之后执行的在低于400℃的温度下加强两个基板之间的组件的第一热处理，加强所述组件，c）在高于900℃的温度下的第二次热处理，400℃和900℃之间的曝光时间小于1分钟或30秒。

8. 发明申请

WO2013045985A1 METHODS OF TRANSFERRING LAYERS OF MATERIAL IN 3D INTEGRATION PROCESSES AND RELATED STRUCTURES AND DEVICES 审中-公开
标题翻译：在3D集成过程中传输材料层的方法及相关结构与设备
公开(公告)号：WO2013045985A1
公开(公告)日：2013-04-04
申请号：PCT/IB2012/001578
申请日：2012-08-13
申请人： SOITEC , SADAKA, Mariam , RADU, Ionut
发明人： SADAKA, Mariam , RADU, Ionut
IPC分类号： H01L21/762
CPC分类号： H01L21/76254 , H01L27/0688
摘要： Methods of transferring a layer of semiconductor material from a first donor structure to a second structure include forming a generally planar weakened zone within the first donor structure defined by implanted ions therein. At least one of a concentration of the implanted ions and an elemental composition of the implanted ions may be formed to vary laterally across the generally planar weakened zone. The first donor structure may be bonded to a second structure, and the first donor structure may be fractured along the generally planar weakened zone, leaving the layer of semiconductor material bonded to the second structure. Semiconductor devices may be fabricated by forming active device structures on the transferred layer of semiconductor material. Semiconductor structures are fabricated using the described methods.
摘要翻译：将半导体材料层从第一施主结构转移到第二结构的方法包括在由其中的注入离子限定的第一施主结构内形成大致平坦的弱化区。注入离子的浓度和注入离子的元素组成中的至少一种可以形成为跨越大致平坦的弱化区横向变化。第一施主结构可以结合到第二结构，并且第一施主结构可以沿着大致平坦的弱化区断裂，留下半导体材料层与第二结构结合。可以通过在半导体材料的转移层上形成有源器件结构来制造半导体器件。使用所述方法制造半导体结构。

9. 发明申请

WO2012130730A1 METHODS FOR BONDING SEMICONDUCTOR STRUCTURES INVOLVING ANNEALING PROCESSES, AND BONDED SEMICONDUCTOR STRUCTURES AND INTERMEDIATE STRUCTURES FORMED USING SUCH METHODS 审中-公开
标题翻译：用于结合涉及退火工艺的半导体结构的方法以及使用这种方法形成的结合的半导体结构和中间结构
公开(公告)号：WO2012130730A1
公开(公告)日：2012-10-04
申请号：PCT/EP2012/055119
申请日：2012-03-22
申请人： SOITEC , SADAKA, Mariam , RADU, Ionut , LANDRU, Didier
发明人： SADAKA, Mariam , RADU, Ionut , LANDRU, Didier
IPC分类号： H01L21/60 , H01L23/485
CPC分类号： H01L24/03 , H01L24/05 , H01L24/08 , H01L24/80 , H01L2224/0312 , H01L2224/03466 , H01L2224/0381 , H01L2224/03845 , H01L2224/03848 , H01L2224/03901 , H01L2224/05022 , H01L2224/05073 , H01L2224/05147 , H01L2224/05551 , H01L2224/05557 , H01L2224/05558 , H01L2224/05562 , H01L2224/05567 , H01L2224/0557 , H01L2224/05571 , H01L2224/05573 , H01L2224/056 , H01L2224/05647 , H01L2224/0805 , H01L2224/0807 , H01L2224/08121 , H01L2224/08145 , H01L2224/08501 , H01L2224/0903 , H01L2224/80048 , H01L2224/80097 , H01L2224/80099 , H01L2224/80201 , H01L2224/80357 , H01L2224/8583 , H01L2224/85897 , H01L2224/85898 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01025 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01047 , H01L2924/01067 , H01L2924/01074 , H01L2924/01082 , H01L2924/01015 , H01L2924/01014 , H01L2924/01007 , H01L2924/00012 , H01L2224/05552
摘要： Methods of bonding together semiconductor structures include annealing metal of a feature on a semiconductor structure prior to directly bonding the feature to a metal feature of another semiconductor structure to form a bonded metal structure, and annealing the bonded metal structure after the bonding process. The thermal budget of the first annealing process may be at least as high as a thermal budget of a later annealing process. Additional methods involve forming a void in a metal feature, and annealing the metal feature to expand the metal of the feature into the void. Bonded semiconductor structures and intermediate structures are formed using such methods.
摘要翻译：将半导体结构结合在一起的方法包括在将特征直接接合到另一半导体结构的金属特征之前的半导体结构上的特征的退火金属，以形成接合的金属结构，以及在接合工艺之后使接合的金属结构退火。第一退火工艺的热预算可以至少等于后续退火工艺的热预算。附加的方法包括在金属特征中形成空隙，并退火金属特征以将特征的金属扩展到空隙中。使用这种方法形成结合的半导体结构和中间结构。

10. 发明申请

US20120292748A1 METHODS AND STRUCTURES FOR FORMING INTEGRATED SEMICONDUCTOR STRUCTURES 有权
标题翻译：形成集成半导体结构的方法和结构
公开(公告)号：US20120292748A1
公开(公告)日：2012-11-22
申请号：US13522628
申请日：2011-01-04
申请人： Mariam Sadaka , Radu Ionut
发明人： Mariam Sadaka , Radu Ionut
IPC分类号： H01L29/02 , H01L21/762
CPC分类号： H01L25/50 , H01L21/31053 , H01L23/3178 , H01L24/05 , H01L24/80 , H01L25/0657 , H01L2224/0391 , H01L2224/05571 , H01L2224/05624 , H01L2224/05647 , H01L2224/05657 , H01L2224/05676 , H01L2224/05681 , H01L2224/05686 , H01L2224/08146 , H01L2224/80894 , H01L2224/83894 , H01L2225/06513 , H01L2225/06541 , H01L2924/00014 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/0103 , H01L2924/01032 , H01L2924/01033 , H01L2924/01044 , H01L2924/01049 , H01L2924/01051 , H01L2924/01057 , H01L2924/01072 , H01L2924/01073 , H01L2924/01074 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/05042 , H01L2924/12042 , H01L2924/14 , H01L2924/00012 , H01L2224/05552 , H01L2924/00
摘要： The invention provides methods and structures for fabricating a semiconductor structure and particularly for forming a semiconductor structure with improved planarity for achieving a bonded semiconductor structure comprising a processed semiconductor structure and a number of bonded semiconductor layers. Methods for forming semiconductor structures include forming a dielectric layer over a non-planar surface of a processed semiconductor structure, planarizing a surface of the dielectric layer on a side thereof opposite the processed semiconductor structure, and attaching a semiconductor structure to the planarized surface of the dielectric layer. Semiconductor structures include a dielectric layer overlaying a non-planar surface of a processed semiconductor structure, and a masking layer overlaying the dielectric layer on a side thereof opposite the processed semiconductor structure. The masking layer includes a plurality of mask openings over conductive regions of the non-planar surface of the processed semiconductor structure.
摘要翻译：本发明提供了用于制造半导体结构的方法和结构，特别是用于形成具有改善的平面性的半导体结构，以实现包括经处理的半导体结构和多个键合半导体层的键合半导体结构。用于形成半导体结构的方法包括在被处理的半导体结构的非平面表面上形成电介质层，在介电层的与处理的半导体结构相对的一侧上的表面平坦化，以及将半导体结构附着到电介质层。半导体结构包括覆盖加工半导体结构的非平面表面的电介质层和覆盖在与处理的半导体结构相对的一侧上的电介质层的掩模层。掩模层包括在处理的半导体结构的非平面表面的导电区域上的多个掩模开口。

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