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1. 发明授权

US07172963B2 Manufacturing method of semiconductor integrated circuit device that includes chemically and mechanically polishing two conductive layers using two polishing pads that have different properties 失效
标题翻译：包括使用具有不同性质的两个抛光垫对两个导电层进行化学和机械抛光的半导体集成电路器件的制造方法
公开(公告)号：US07172963B2
公开(公告)日：2007-02-06
申请号：US10863776
申请日：2004-06-09
申请人： Yohei Yamada , Nobuhiro Konishi
发明人： Yohei Yamada , Nobuhiro Konishi
IPC分类号： H01L21/4763
CPC分类号： H01L21/7684 , B24B37/04 , H01L21/02074 , H01L21/3212
摘要： In the forming process of buried wirings by filling wiring trenches formed in an insulator with a conductive film mainly made of Cu, the buried wirings are formed to have a uniform-height regardless of the width and density of the wiring trenches. When polishing a barrier conductor film comprised of a Ta film in the CMP process for forming the buried wirings, the polishing agent, which controls the removal rate of the underlying insulator of a silicon oxide film relative to the barrier conductor film to almost one twentieth or less, is used as the slurry, and the pad which is made of polyurethane with a hardness of 75 degrees or more measured by the Type E durometer in conformity with the JIS K6253 and which is comprised of the foam including non-uniform pores with a diameter of about 150 μm or larger and a density of about 0.4–0.16 g/cm3, is used as the polishing pad.
摘要翻译：在通过用主要由Cu制成的导电膜填充在绝缘体中形成的布线沟槽的埋入布线的形成过程中，埋设布线形成为具有均匀高度，而与布线沟槽的宽度和密度无关。在用于形成掩埋布线的CMP工艺中抛光由Ta膜构成的阻挡导体膜时，抛光剂将氧化硅膜相对于阻挡导体膜的下层绝缘体的去除速率控制为几乎二十分之一，较少，用作浆料，并且由根据JIS K6253通过E型硬度计测量的由硬度为75度或更高的聚氨酯制成的垫，其由包含不均匀孔的泡沫构成，所述泡沫包括具有直径为约150μm或更大，密度为约0.4-0.16g / cm 3，用作抛光垫。

2. 发明授权

US6147001A Method of manufacturing semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件的制造方法
公开(公告)号：US6147001A
公开(公告)日：2000-11-14
申请号：US845398
申请日：1997-04-24
申请人： Takeshi Kimura , Hidefumi Ito , Hiroyuki Kojima , Nobuhiro Konishi , Yuuichirou Taguma , Shinichiro Mitani
发明人： Takeshi Kimura , Hidefumi Ito , Hiroyuki Kojima , Nobuhiro Konishi , Yuuichirou Taguma , Shinichiro Mitani
IPC分类号： H01L21/336 , H01L21/304 , H01L21/3105 , H01L21/321 , H01L29/78 , H01L21/302
CPC分类号： B24B37/30 , H01L21/31053 , H01L21/3212
摘要： A method of manufacturing a semiconductor integrated circuit wherein a patterned wafer polishing machine for uniformly polishing a surface by chemical mechanical polishing is utilized which is provided with a head for holding a wafer and rubbing it on an abrasive surface. A pressure plate provided with vents is held by the head body which is provided with a gas inlet and an elastic film for sealing vents is provided on the end face on the side reverse to the gas inlet side of the pressure plate. A patterned wafer is held by the head as the wafer, pressed by action of the pressure of air from the gas inlet via the elastic film is pressed mechanically by the pressure plate. The polishing surface which is a principal plane on the patterned side of the wafer is mechanochemically polished by the abrasive surface.
摘要翻译：一种制造半导体集成电路的方法，其中使用通过化学机械抛光均匀抛光表面的图案化晶片抛光机，其设置有用于保持晶片并将其摩擦在研磨表面上的头部。设置有通风口的压板由设置有气体入口的头体保持，并且在与压力板的气体入口侧相反的一侧的端面上设置用于密封通气口的弹性膜。图案化的晶片由头部保持，作为晶片，通过弹性膜通过来自气体入口的空气的压力的作用被压力机构压迫。作为晶片图案侧的主平面的抛光表面通过研磨表面进行机械化学研磨。

3. 发明授权

US08187966B2 Manufacturing method for semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件的制造方法
公开(公告)号：US08187966B2
公开(公告)日：2012-05-29
申请号：US12411387
申请日：2009-03-25
申请人： Hiroyuki Masuda , Hiroshi Oshita , Nobuhiro Konishi
发明人： Hiroyuki Masuda , Hiroshi Oshita , Nobuhiro Konishi
IPC分类号： H01L21/4763
CPC分类号： H01L21/02074 , H01L21/67046 , H01L21/67051 , H01L21/67219 , H01L21/67745 , H01L21/76808 , H01L21/76832 , H01L21/76834 , H01L2221/1036
摘要： A Cu-CMP step applied to processes for 130 nm, 90 nm, and 65 nm technical nodes or the like mainly employs slurry to which an anticorrosive agent is added for preventing corrosion of Cu wiring. The inventors of the present application have studied and clearly found that in the Cu-CMP step using the slurry with the anticorrosive agent added thereto, the anticorrosive agent often forms complexes with Cu, which remain as foreign matter on a wafer in large quantity, leading to a reduction in yield, and in reliability of TDDB characteristics of the Cu wiring. In the invention of the present application, a post-CMP cleaning process involves applying wet cleaning to a wafer by supplying a cleaning solution, such as a chemical solution or pure water, to a device surface of the wafer substantially in a vertical direction with respect to the horizontal device surface, while rotating the wafer substantially about its center in the horizontal plane. The rotation speed of the wafer is set low such that the thickness of the cleaning solution over the entire device surface becomes substantially uniform.
摘要翻译：应用于130nm，90nm和65nm技术节点等的处理的Cu-CMP步骤主要采用添加有防腐蚀剂以防止Cu布线腐蚀的浆料。本申请的发明人已经研究并清楚地发现，在使用添加了防锈剂的浆料的Cu-CMP步骤中，防腐剂通常与Cu形成复合物，Cu与大量的晶片上留下异物，导致降低产量，并且在Cu布线的TDDB特性的可靠性方面。在本申请的发明中，后CMP清洗工艺涉及通过向晶片的装置表面提供基本上沿垂直方向的清洁溶液（例如化学溶液或纯水）向晶片施加湿清洗同时使晶片基本上绕其水平面的中心旋转。将晶片的旋转速度设定得较低，使得整个器件表面上的清洁溶液的厚度变得基本均匀。

4. 发明申请

US20090286392A1 MANUFACTURING METHOD FOR SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 有权
标题翻译：半导体集成电路器件的制造方法
公开(公告)号：US20090286392A1
公开(公告)日：2009-11-19
申请号：US12411387
申请日：2009-03-25
申请人： Hiroyuki Masuda , Hiroshi Oshita , Nobuhiro Konishi
发明人： Hiroyuki Masuda , Hiroshi Oshita , Nobuhiro Konishi
IPC分类号： H01L21/768
CPC分类号： H01L21/02074 , H01L21/67046 , H01L21/67051 , H01L21/67219 , H01L21/67745 , H01L21/76808 , H01L21/76832 , H01L21/76834 , H01L2221/1036
摘要： A Cu-CMP step applied to processes for 130 nm, 90 nm, and 65 nm technical nodes or the like mainly employs slurry to which an anticorrosive agent is added for preventing corrosion of Cu wiring. The inventors of the present application have studied and clearly found that in the Cu-CMP step using the slurry with the anticorrosive agent added thereto, the anticorrosive agent often forms complexes with Cu, which remain as foreign matter on a wafer in large quantity, leading to a reduction in yield, and in reliability of TDDB characteristics of the Cu wiring. In the invention of the present application, a post-CMP cleaning process involves applying wet cleaning to a wafer by supplying a cleaning solution, such as a chemical solution or pure water, to a device surface of the wafer substantially in a vertical direction with respect to the horizontal device surface, while rotating the wafer substantially about its center in the horizontal plane. The rotation speed of the wafer is set low such that the thickness of the cleaning solution over the entire device surface becomes substantially uniform.
摘要翻译：应用于130nm，90nm和65nm技术节点等的处理的Cu-CMP步骤主要采用添加有防腐蚀剂以防止Cu布线腐蚀的浆料。本申请的发明人已经研究并清楚地发现，在使用添加有防锈剂的浆料的Cu-CMP步骤中，防腐剂通常与Cu大量形成与Cu大量的复合物，其作为异物留在晶片上，导致降低产量，并且在Cu布线的TDDB特性的可靠性方面。在本申请的发明中，后CMP清洗工艺涉及通过向晶片的装置表面提供基本上沿垂直方向的清洁溶液（例如化学溶液或纯水）向晶片施加湿清洗同时使晶片基本上绕其水平面的中心旋转。将晶片的旋转速度设定得较低，使得整个器件表面上的清洁溶液的厚度变得基本均匀。

5. 发明申请

US20050003670A1 Manufacturing method of semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件的制造方法
公开(公告)号：US20050003670A1
公开(公告)日：2005-01-06
申请号：US10863776
申请日：2004-06-09
申请人： Yohei Yamada , Nobuhiro Konishi
发明人： Yohei Yamada , Nobuhiro Konishi
IPC分类号： H01L21/3205 , B24B37/04 , H01L21/02 , H01L21/28 , H01L21/304 , H01L21/306 , H01L21/321 , H01L21/768 , H01L21/4763 , H01L21/302 , H01L21/461
CPC分类号： H01L21/7684 , B24B37/04 , H01L21/02074 , H01L21/3212
摘要： In the forming process of buried wirings by filling wiring trenches formed in an insulator with a conductive film mainly made of Cu, the buried wirings are formed to have a uniform-height regardless of the width and density of the wiring trenches. When polishing a barrier conductor film comprised of a Ta film in the CMP process for forming the buried wirings, the polishing agent which can control the removal rate of the underlying insulator of a silicon oxide film relative to the barrier conductor film to almost one twentieth or less is used as the slurry, and the pad made of polyurethane with a hardness of 75 degrees or more measured by the Type E durometer in conformity with the JIS K6253, which is comprised of the foam including non-uniform pores with a diameter of about 150 μm or larger and a density of about 0.4-0.6 g/cm3, is used as the polishing pad.
摘要翻译：在通过用主要由Cu制成的导电膜填充在绝缘体中形成的布线沟槽的埋入布线的形成过程中，埋设布线形成为具有均匀的高度，而与布线沟槽的宽度和密度无关。在用于形成掩埋布线的CMP工艺中抛光由Ta膜构成的阻挡导体膜时，可以将氧化硅膜相对于阻挡导体膜的下层绝缘体的去除速率控制在几乎二十分之一的抛光剂较少用作浆料，并且通过根据JIS K6253通过E型硬度计测量的硬度为75度以上的聚氨酯制成的垫，其由包括直径约为约的不均匀孔的泡沫构成 150μm或更大，密度约为0.4-0.6g / cm 3被用作抛光垫。

6. 发明授权

US07084063B2 Fabrication method of semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件的制造方法
公开(公告)号：US07084063B2
公开(公告)日：2006-08-01
申请号：US10742932
申请日：2003-12-23
申请人： Junji Noguchi , Shoji Asaka , Nobuhiro Konishi , Naohumi Ohashi , Hiroyuki Maruyama
发明人： Junji Noguchi , Shoji Asaka , Nobuhiro Konishi , Naohumi Ohashi , Hiroyuki Maruyama
IPC分类号： H01L21/302
CPC分类号： H01L21/76843 , H01L21/02074 , H01L21/321 , H01L21/3212 , H01L21/32136 , H01L21/76801 , H01L21/76808 , H01L21/76832 , H01L21/76838 , H01L21/76849 , H01L21/76862 , H01L21/76864 , H01L21/76867 , H01L21/76883 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： The copper interconnect formed by the use of a damascene technique is improved in dielectric breakdown strength (reliability). During post-CMP cleaning, alkali cleaning, a deoxidizing process due to hydrogen annealing or the like, and acid cleaning are carried out in this order. After the post-CMP cleaning and before forming an insulation film for a cap film, hydrogen plasma and ammonia plasma processes are carried out on the semiconductor substrate. In this way, a copper-based buried interconnect is formed in an interlayer insulation film structured of an insulation material having a low dielectric constant.
摘要翻译：通过使用镶嵌技术形成的铜互连在介电击穿强度（可靠性）方面得到改善。在后CMP清洗中，碱洗，由于氢退火等引起的脱氧处理以及酸清洗依次进行。在CMP后清洗之后，在形成用于盖膜的绝缘膜之前，在半导体衬底上进行氢等离子体和氨等离子体处理。以这种方式，在由具有低介电常数的绝缘材料构成的层间绝缘膜中形成铜基掩埋互连。

7. 发明授权

US06949478B2 Oxide film forming method 失效
标题翻译：氧化膜成型方法
公开(公告)号：US06949478B2
公开(公告)日：2005-09-27
申请号：US10120628
申请日：2002-04-11
申请人： Tadahiro Ohmi , Takashi Imaoka , Hisayuki Shimada , Nobuhiro Konishi , Mizuho Morita , Takeo Yamashita , Tadashi Shibata , Hidetoshi Wakamatsu , Jinzo Watanabe , Shintaro Aoyama , Masakazu Nakamura
发明人： Tadahiro Ohmi , Takashi Imaoka , Hisayuki Shimada , Nobuhiro Konishi , Mizuho Morita , Takeo Yamashita , Tadashi Shibata , Hidetoshi Wakamatsu , Jinzo Watanabe , Shintaro Aoyama , Masakazu Nakamura
IPC分类号： B01J19/08 , C23C8/10 , C23C8/36 , C23C14/02 , C23C14/48 , C23C16/02 , C23C16/44 , C30B23/02 , C30B25/02 , G01N23/00 , H01L21/66 , H01L21/31
CPC分类号： C30B23/02 , C23C8/10 , C23C8/36 , C23C14/022 , C23C14/48 , C23C16/02 , C23C16/4401 , C30B25/02 , C30B29/16 , Y10S438/903
摘要： A method of forming an oxide film having high insularity capability is performed within an ultra clean environment, using charged particles.
摘要翻译：使用带电粒子在超清洁环境下进行形成具有高绝缘性的氧化膜的方法。

8. 发明授权

US06723631B2 Fabrication method of semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件的制造方法
公开(公告)号：US06723631B2
公开(公告)日：2004-04-20
申请号：US09965220
申请日：2001-09-28
申请人： Junji Noguchi , Shoji Asaka , Nobuhiro Konishi , Naohumi Ohashi , Hiroyuki Maruyama
发明人： Junji Noguchi , Shoji Asaka , Nobuhiro Konishi , Naohumi Ohashi , Hiroyuki Maruyama
IPC分类号： H01L214763
CPC分类号： H01L21/76843 , H01L21/02074 , H01L21/321 , H01L21/3212 , H01L21/32136 , H01L21/76801 , H01L21/76808 , H01L21/76832 , H01L21/76838 , H01L21/76849 , H01L21/76862 , H01L21/76864 , H01L21/76867 , H01L21/76883 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： The copper interconnect formed by the use of a damascene technique is improved in dielectric breakdown strength (reliability). During post-CMP cleaning, alkali cleaning, a deoxidizing process due to hydrogen annealing or the like, and acid cleaning are carried out in this order. After the post-CMP cleaning and before forming an insulation film for a cap film, hydrogen plasma and ammonia plasma processes are carried out on the semiconductor substrate. In this way, a copper-based buried interconnect is formed in an interlayer insulation film structured of an insulation material having a low dielectric constant.
摘要翻译：通过使用镶嵌技术形成的铜互连在介电击穿强度（可靠性）方面得到改善。在后CMP清洗中，碱洗，由于氢退火等引起的脱氧处理和酸清洗按顺序进行。在CMP后清洗之后，在形成用于盖膜的绝缘膜之前，在半导体衬底上进行氢等离子体和氨等离子体处理。以这种方式，在由具有低介电常数的绝缘材料构成的层间绝缘膜中形成铜基掩埋互连。

9. 发明申请

US20050206018A1 Oxide film forming method 审中-公开
标题翻译：氧化膜成型方法
公开(公告)号：US20050206018A1
公开(公告)日：2005-09-22
申请号：US11129710
申请日：2005-05-13
申请人： Tadahiro Ohmi , Takashi Imaoka , Hisayuki Shimada , Nobuhiro Konishi , Mizuho Morita , Takeo Yamashita , Tadashi Shibata , Hidetoshi Wakamatsu , Jinzo Watanabe , Shintaro Aoyama , Masakazu Nakamura
发明人： Tadahiro Ohmi , Takashi Imaoka , Hisayuki Shimada , Nobuhiro Konishi , Mizuho Morita , Takeo Yamashita , Tadashi Shibata , Hidetoshi Wakamatsu , Jinzo Watanabe , Shintaro Aoyama , Masakazu Nakamura
IPC分类号： B01J19/08 , C23C8/10 , C23C8/36 , C23C14/02 , C23C14/48 , C23C16/02 , C23C16/44 , C30B23/02 , C30B25/02 , G01N23/00 , H01L21/66
CPC分类号： C30B23/02 , C23C8/10 , C23C8/36 , C23C14/022 , C23C14/48 , C23C16/02 , C23C16/4401 , C30B25/02 , C30B29/16 , Y10S438/903
摘要： Vacuum processing equipment capable of preventing particles from sticking to objects to be processed in vacuum vessels. The vacuum equipment comprises a series of vacuum vessels separated by doors, and the pressure in the vessels are reducible respectively. The vessels are so configured that objects to be processed are moveable among them and there is provided light projection means for projecting ultra rays on gases introduced to at least of the vessels.
摘要翻译：真空处理设备能够防止颗粒粘附在真空容器中被处理物体。真空设备包括一系列由门隔开的真空容器，容器中的压力分别可减少。容器被配置成使待处理的物体在它们之间是可移动的，并且设置有用于将超光线投射到至少导入到容器中的气体的光投射装置。

10. 发明授权

US6146135A Oxide film forming method 失效
公开(公告)号：US6146135A
公开(公告)日：2000-11-14
申请号：US680519
申请日：1996-07-09
申请人： Jinzo Watanabe , Takeo Yamashita , Masakazu Nakamura , Shintaro Aoyama , Hidetoshi Wakamatsu , Tadashi Shibata , Tadahiro Ohmi , Nobuhiro Konishi , Mizuho Morita , Hisayuki Shimada , Takashi Imaoka
发明人： Jinzo Watanabe , Takeo Yamashita , Masakazu Nakamura , Shintaro Aoyama , Hidetoshi Wakamatsu , Tadashi Shibata , Tadahiro Ohmi , Nobuhiro Konishi , Mizuho Morita , Hisayuki Shimada , Takashi Imaoka
IPC分类号： B01J19/08 , C23C8/10 , C23C8/36 , C23C14/02 , C23C14/48 , C23C16/02 , C23C16/44 , C30B23/02 , C30B25/02 , G01N23/00 , H01L21/66 , F26B21/00 , F26B3/00 , F26B19/00
CPC分类号： C30B23/02 , C23C14/022 , C23C14/48 , C23C16/02 , C23C16/4401 , C23C8/10 , C23C8/36 , C30B25/02 , C30B29/16 , Y10S438/903
摘要： Vacuum processing equipment capable of preventing particles from sticking to objects to be processed in vacuum vessels. The vacuum equipment comprises a series of vacuum vessels separated by doors, and the pressure in the vessels are reducible respectively. The vessels are so configured that objects to be processed are movable among them, and there is provided light projection means for projecting ultra rays on gases introduced to at least of the vessels.

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