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1. 发明申请

US20110188330A1 SEMICONDUCTOR STORAGE DEVICE 有权
标题翻译：半导体存储设备
公开(公告)号：US20110188330A1
公开(公告)日：2011-08-04
申请号：US13014510
申请日：2011-01-26
申请人： Muneaki MATSUSHIGE , Atsunori Hirobe , Kazutaka Kikuchi , Tetsuo Fukushi
发明人： Muneaki MATSUSHIGE , Atsunori Hirobe , Kazutaka Kikuchi , Tetsuo Fukushi
IPC分类号： G11C7/10 , G11C7/00
CPC分类号： G11C7/00 , G11C7/10
摘要： A semiconductor storage device includes: a plurality of memory cell arrays; a plurality of bidirectional data buses provided in correspondence with respective ones of the plurality of memory cell arrays; a plurality of bidirectional buffer circuits, which are provided in correspondence with respective ones of the memory cell arrays, capable of connecting adjacent bidirectional data buses serially so as to relay data in the bidirectional data buses; and a control circuit for controlling activation of the bidirectional buffer circuits. The bidirectional buffer circuit is arranged so as to invert logic and the bidirectional buffer circuit is arranged so as not to invert logic.
摘要翻译：半导体存储装置包括：多个存储单元阵列; 多个双向数据总线，与所述多个存储单元阵列中的相应数据总线相对应地设置; 多个双向缓冲电路，其与存储单元阵列相对应地设置，能够连续地连接相邻的双向数据总线，以便中继双向数据总线中的数据; 以及用于控制双向缓冲电路的激活的控制电路。双向缓冲电路被布置为反转逻辑，并且双向缓冲电路被布置成不反转逻辑。

2. 发明申请

US20100219870A1 DUTY RATIO CORRECTION CIRCUIT AND DUTY RATIO CORRECTION METHOD 有权
标题翻译：占空比校正电路和占空比校正方法
公开(公告)号：US20100219870A1
公开(公告)日：2010-09-02
申请号：US12697743
申请日：2010-02-01
申请人： Kazutaka KIKUCHI
发明人： Kazutaka KIKUCHI
IPC分类号： H03K3/017
CPC分类号： H03K5/1565
摘要： A duty ratio correction circuit includes a clock input buffer that receives a first clock signal, a clock duty adjuster that adjusts a duty ratio of a second clock signal output from the clock input buffer based on a correction signal and generates a third clock signal, a data input buffer that receives a first data signal, a data duty adjuster that adjusts a duty ratio of a second data signal output from the data input buffer based on the correction signal and generates a third data signal, and a duty comparator that generates the correction signal based on the third clock signal.
摘要翻译：占空比校正电路包括接收第一时钟信号的时钟输入缓冲器，基于校正信号调整从时钟输入缓冲器输出的第二时钟信号的占空比并产生第三时钟信号的时钟占空比调整器，接收第一数据信号的数据输入缓冲器，根据校正信号调整从数据输入缓冲器输出的第二数据信号的占空比并产生第三数据信号的数据占空比调整器，以及产生校正的占空比比较器信号基于第三个时钟信号。

3. 发明授权

US08106696B2 Duty ratio correction circuit and duty ratio correction method 有权
标题翻译：占空比校正电路和占空比校正方法
公开(公告)号：US08106696B2
公开(公告)日：2012-01-31
申请号：US12697743
申请日：2010-02-01
申请人： Kazutaka Kikuchi
发明人： Kazutaka Kikuchi
IPC分类号： H03K3/017
CPC分类号： H03K5/1565
摘要： A duty ratio correction circuit includes a clock input buffer that receives a first clock signal, a clock duty adjuster that adjusts a duty ratio of a second clock signal output from the clock input buffer based on a correction signal and generates a third clock signal, a data input buffer that receives a first data signal, a data duty adjuster that adjusts a duty ratio of a second data signal output from the data input buffer based on the correction signal and generates a third data signal, and a duty comparator that generates the correction signal based on the third clock signal.
摘要翻译：占空比校正电路包括接收第一时钟信号的时钟输入缓冲器，基于校正信号调整从时钟输入缓冲器输出的第二时钟信号的占空比并产生第三时钟信号的时钟占空比调整器，接收第一数据信号的数据输入缓冲器，根据校正信号调整从数据输入缓冲器输出的第二数据信号的占空比并产生第三数据信号的数据占空比调整器，以及产生校正的占空比比较器信号基于第三个时钟信号。

4. 发明申请

US20110181339A1 LEVEL SHIFT CIRCUIT 有权
标题翻译：水平移位电路
公开(公告)号：US20110181339A1
公开(公告)日：2011-07-28
申请号：US13012328
申请日：2011-01-24
申请人： Kazutaka Kikuchi
发明人： Kazutaka Kikuchi
IPC分类号： H03L5/00
CPC分类号： H03K19/018521
摘要： A level shift circuit of the invention includes a CMOS inverter circuit that receives an input pulse signal having a crest value of a first potential, a latch circuit that operates on a power supply of a second potential which is higher than the first potential, and a power supply circuit that supplies a power supply of not less than the first potential and less than the second potential to the CMOS inverter circuit. The latch circuit has one end thereof connected to an output end of the CMOS inverter circuit and outputs from the other end thereof an output pulse signal having a crest value of the second potential and a same phase as the input pulse signal. The power supply circuit functions to limit the power supply when the input pulse signal assumes at least the ground level.
摘要翻译：本发明的电平移位电路包括CMOS反相器电路，其接收具有第一电位的峰值的输入脉冲信号，对高于第一电位的第二电位的电源进行操作的锁存电路，以及电源电路，向CMOS反相电路供给不低于第一电位且小于第二电位的电源。锁存电路的一端连接到CMOS反相器电路的输出端，从另一端输出具有第二电位的峰值和与输入脉冲信号相同相位的输出脉冲信号。当输入脉冲信号至少占地面电平时，电源电路用于限制电源。

5. 发明申请

US20100127733A1 DUTY DETECTION CIRCUIT, DUTY CORRECTION CIRCUIT, AND DUTY DETECTION METHOD 有权
标题翻译：负载检测电路，占空比校正电路和占空比检测方法
公开(公告)号：US20100127733A1
公开(公告)日：2010-05-27
申请号：US12623713
申请日：2009-11-23
申请人： Kazutaka KIKUCHI
发明人： Kazutaka KIKUCHI
IPC分类号： G01R29/02 , H03K3/017
CPC分类号： G01R29/0273 , H03K5/1565
摘要： Provided is a duty detection circuit including: a first capacitor; a first transistor that controls charge or discharge currents of the first capacitor during a first period of a clock signal; a second capacitor; a second transistor that controls charge or discharge currents of the second capacitor during a second period of the clock signal; and a latch circuit that detects that a potential of one of the first capacitor and the second capacitor reaches a predetermined potential, and latches an output based on a result of the detection.
摘要翻译：提供一种占空比检测电路，包括：第一电容器; 在时钟信号的第一周期期间控制第一电容器的充电或放电电流的第一晶体管; 第二电容器; 在所述时钟信号的第二周期期间控制所述第二电容器的充电或放电电流的第二晶体管; 以及锁存电路，其检测第一电容器和第二电容器中的一个的电位达到预定电位，并且基于检测结果锁存输出。

6. 发明授权

US08493125B2 Level shift circuit 有权
公开(公告)号：US08493125B2
公开(公告)日：2013-07-23
申请号：US13012328
申请日：2011-01-24
申请人： Kazutaka Kikuchi
发明人： Kazutaka Kikuchi
IPC分类号： H03L5/00
CPC分类号： H03K19/018521
摘要： A level shift circuit of the invention includes a CMOS inverter circuit that receives an input pulse signal having a crest value of a first potential, a latch circuit that operates on a power supply of a second potential which is higher than the first potential, and a power supply circuit that supplies a power supply of not less than the first potential and less than the second potential to the CMOS inverter circuit. The latch circuit has one end thereof connected to an output end of the CMOS inverter circuit and outputs from the other end thereof an output pulse signal having a crest value of the second potential and a same phase as the input pulse signal. The power supply circuit functions to limit the power supply when the input pulse signal assumes at least the ground level.

7. 发明授权

US08335116B2 Semiconductor storage device 有权
标题翻译：半导体存储设备
公开(公告)号：US08335116B2
公开(公告)日：2012-12-18
申请号：US13014510
申请日：2011-01-26
申请人： Muneaki Matsushige , Atsunori Hirobe , Kazutaka Kikuchi , Tetsuo Fukushi
发明人： Muneaki Matsushige , Atsunori Hirobe , Kazutaka Kikuchi , Tetsuo Fukushi
IPC分类号： G11C7/00 , G11C8/00 , G11C8/16
CPC分类号： G11C7/00 , G11C7/10
摘要： A semiconductor storage device includes: a plurality of memory cell arrays; a plurality of bidirectional data buses provided in correspondence with respective ones of the plurality of memory cell arrays; a plurality of bidirectional buffer circuits, which are provided in correspondence with respective ones of the memory cell arrays, capable of connecting adjacent bidirectional data buses serially so as to relay data in the bidirectional data buses; and a control circuit for controlling activation of the bidirectional buffer circuits. The bidirectional buffer circuit is arranged so as to invert logic and the bidirectional buffer circuit is arranged so as not to invert logic.
摘要翻译：半导体存储装置包括：多个存储单元阵列; 多个双向数据总线，与所述多个存储单元阵列中的相应数据总线相对应地设置; 多个双向缓冲电路，其与存储单元阵列相对应地设置，能够连续地连接相邻的双向数据总线，以便中继双向数据总线中的数据; 以及用于控制双向缓冲电路的激活的控制电路。双向缓冲电路被布置为反转逻辑，并且双向缓冲电路被布置成不反转逻辑。

8. 发明授权

US08305123B2 Duty detection circuit, duty correction circuit, and duty detection method 有权
标题翻译：占空比检测电路，占空比校正电路和占空比检测方法
公开(公告)号：US08305123B2
公开(公告)日：2012-11-06
申请号：US12623713
申请日：2009-11-23
申请人： Kazutaka Kikuchi
发明人： Kazutaka Kikuchi
IPC分类号： H03K3/017
CPC分类号： G01R29/0273 , H03K5/1565
摘要： Provided is a duty detection circuit including: a first capacitor; a first transistor that controls charge or discharge currents of the first capacitor during a first period of a clock signal; a second capacitor; a second transistor that controls charge or discharge currents of the second capacitor during a second period of the clock signal; and a latch circuit that detects that a potential of one of the first capacitor and the second capacitor reaches a predetermined potential, and latches an output based on a result of the detection.
摘要翻译：提供一种占空比检测电路，包括：第一电容器; 在时钟信号的第一周期期间控制第一电容器的充电或放电电流的第一晶体管; 第二电容器; 在所述时钟信号的第二周期期间控制所述第二电容器的充电或放电电流的第二晶体管; 以及锁存电路，其检测第一电容器和第二电容器中的一个的电位达到预定电位，并且基于检测结果锁存输出。

9. 发明申请

US20120313686A1 LEVEL SHIFT CIRCUIT 有权
标题翻译：水平移位电路
公开(公告)号：US20120313686A1
公开(公告)日：2012-12-13
申请号：US13593010
申请日：2012-08-23
申请人： Kazutaka KIKUCHI
发明人： Kazutaka KIKUCHI
IPC分类号： H03L5/00
CPC分类号： H03K19/018521
摘要： A level shift circuit of the invention includes a CMOS inverter circuit that receives an input pulse signal having a crest value of a first potential, a latch circuit that operates on a power supply of a second potential which is higher than the first potential, and a power supply circuit that supplies a power supply of not less than the first potential and less than the second potential to the CMOS inverter circuit. The latch circuit has one end thereof connected to an output end of the CMOS inverter circuit and outputs from the other end thereof an output pulse signal having a crest value of the second potential and a same phase as the input pulse signal. The power supply circuit functions to limit the power supply when the input pulse signal assumes at least the ground level.
摘要翻译：本发明的电平移位电路包括CMOS反相器电路，其接收具有第一电位的峰值的输入脉冲信号，对高于第一电位的第二电位的电源进行操作的锁存电路，以及电源电路，向CMOS反相电路供给不低于第一电位且小于第二电位的电源。锁存电路的一端连接到CMOS反相器电路的输出端，从另一端输出具有第二电位的峰值和与输入脉冲信号相同相位的输出脉冲信号。当输入脉冲信号至少占地面电平时，电源电路用于限制电源。

10. 发明授权

US08305135B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08305135B2
公开(公告)日：2012-11-06
申请号：US12926130
申请日：2010-10-27
申请人： Kazutaka Kikuchi
发明人： Kazutaka Kikuchi
IPC分类号： G05F1/10
CPC分类号： G05F1/56
摘要： This invention allows for stable operation of a circuit to which an output voltage is supplied. The invention resides in a semiconductor device comprising a VREF1 regulator to which a reference voltage Vref1 relative to a first potential is input; and an output circuit which generates an output voltage Vint that is proportional to a voltage on its input terminal relative to a second potential. The VREF1 regulator comprises a constant current source which generates a constant current having a current value that is proportional to the reference voltage Vref1; and a first resistor element which is supplied with the constant current, one end of which is coupled to the input terminal of the output circuit and the other end of which is coupled to the second potential.
摘要翻译：本发明允许提供输出电压的电路的稳定操作。本发明涉及一种半导体器件，其包括相对于第一电位输入参考电压Vref1的VREF1调节器; 以及输出电路，其产生与其输入端子上的相对于第二电位的电压成比例的输出电压Vint。 VREF1调节器包括恒定电流源，其产生具有与参考电压Vref1成比例的电流值的恒定电流; 以及第一电阻元件，其被提供有恒定电流，其一端耦合到输出电路的输入端并且另一端耦合到第二电位。

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