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1. 发明授权

US06933579B1 Semiconductor solid phase epitaxy damage control method and integrated circuit produced thereby 有权
标题翻译：由此产生的半导体固相外延损伤控制方法和集成电路
公开(公告)号：US06933579B1
公开(公告)日：2005-08-23
申请号：US10728001
申请日：2003-12-03
申请人： William George En , Witold P. Maszara , Mario M. Pelella
发明人： William George En , Witold P. Maszara , Mario M. Pelella
IPC分类号： H01L21/265 , H01L21/336 , H01L29/78
CPC分类号： H01L29/66628 , H01L21/26506 , H01L29/6656 , H01L29/66636 , H01L29/7834
摘要： A method of forming an integrated circuit with a semiconductor substrate is provided. A gate dielectric is formed on the semiconductor substrate, and a gate is formed on the gate dielectric. A raised source/drain layer is formed on the semiconductor substrate adjacent the gate and the gate dielectric. An amorphized shallow source/drain extension implanted region is formed in the raised source/drain layer and the semiconductor substrate therebeneath. The amorphized region is then recrystallized to form a shallow source/drain extension having residual recrystallization damage elevated into the raised source/drain layer.
摘要翻译：提供一种形成具有半导体衬底的集成电路的方法。在半导体衬底上形成栅极电介质，在栅极电介质上形成栅极。凸起的源极/漏极层形成在与栅极和栅极电介质相邻的半导体衬底上。在凸起的源极/漏极层和其下的半导体衬底上形成非晶化的浅源极/漏极延伸注入区。然后将非晶化区域重结晶以形成具有升高到升高的源极/漏极层中的残余再结晶损伤的浅源/漏极延伸。

2. 发明授权

US06509613B1 Self-aligned floating body control for SOI device through leakage enhanced buried oxide 有权
标题翻译：用于SOI器件的自对准浮体控制通过泄漏增强掩埋氧化物
公开(公告)号：US06509613B1
公开(公告)日：2003-01-21
申请号：US09849494
申请日：2001-05-04
申请人： William George En , Srinath Krishnan , Judy Xilin An
发明人： William George En , Srinath Krishnan , Judy Xilin An
IPC分类号： H01L2701
CPC分类号： H01L29/66772 , H01L29/78612
摘要： A semiconductor-on-insulator (SOI) device formed on an SOI structure with a buried oxide (BOX) layer disposed therein and an active region disposed on the BOX layer having active regions defined by isolation trenches and the BOX layer. The SOI device includes a gate formed over one of the active regions. The gate defines a channel interposed between a source and a drain formed within one of the active regions. The SOI device includes a leakage enhanced region within the BOX layer defined by the gate.
摘要翻译：在SOI结构上形成有埋置氧化物（BOX）层的绝缘体上半导体器件（SOI）器件，以及设置在BOX层上的有源区域，其中有源区域由隔离沟槽和BOX层限定。 SOI器件包括形成在一个有源区上的栅极。栅极限定插入在一个有源区域内形成的源极和漏极之间的沟道。 SOI器件包括由栅极限定的BOX层内的泄漏增强区域。

3. 发明授权

US07298012B2 Shallow junction semiconductor 失效
标题翻译：浅结半导体
公开(公告)号：US07298012B2
公开(公告)日：2007-11-20
申请号：US11307537
申请日：2006-02-11
申请人： Mario M. Pelella , William George En , Eric Paton , Witold P. Maszara
发明人： Mario M. Pelella , William George En , Eric Paton , Witold P. Maszara
IPC分类号： H01L29/76
CPC分类号： H01L29/665 , H01L21/26506 , H01L21/28518 , H01L21/823814 , H01L29/6656 , H01L29/6659
摘要： An integrated circuit with a semiconductor substrate is provided. A gate dielectric is on the semiconductor substrate, and a gate is on the gate dielectric. A silicide layer is on the semiconductor substrate adjacent the gate and the gate dielectric. The silicide layer incorporates a substantially uniformly distributed and concentrated dopant therein. A shallow source/drain junction is beneath the salicide layer. An interlayer dielectric is above the semiconductor substrate, and contacts are in the interlayer dielectric to the salicide layer.
摘要翻译：提供了具有半导体衬底的集成电路。栅极电介质位于半导体衬底上，栅极位于栅极电介质上。硅化物层位于与栅极和栅极电介质相邻的半导体衬底上。硅化物层在其中包含基本均匀分布和浓缩的掺杂剂。浅层源极/漏极结在自对准层下面。层间电介质位于半导体衬底之上，并且触点位于硅化物层的层间电介质中。

4. 发明授权

US07211473B1 Method and structure for controlling floating body effects 有权
标题翻译：控制浮体效应的方法和结构
公开(公告)号：US07211473B1
公开(公告)日：2007-05-01
申请号：US10756585
申请日：2004-01-12
申请人： Mario M. Pelella , William George En , Ping-Chin Yeh
发明人： Mario M. Pelella , William George En , Ping-Chin Yeh
IPC分类号： H01L21/00
CPC分类号： H01L29/78612 , H01L29/66772
摘要： A method for forming an integrated circuit with a semiconductor substrate is provided. A gate dielectric is formed on the semiconductor substrate, and a gate is formed on the gate dielectric. Source/drain junctions are formed in the semiconductor substrate adjacent the gate. A facet is formed in at least one of the source/drain junctions of the integrated circuit.
摘要翻译：提供了一种用于形成具有半导体衬底的集成电路的方法。在半导体衬底上形成栅极电介质，在栅极电介质上形成栅极。源极/漏极结形成在与栅极相邻的半导体衬底中。在集成电路的源极/漏极结中的至少一个上形成刻面。

5. 发明授权

US07033916B1 Shallow junction semiconductor and method for the fabrication thereof 失效
标题翻译：浅结半导体及其制造方法
公开(公告)号：US07033916B1
公开(公告)日：2006-04-25
申请号：US10770990
申请日：2004-02-02
申请人： Mario M. Pelella , William George En , Eric Paton , Witold P. Maszara
发明人： Mario M. Pelella , William George En , Eric Paton , Witold P. Maszara
IPC分类号： H01L21/22 , H01L21/336 , H01L21/8234 , H01L21/44
CPC分类号： H01L29/665 , H01L21/26506 , H01L21/28518 , H01L21/823814 , H01L29/6656 , H01L29/6659
摘要： A method of forming an integrated circuit with a semiconductor substrate is provided. A gate dielectric is formed on the semiconductor substrate, and a gate is formed on the gate dielectric. A super-saturated doped source silicide metallic layer is formed on the semiconductor substrate adjacent the gate and the gate dielectric. The silicide metallic layer incorporates a substantially uniformly distributed dopant therein in a substantially uniform super-saturated concentration. The silicide metallic layer is reacted with the semiconductor substrate therebeneath to form a salicide layer and outdiffuse the dopant from the salicide layer into the semiconductor substrate therebeneath. The outdiffused dopant in the semiconductor substrate is then activated to form a shallow source/drain junction beneath the salicide layer. An interlayer dielectric is then deposited above the semiconductor substrate, and contacts are formed in the interlayer dielectric to the salicide layer.
摘要翻译：提供一种形成具有半导体衬底的集成电路的方法。在半导体衬底上形成栅极电介质，在栅极电介质上形成栅极。在与栅极和栅极电介质相邻的半导体衬底上形成超饱和掺杂源极化硅金属层。硅化金属层以基本均匀的超饱和浓度掺入其中基本上均匀分布的掺杂剂。硅化物金属层与其下面的半导体衬底反应以形成自对准硅化物层，并将掺杂剂从硅化物层扩散到其内的半导体衬底中。然后激活半导体衬底中的向外扩散的掺杂剂以在自对准硅化物层下面形成浅的源极/漏极结。然后在半导体衬底上沉积层间电介质，并且在层间电介质中形成接触到硅化物层。

6. 发明授权

US06812550B1 Wafer pattern variation of integrated circuit fabrication 失效
标题翻译：集成电路制造的晶圆图案变化
公开(公告)号：US06812550B1
公开(公告)日：2004-11-02
申请号：US10700733
申请日：2003-11-03
申请人： William George En , Eric Paton , Mario M. Pelella , Witold P. Maszara
发明人： William George En , Eric Paton , Mario M. Pelella , Witold P. Maszara
IPC分类号： H01L2358
CPC分类号： H01L23/585 , H01L22/14 , H01L23/34 , H01L2924/0002 , H01L2924/3511 , H01L2924/00
摘要： A method for manufacturing an integrated circuit on a semiconductor wafer is provided. The semiconductor wafer has complete die and partial die areas thereon. Functional circuit patterns are formed in a plurality of the complete die areas. The thermal absorption properties of the semiconductor wafer are tuned by forming differing patterns in a plurality of the partial die areas.
摘要翻译：提供了一种在半导体晶片上制造集成电路的方法。半导体晶片在其上具有完整的模具和部分模具区域。功能电路图案形成在多个完整的模具区域中。通过在多个部分管芯区域中形成不同的图案来调整半导体晶片的热吸收性能。

7. 发明授权

US06573172B1 Methods for improving carrier mobility of PMOS and NMOS devices 有权
标题翻译：改善PMOS和NMOS器件载流子迁移率的方法
公开(公告)号：US06573172B1
公开(公告)日：2003-06-03
申请号：US10244439
申请日：2002-09-16
申请人： William George En , Angela Hui , Minh Van Ngo
发明人： William George En , Angela Hui , Minh Van Ngo
IPC分类号： H01L214763
CPC分类号： H01L21/76832 , H01L21/823807 , H01L21/823828 , H01L29/7833 , H01L29/7842 , H01L29/7843
摘要： Methods are described for fabricating semiconductor devices, in which a tensile film is formed over PMOS transistors to cause a compressive stress therein and a compressive film is formed over NMOS transistors to achieve a tensile stress therein, by which improved carrier mobility is facilitated in both PMOS and NMOS devices.
摘要翻译：描述了用于制造半导体器件的方法，其中在PMOS晶体管上形成拉伸膜以在其中引起压应力，并且在NMOS晶体管上形成压缩膜以在其中实现拉伸应力，由此在PMOS中增加载流子迁移率和NMOS器件。

8. 发明授权

US06433391B1 Bonded SOI for floating body and metal gettering control 失效
标题翻译：焊接SOI用于浮体和金属吸气控制
公开(公告)号：US06433391B1
公开(公告)日：2002-08-13
申请号：US09877631
申请日：2001-06-08
申请人： William George En , Dong-Hyuk Ju
发明人： William George En , Dong-Hyuk Ju
IPC分类号： H01L2900
CPC分类号： H01L29/78612 , H01L21/3226 , H01L29/4908 , H01L29/66772 , H01L29/78603
摘要： A device and method for making a semiconductor-on-insulator (SOI) structure having an insulator layer disposed between a semiconductor substrate and a semiconductor layer. An interface between the insulator layer and the semiconductor layer bleeds off extra carriers. Active regions are defined in the semiconductor layer by isolation trenches and the insulator layer.
摘要翻译：一种用于制造绝缘体上半导体（SOI）结构的器件和方法，其具有设置在半导体衬底和半导体层之间的绝缘体层。绝缘体层和半导体层之间的界面使额外的载流子流出。有源区通过隔离沟槽和绝缘体层限定在半导体层中。

9. 发明授权

US5963412A Process induced charging damage control device 失效
标题翻译：过程感应充电损坏控制装置
公开(公告)号：US5963412A
公开(公告)日：1999-10-05
申请号：US969580
申请日：1997-11-13
申请人： William George En
发明人： William George En
IPC分类号： H01L27/02 , H02H3/22
CPC分类号： H01L27/0248
摘要： A plasma charging damage protection structure (40, 104) includes a first conduction path (90) for conducting positive plasma charging away from a device needing protection (44) and a second conduction path (94) for conducting negative plasma charging away from the device needing protection (44). In addition, a method (200) of preventing plasma induced charging damage includes the forming of plasma charging during semiconductor processing (202). The method also includes conducting the plasma charging through a first conduction path if the plasma charging is positive (210) and conducting the plasma charging through a second conduction path if the plasma charging is negative (214).
摘要翻译：等离子体充电损伤保护结构（40,104）包括用于从需要保护的装置（44）和第二导电路径（94）进行正等离子体充电的第一导电路径（90），用于将远离装置的负等离子体充电需要保护（44）。此外，防止等离子体诱导的充电损坏的方法（200）包括在半导体处理期间形成等离子体充电（202）。如果等离子体充电是正的（210）并且如果等离子体充电是负的，则通过第二导电路径进行等离子体充电（214），该方法还包括通过第一导电路径进行等离子体充电。

10. 发明授权

US07071044B1 Method of making a test structure for gate-body current and direct extraction of physical gate length using conventional CMOS 失效
标题翻译：使用常规CMOS制作门体电流测试结构并直接提取物理栅极长度的方法
公开(公告)号：US07071044B1
公开(公告)日：2006-07-04
申请号：US10838229
申请日：2004-05-05
申请人： Srinath Krishnan , William George En
发明人： Srinath Krishnan , William George En
IPC分类号： H01L21/336
CPC分类号： H01L21/84 , H01L22/34 , H01L29/105 , H01L29/78621
摘要： A structure for testing relative to an MOS transistor, can be easily constructed as part of the CMOS process flow. A doped device well is formed, for example, in a silicon-on-insulator structure. The concentration level in the well corresponds to that for a well of the transistor. Gate insulator and polysilicon layers are formed, and the polysilicon is implanted with dopant, to a concentration level expected in the transistor gate. After gate patterning, the methodology involves forming sidewall spacers and implanting dopant into the active device well, to form regions in the test structure corresponding to the transistor source and drain. Although the concentrations mimic those in the transistor source and drain, these test structure regions are doped with opposite type dopant material. The test structure enables accurate measurement of the gate-body current, for modeling floating body effects and/or for measurement of gate length.
摘要翻译：用于相对于MOS晶体管测试的结构可以容易地构建为CMOS工艺流程的一部分。掺杂器件阱例如在绝缘体上硅结构中形成。阱中的浓度水平对应于晶体管的阱。形成栅极绝缘体和多晶硅层，并且将掺杂剂注入多晶硅至晶体管栅极中预期的浓度水平。在栅极图案化之后，该方法涉及形成侧壁间隔物并将掺杂剂注入到有源器件阱中，以在对应于晶体管源极和漏极的测试结构中形成区域。尽管浓度模拟晶体管源极和漏极中的浓度，但是这些测试结构区域掺杂有相反类型的掺杂剂材料。测试结构能够准确测量门体电流，用于建模浮体效应和/或测量栅极长度。

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