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1. 发明申请

US20080054316A1 STRAINED FULLY DEPLETED SILICON ON INSULATOR SEMICONDUCTOR DEVICE 有权
标题翻译：绝缘子半导体器件上残留的全部绝缘硅
公开(公告)号：US20080054316A1
公开(公告)日：2008-03-06
申请号：US11926655
申请日：2007-10-29
申请人： Qi Xiang , Niraj Subba , Witold Maszara , Zoran Krivokapic , Ming-Ren Lin
发明人： Qi Xiang , Niraj Subba , Witold Maszara , Zoran Krivokapic , Ming-Ren Lin
IPC分类号： H01L29/78
CPC分类号： H01L29/66772 , H01L29/66636 , H01L29/7842 , H01L29/7848 , H01L29/78639 , H01L29/78684 , Y10S438/938
摘要： A semiconductor substrate is provided having an insulator thereon with a semiconductor layer on the insulator. A deep trench isolation is formed, introducing strain to the semiconductor layer. A gate dielectric and a gate are formed on the semiconductor layer. A spacer is formed around the gate, and the semiconductor layer and the insulator are removed outside the spacer. Recessed source/drain are formed outside the spacer.
摘要翻译：提供了一种在绝缘体上具有半导体层的绝缘体的半导体衬底。形成深沟槽隔离，向半导体层引入应变。栅极电介质和栅极形成在半导体层上。在栅极周围形成间隔物，并且将半导体层和绝缘体去除在间隔物的外部。凹陷的源极/漏极形成在间隔物外部。

2. 发明申请

US20060099752A1 Strained fully depleted silicon on insulator semiconductor device and manufacturing method therefor 失效
标题翻译：应变完全耗尽的绝缘体上硅绝缘体器件及其制造方法
公开(公告)号：US20060099752A1
公开(公告)日：2006-05-11
申请号：US10986399
申请日：2004-11-10
申请人： Qi Xiang , Niraj Subba , Witold Maszara , Zoran Krivokapic , Ming-Ren Lin
发明人： Qi Xiang , Niraj Subba , Witold Maszara , Zoran Krivokapic , Ming-Ren Lin
IPC分类号： H01L21/8234 , H01L21/336
CPC分类号： H01L29/66772 , H01L29/66636 , H01L29/7842 , H01L29/7848 , H01L29/78639 , H01L29/78684 , Y10S438/938
摘要： A semiconductor substrate is provided having an insulator thereon with a semiconductor layer on the insulator. A deep trench isolation is formed, introducing strain to the semiconductor layer. A gate dielectric and a gate are formed on the semiconductor layer. A spacer is formed around the gate, and the semiconductor layer and the insulator are removed outside the spacer. Recessed source/drain are formed outside the spacer.
摘要翻译：提供了一种在绝缘体上具有半导体层的绝缘体的半导体衬底。形成深沟槽隔离，向半导体层引入应变。栅极电介质和栅极形成在半导体层上。在栅极周围形成间隔物，并且将半导体层和绝缘体去除在间隔物的外部。凹陷的源极/漏极形成在间隔物外部。

3. 发明授权

US07871873B2 Method of forming fin structures using a sacrificial etch stop layer on bulk semiconductor material 有权
标题翻译：在体半导体材料上使用牺牲蚀刻停止层形成翅片结构的方法
公开(公告)号：US07871873B2
公开(公告)日：2011-01-18
申请号：US12413174
申请日：2009-03-27
申请人： Witold Maszara , Ming-Ren Lin , Jin Cho , Zoran Krivokapic
发明人： Witold Maszara , Ming-Ren Lin , Jin Cho , Zoran Krivokapic
IPC分类号： H01L21/00 , H01L21/84 , H01L21/336
CPC分类号： H01L29/66795
摘要： A method of manufacturing semiconductor fins for a semiconductor device may begin by providing a bulk semiconductor substrate. The method continues by growing a layer of first epitaxial semiconductor material on the bulk semiconductor substrate, and by growing a layer of second epitaxial semiconductor material on the layer of first epitaxial semiconductor material. The method then creates a fin pattern mask on the layer of second epitaxial semiconductor material. The fin pattern mask has features corresponding to a plurality of fins. Next, the method anisotropically etches the layer of second epitaxial semiconductor material, using the fin pattern mask as an etch mask, and using the layer of first epitaxial semiconductor material as an etch stop layer. This etching step results in a plurality of fins formed from the layer of second epitaxial semiconductor material.
摘要翻译：制造用于半导体器件的半导体鳍片的方法可以通过提供体半导体衬底开始。该方法通过在体半导体衬底上生长第一外延半导体材料层并通过在第一外延半导体材料层上生长第二外延半导体材料层来继续。该方法然后在第二外延半导体材料层上产生鳍状图案掩模。翅片图形掩模具有对应于多个翅片的特征。接下来，使用鳍图案掩模作为蚀刻掩模，并且使用第一外延半导体材料层作为蚀刻停止层，该方法各向异性地蚀刻第二外延半导体材料的层。该蚀刻步骤导致由第二外延半导体材料层形成的多个鳍片。

4. 发明授权

US06873030B2 Metal gate electrode using silicidation and method of formation thereof 有权
标题翻译：使用硅化物的金属栅电极及其形成方法
公开(公告)号：US06873030B2
公开(公告)日：2005-03-29
申请号：US10431008
申请日：2003-05-07
申请人： Witold Maszara , Zoran Krivokapic
发明人： Witold Maszara , Zoran Krivokapic
IPC分类号： H01L21/28 , H01L21/285 , H01L21/336 , H01L29/423 , H01L29/49 , H01L29/78 , H01L27/082 , H01L29/76
CPC分类号： H01L21/28518 , H01L21/28097 , H01L29/4975 , H01L29/665 , H01L29/66545 , H01L29/6659
摘要： A semiconductor device is fabricated by providing a substrate, and providing a dielectric layer on the substrate. A polysilicon body is formed on the dielectric layer, and a metal layer is provided on the polysilicon body. A silicidation process is undertaken to silicidize substantially the entire polysilicon body to form a gate on the dielectric. In an alternative process, a cap layer is provided on the polysilicon body, which cap layer is removed prior to the silicidation process. The polysilicon body is doped with a chosen specie prior to the silicidation process, which dopant, during the silicidation process, is driven toward the dielectric layer to form a gate portion having a high concentration thereof adjacent the dielectric, the type and concentration of this specie being instrumental in determining the work function of the formed gate.
摘要翻译：通过提供衬底来制造半导体器件，并在衬底上提供介电层。在电介质层上形成多晶硅体，在多晶硅体上设置金属层。进行硅化处理以基本上硅化整个多晶硅体以在电介质上形成栅极。在替代方法中，在多晶硅体上设置覆盖层，在硅化过程之前去除盖层。在硅化过程之前，多晶硅体掺杂有选择的特性，在硅化过程期间，该掺杂剂被驱动到电介质层，以形成其邻近电介质的高浓度的栅极部分，该物质的类型和浓度有助于确定形成的门的工作功能。

5. 发明授权

US06599831B1 Metal gate electrode using silicidation and method of formation thereof 有权
标题翻译：使用硅化物的金属栅电极及其形成方法
公开(公告)号：US06599831B1
公开(公告)日：2003-07-29
申请号：US10135227
申请日：2002-04-30
申请人： Witold Maszara , Zoran Krivokapic
发明人： Witold Maszara , Zoran Krivokapic
IPC分类号： H01L214763
CPC分类号： H01L21/28518 , H01L21/28097 , H01L29/4975 , H01L29/665 , H01L29/66545 , H01L29/6659
摘要： A semiconductor device is fabricated by providing a substrate, and providing a dielectric layer on the substrate. A polysilicon body is formed on the dielectric layer, and a metal layer is provided on the polysilicon body. A silicidation process is undertaken to silicidize substantially the entire polysilicon body to form a gate on the dielectric. In an alternative process, a cap layer is provided on the polysilicon body, which cap layer is removed prior to the silicidation process. The polysilicon body is doped with a chosen specie prior to the silicidation process, which dopant, during the silicidation process, is driven toward the dielectric layer to form a gate portion having a high concentration thereof adjacent the dielectric, the type and concentration of this specie being instrumental in determining the work function of the formed gate.
摘要翻译：通过提供衬底来制造半导体器件，并在衬底上提供介电层。在电介质层上形成多晶硅体，在多晶硅体上设置金属层。进行硅化处理以基本上硅化整个多晶硅体以在电介质上形成栅极。在替代方法中，在多晶硅体上设置覆盖层，在硅化过程之前去除盖层。在硅化过程之前，多晶硅体掺杂有选择的特性，在硅化过程期间，该掺杂剂被驱动到电介质层，以形成其邻近电介质的高浓度的栅极部分，该物质的类型和浓度有助于确定形成的门的工作功能。

6. 发明申请

US20060177998A1 FULLY SILICIDED GATE STRUCTURE FOR FINFET DEVICES 有权
标题翻译： FINFET器件的完全硅胶结构
公开(公告)号：US20060177998A1
公开(公告)日：2006-08-10
申请号：US11379435
申请日：2006-04-20
申请人： Ming-Ren Lin , Witold Maszara , Haihong Wang , Bin Yu
发明人： Ming-Ren Lin , Witold Maszara , Haihong Wang , Bin Yu
IPC分类号： H01L21/3205
CPC分类号： H01L29/785 , H01L29/4908 , H01L29/66795 , H01L29/7842
摘要： A method may include forming a gate electrode over a fin structure, depositing a first metal layer on a top surface of the gate electrode, performing a first silicide process to convert a portion of the gate electrode into a metal-silicide compound, depositing a second metal layer on a top surface of the metal-silicide compound, and performing a second silicide process to form a fully-silicided gate electrode.
摘要翻译：一种方法可以包括在鳍结构上形成栅电极，在栅电极的顶表面上沉积第一金属层，执行第一硅化工艺以将栅电极的一部分转化为金属硅化物，在金属硅化物化合物的顶表面上的金属层，并且执行第二硅化物处理以形成全硅化物栅电极。

7. 发明申请

US20050048727A1 FORMATION OF FINFET USING A SIDEWALL EPITAXIAL LAYER 有权
标题翻译：使用边墙外延层形成FINFET
公开(公告)号：US20050048727A1
公开(公告)日：2005-03-03
申请号：US10654631
申请日：2003-09-03
申请人： Witold Maszara , Jung-Suk Goo , James Pan , Qi Xiang
发明人： Witold Maszara , Jung-Suk Goo , James Pan , Qi Xiang
IPC分类号： A61F5/37 , H01L21/336 , H01L29/10 , H01L29/786
CPC分类号： H01L29/785 , A61F5/3776 , H01L29/1054 , H01L29/66795 , H01L29/78687 , Y10S438/933
摘要： A method of forming a finFET transistor using a sidewall epitaxial layer includes forming a silicon germanium (SiGe) layer above an oxide layer above a substrate, forming a cap layer above the SiGe layer, removing portions of the SiGe layer and the cap layer to form a feature, forming sidewalls along lateral walls of the feature, and removing the feature.
摘要翻译：使用侧壁外延层形成finFET晶体管的方法包括在衬底上方的氧化层上形成硅锗（SiGe）层，在SiGe层上方形成覆盖层，去除SiGe层和覆盖层的部分以形成特征，沿着所述特征的侧壁形成侧壁，以及去除所述特征。

8. 发明申请

US20050048743A1 Method of growing as a channel region to reduce source/drain junction capicitance 有权
标题翻译：作为渠道区域生长以减少源/汇交汇率资本的方法
公开(公告)号：US20050048743A1
公开(公告)日：2005-03-03
申请号：US10654497
申请日：2003-09-03
申请人： Ihsan Djomehri , Jung-Suk Goo , Srinath Krishnan , Witold Maszara , James Pan , Qi Xiang
发明人： Ihsan Djomehri , Jung-Suk Goo , Srinath Krishnan , Witold Maszara , James Pan , Qi Xiang
IPC分类号： H01L21/20 , H01L29/06 , H01L29/08 , H01L29/10 , H01L29/78
CPC分类号： H01L29/0847 , H01L21/02381 , H01L21/0245 , H01L21/02532 , H01L21/0262 , H01L21/02639 , H01L29/0653 , H01L29/1054 , H01L29/78
摘要： A method of forming a channel region for a transistor includes forming a layer of silicon germanium (SiGe) above a substrate, forming an oxide layer above the SiGe layer wherein the oxide layer includes an aperture in a channel area and the aperture is filled with a SiGe feature, depositing a layer having a first thickness above the oxide layer and the SiGe feature, and forming source and drain regions in the layer.
摘要翻译：形成用于晶体管的沟道区的方法包括在衬底上形成硅锗层（SiGe），在SiGe层上形成氧化物层，其中氧化物层包括沟道区中的孔，并且孔填充有 SiGe特征，在氧化物层上沉积具有第一厚度的层和SiGe特征，以及在该层中形成源区和漏区。

9. 发明申请

US20050121731A1 Formation of abrupt junctions in devices by using silicide growth dopant snowplow effect 有权
标题翻译：通过使用硅化物生长掺杂剂积雪效应在器件中形成突变结
公开(公告)号：US20050121731A1
公开(公告)日：2005-06-09
申请号：US10727999
申请日：2003-12-03
申请人： Witold Maszara
发明人： Witold Maszara
IPC分类号： H01L21/265 , H01L21/285 , H01L21/336 , H01L29/417 , H01L29/78 , H01L29/76
CPC分类号： H01L29/78 , H01L21/2652 , H01L21/28518 , H01L29/41775 , H01L29/665 , H01L29/66628
摘要： A method of forming an abrupt junction device with a semiconductor substrate is provided. A gate dielectric is formed on a semiconductor substrate, and a gate is formed on the gate dielectric. A sidewall spacer is formed on the semiconductor substrate adjacent the gate and the gate dielectric. A thickening layer is formed by selective epitaxial growth on the semiconductor substrate adjacent the sidewall spacer. Raised source/drain dopant implanted regions are formed in at least a portion of the thickening layer. Silicide layers are formed in at least a portion of the raised source/drain dopant implanted regions to form source/drain regions, beneath the silicide layers, that are enriched with dopant from the silicide layers. A dielectric layer is deposited over the silicide layers, and contacts are then formed in the dielectric layer to the silicide layers.
摘要翻译：提供了一种形成具有半导体衬底的突点连接器件的方法。在半导体衬底上形成栅极电介质，在栅极电介质上形成栅极。在与栅极和栅极电介质相邻的半导体衬底上形成侧壁间隔物。通过在邻近侧壁间隔物的半导体衬底上选择性外延生长形成增厚层。在增稠层的至少一部分形成凸起的源/漏掺杂剂注入区。在升高的源极/漏极掺杂剂注入区域的至少一部分中形成硅化物层，以在硅化物层下面形成源极/漏极区域，其从硅化物层富集掺杂剂。在硅化物层上沉积电介质层，然后在电介质层中形成接触到硅化物层。

10. 发明授权

US06274915B1 Method of improving MOS device performance by controlling degree of depletion in the gate electrode 有权
标题翻译：通过控制栅电极的耗尽程度来提高MOS器件性能的方法
公开(公告)号：US06274915B1
公开(公告)日：2001-08-14
申请号：US09225646
申请日：1999-01-05
申请人： Srinath Krishnan , Ming-Yin Hao , David Bang , Witold Maszara
发明人： Srinath Krishnan , Ming-Yin Hao , David Bang , Witold Maszara
IPC分类号： H01L2976
CPC分类号： H01L29/4916 , H01L29/1033
摘要： A design for an MOS transistor deliberately uses depletion in a polysilicon gate electrode to improve circuit performance. Conventional transistor design seeks to minimize depletion in a polysilicon gate electrode to increase drive current. According to an embodiment of the present invention, appropriate levels of depletion in the gate electrode, larger than conventional levels, simultaneously provide desired drive current while minimizing circuit delay. According to another aspect, circuit performance is improved by adjusting doping levels in the channel region to maintain a threshold voltage at the same level as that which is achieved with minimum depletion in a polysilicon gate electrode. A method of fabricating an MOS device including a polysilicon gate electrode with increased depletion is also provided. A self-aligned doping process is used in which the polysilicon gate, the source region, and the drain region, are simultaneously implanted to dopant concentrations of between 1×1019 and 5×1019 atoms/cm3.
摘要翻译： MOS晶体管的设计故意使用多晶硅栅电极中的耗尽来改善电路性能。常规的晶体管设计旨在最小化多晶硅栅电极的耗尽以增加驱动电流。根据本发明的实施例，大于常规电平的栅电极的适当耗尽量同时提供期望的驱动电流同时最小化电路延迟。根据另一方面，通过调整沟道区域中的掺杂水平来改善电路性能，以将阈值电压维持在与多晶硅栅电极中的最小耗尽所达到的阈值电压相同的水平。还提供了一种制造包括具有增加的耗尽的多晶硅栅电极的MOS器件的方法。使用自对准掺杂工艺，其中多晶硅栅极，源极区域和漏极区域被同时注入到掺杂剂浓度为1×1019至5×1019原子/ cm3之间。

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