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1. 发明授权

US06969645B2 Method of manufacturing a semiconductor device comprising a non-volatile memory with memory cells 失效
标题翻译：包括具有存储单元的非易失性存储器的半导体器件的制造方法
公开(公告)号：US06969645B2
公开(公告)日：2005-11-29
申请号：US10482185
申请日：2002-07-03
申请人： Jurriaan Schmitz , Franciscus Petrus Widdershoven , Michiel Slotboom
发明人： Jurriaan Schmitz , Franciscus Petrus Widdershoven , Michiel Slotboom
IPC分类号： H01L21/8247 , H01L21/28 , H01L21/336 , H01L27/115 , H01L29/423 , H01L29/788 , H01L29/792 , H01L21/8238
CPC分类号： H01L21/28273 , H01L29/42328
摘要： A method of manufacturing a semiconductor device comprising a non-volatile memory with memory cells (Mij) including a select transistor (T1) with a select gate (1) and including a memory transistor (T2) with a floating gate (2) and a control gate (3). In a semiconductor body (10), active semiconductor regions are formed which are mutually insulated by field oxide regions (12). Next, the surface (11) is provided with a gate oxide layer (14) and a first layer of a conductive material wherein the select gate (1) is etched. Subsequently, the walls of the select gate extending perpendicularly to the surface are provided with an isolating material (17). The gate oxide next to the select gate is replaced by a layer of tunnel oxide (18). Next, a second layer of a conductive material (21), an interlayer dielectric (25) and a third layer of a conductive material (26) are deposited. The control gate (3) extending above and next to the select gate is formed in the third layer. Using the control gate as a mask, the floating gate (2) is subsequently etched in the second layer of conductive material. In this method, the second layer is deposited in a larger thickness than the select gate, after which this layer is planarized prior to the deposition of the interlayer dielectric and the third layer of conductive material. In this manner, a compact memory cell can be manufactured.
摘要翻译：一种制造包括非易失性存储器的半导体器件的方法，所述非易失性存储器具有包括具有选择栅极（1）并且包括具有浮置栅极（2）的存储晶体管（T 2）的选择晶体管（T 1）的存储器单元（Mij）和控制门（3）。在半导体本体（10）中，形成由场氧化物区域（12）相互绝缘的有源半导体区域。接下来，表面（11）设置有栅极氧化物层（14）和其中蚀刻选择栅极（1）的导电材料的第一层。随后，垂直于表面延伸的选择栅的壁设置有隔离材料（17）。选择栅极旁边的栅极氧化层被隧道氧化物层（18）代替。接下来，沉积第二层导电材料（21），层间电介质（25）和第三层导电材料（26）。在第三层中形成在选择栅极上方和下方延伸的控制栅极（3）。使用控制栅极作为掩模，随后在第二层导电材料中蚀刻浮栅（2）。在该方法中，第二层被沉积成比选择栅极更大的厚度，然后在沉积层间电介质和第三层导电材料之前将该层平坦化。以这种方式，可以制造紧凑的存储单元。

2. 发明授权

US06642103B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US06642103B2
公开(公告)日：2003-11-04
申请号：US09980510
申请日：2001-11-02
申请人： Nicole Anne Helena Freddy Wils , Michiel Slotboom , Franciscus Petrus Widdershoven
发明人： Nicole Anne Helena Freddy Wils , Michiel Slotboom , Franciscus Petrus Widdershoven
IPC分类号： H01L21336
CPC分类号： H01L27/11568 , H01L27/115 , H01L27/11521 , H01L29/42324 , H01L29/42328 , H01L29/66825 , H01L29/66833
摘要： A semiconductor device includes a semiconductor body (1) which is provided at a surface (2) with a non-volatile memory cell comprising a source (3) and a drain (4), and an access gate (14) which is electrically insulated from a gate structure (8) comprising a control gate (9), the gate structure (8) being electrically insulated from the semiconductor body (1) by a gate dielectric (11,25). The gate dielectric (11,25) is provided with a charge-storage region wherein data in the form of electric charge can be stored. The access gate (14) has a substantially flat surface portion (17) extending substantially parallel to the surface (2) of the semiconductor body (1) and has the shape of a block which is disposed against the gate structure (8) without overlapping the gate structure (8).
摘要翻译：半导体器件包括：半导体本体（1），其在表面（2）处设置有包括源极（3）和漏极（4）的非易失性存储单元;以及存取栅极（14），其电绝缘从包括控制栅极（9）的栅极结构（8），栅极结构（8）通过栅极电介质（11,25）与半导体本体（1）电绝缘。栅极电介质（11,25）设置有电荷存储区域，其中可以存储电荷形式的数据。进入门（14）具有基本上平行于半导体本体（1）的表面（2）延伸的基本平坦的表面部分（17），并且具有块状形状，该块形状抵靠栅极结构（8）而不重叠门结构（8）。

3. 发明授权

US06991982B2 Method of manufacturing a semiconductor non-volatile memory 失效
标题翻译：制造半导体非易失性存储器的方法
公开(公告)号：US06991982B2
公开(公告)日：2006-01-31
申请号：US10514022
申请日：2003-05-05
申请人： Robertus Theodorus Fransiscus Van Schaijk , Michiel Slotboom
发明人： Robertus Theodorus Fransiscus Van Schaijk , Michiel Slotboom
IPC分类号： H01L21/336
CPC分类号： H01L27/11521 , H01L21/28273 , H01L27/115 , H01L29/42324
摘要： A method of manufacturing a semiconductor device comprising a non-volatile memory with memory transistors and selection transistors. In this method a semiconductor body is provided with strip-shaped active regions (4) which are mutually isolated by field-oxide regions (3 of 4). On the surface (2) a first system of conductors 11 is then formed which are directed perpendicularly to the active regions and are covered by an insulating layer (12), charge storage regions (13) being formed below these conductors, at the location where these conductors and the active regions cross each other. These conductors form word lines of the memory and, at the location where said conductors and the active regions cross each other, they form control gates. Next, a conductive layer (16) is deposited and planarized. The planarized conductive layer (16) is then provided with an etch mask with strips directed perpendicularly to the active regions, which strips extend above and next to the conductors (11). Then a second system of conductors (19) is etched in the planarized conductive layer. The planarized layer here covers the conductors (11) with the insulating top layer (12) completely, so that the conductors (19) of the second system extend above the conductors (11) of the first system. Thus a very compact memory can be produced, enabling data written in the memory to be read out in very short times.
摘要翻译：一种制造半导体器件的方法，包括具有存储晶体管和选择晶体管的非易失性存储器。在这种方法中，半导体本体设置有由场氧化物区域（3/4）相互隔离的带状有源区域（4）。在表面（2）上，形成垂直于有源区域的导体11的第一系统，并被绝缘层（12）覆盖，电荷存储区域（13）形成在这些导体的下面，这些导体和有源区域彼此交叉。这些导体形成存储器的字线，并且在所述导体和有源区域彼此交叉的位置处，它们形成控制栅极。接下来，沉积并平坦化导电层（16）。然后，平坦化的导电层（16）设置有具有垂直于有源区域的条带的蚀刻掩模，该条带在导体（11）的上方和下方延伸。然后在平坦化的导电层中蚀刻第二导体系统（19）。这里的平坦化层覆盖绝缘顶层（12）完全的导体（11），使得第二系统的导体（19）在第一系统的导体（11）的上方延伸。因此，可以产生非常紧凑的存储器，使得能够在非常短的时间内读出写在存储器中的数据。

4. 发明申请

US20090179254A1 Memory Device With Improved Performance And Method Of Manufacturing Such A Memory Device 审中-公开
标题翻译：具有改进性能的存储器件和制造这样的存储器件的方法
公开(公告)号：US20090179254A1
公开(公告)日：2009-07-16
申请号：US12067491
申请日：2006-09-13
申请人： Robertus Theodorus Franciscus Van Schaijk , Pablo Garcia Tello , Michiel Slotboom
发明人： Robertus Theodorus Franciscus Van Schaijk , Pablo Garcia Tello , Michiel Slotboom
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L29/1054 , G11C16/14 , H01L29/66833 , H01L29/7843 , H01L29/7848 , H01L29/792
摘要： Non-volatile memory device on a semiconductor substrate, comprising a semiconductor base layer, a charge storage layer stack, and a control gate; the base layer comprising source and drain regions and a current-carrying channel region being positioned in between the source and drain regions; the charge storage layer stack comprising a first insulating layer, a charge trapping layer and a second insulating layer, the first insulating layer being positioned above the current-carrying channel region, the charge trapping layer being above the first insulating layer and the second insulating layer being above the charge trapping layer; the control gate being positioned above the charge storage layer stack; the charge storage layer stack being arranged for trapping charge in the charge trapping layer by direct tunneling of charge carriers from the current-carrying channel region through the first insulating layer, wherein the current-carrying channel region is a p-type channel for p-type charge carriers, and the material of at least one of the current-carrying channel region and/or the source and drain regions is in an elastically strained state.
摘要翻译：半导体基板上的非易失性存储器件，包括半导体基底层，电荷存储层堆叠和控制栅极; 所述基极层包括源极和漏极区域，并且载流通道区域位于所述源极和漏极区域之间; 所述电荷存储层堆叠包括第一绝缘层，电荷捕获层和第二绝缘层，所述第一绝缘层位于所述载流通道区域的上方，所述电荷捕获层位于所述第一绝缘层之上，所述第二绝缘层位于电荷捕获层之上; 控制栅极位于电荷存储层堆叠之上; 电荷存储层堆叠被布置用于通过从载流通道区域穿过第一绝缘层直接隧穿隧穿电荷来俘获电荷俘获层，其中载流通道区域是p型沟道，并且载流通道区域和/或源极和漏极区域中的至少一个的材料处于弹性应变状态。

5. 发明授权

US07443725B2 Floating gate isolation and method of making the same 失效
标题翻译：浮闸隔离及其制作方法
公开(公告)号：US07443725B2
公开(公告)日：2008-10-28
申请号：US10542833
申请日：2003-12-16
申请人： Robertus Theodorus Fransiscus Van Schaijk , Michiel Slotboom
发明人： Robertus Theodorus Fransiscus Van Schaijk , Michiel Slotboom
IPC分类号： G11C16/04 , H01L29/788 , H01L21/336
CPC分类号： H01L21/28273 , H01L27/115 , H01L27/11521 , H01L29/7881
摘要： The present invention relates to a method for forming a set of floating gates which are isolated from each other by means of slits, as well as semiconductor devices using the floating gate. The present invention provides a method for manufacturing an array of semiconductor devices on a substrate (10), each device having a floating gate (36), comprising: first forming isolation zones (14) in the substrate (10), thereafter forming a floating gate separator (32) on the isolation zones (14) at locations where separations between adjacent floating gates (36) are to be formed, after forming the floating gate separator (32), forming the floating gates (36) on the substrate (10) between parts of the floating gate separator (32), and thereafter removing the floating gate separator (32) so as to obtain slits in between neighboring floating gates (36). This method has an advantage over prior art in that less residues of floating gate material, or less floating gate material shorts between adjacent floating gates occur. Furthermore, the gate profile is damaged less than in prior art slit processing methods.
摘要翻译：本发明涉及用于形成通过狭缝彼此隔离的一组浮置栅极的方法，以及使用该浮栅的半导体器件。本发明提供了一种用于在衬底（10）上制造半导体器件阵列的方法，每个器件具有浮置栅极（36），包括：首先在衬底（10）中形成隔离区（14），之后形成浮置在形成浮栅分离器（32）之后，在形成浮动栅极（36）之间的位置的位置处，在隔离区（14）上的隔离区（14）上形成栅极分离器（32），在基板），然后移除浮动分离器（32），以便在相邻的浮动栅极（36）之间获得狭缝。该方法相对于现有技术具有优点，因为浮栅之间的较少残留物或较少浮置栅极材料在相邻浮栅之间短路。此外，栅极轮廓比现有技术的狭缝加工方法损坏少。

6. 发明申请

US20070034936A1 Two-transistor memory cell and method for manufacturing 审中-公开
标题翻译：双晶体管存储单元及制造方法
公开(公告)号：US20070034936A1
公开(公告)日：2007-02-15
申请号：US10574030
申请日：2004-09-20
申请人： Robertus Theodorus Van Schaijk , Michiel Slotboom
发明人： Robertus Theodorus Van Schaijk , Michiel Slotboom
IPC分类号： H01L29/788
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/40114 , H01L29/42328 , H01L29/66825 , H01L29/7883
摘要： The present invention provides a method of manufacturing on a substrate (50) a 2-transistor memory cell comprising a storage transistor (1) having a memory gate stack (1) and a selecting transistor, there being a tunnel dielectric layer (51) between the substrate (50) and the memory gate stack. (1). The method comprises forming the memory gate stack (1) by providing a first conductive layer (52) and a second conductive layer (54) and etching the second conductive layer (54) thus forming a control gate and etching the first conductive layer (52) thus forming a floating gate. The method is characterized in that it comprises, before etching the first conductive layer (52), forming spacers (81) against the control gate in the direction of a channel to be formed under the tunnel dielectric layer (51), and thereafter using the spacers (81) as a hard mask to etch the first conductive layer (52) thus forming the floating gate, thus making the floating gate self aligned with the control gate. The present invention also provides a memory cell wherein the control gate (54) is smaller than the floating gate (52), and spacers (81) are present next to the control gate (54).
摘要翻译：本发明提供了一种在基板（50）上制造包括具有存储栅叠层（1）和选择晶体管的存储晶体管（1）的二晶体管存储单元的方法，所述晶体管存在一个隧道介电层（51）基板（50）和存储器栅极堆叠。（1）。该方法包括通过提供第一导电层（52）和第二导电层（54）形成存储器栅极叠层（1）并蚀刻第二导电层（54）从而形成控制栅极并蚀刻第一导电层（52 ），从而形成浮动门。该方法的特征在于，在蚀刻第一导电层（52）之前，其包括在要形成在隧道介电层（51）下方的沟道的方向上在控制栅极上形成间隔物（81），然后使用间隔物（81）作为硬掩模，以蚀刻由此形成浮置栅极的第一导电层（52），从而使浮动栅极与控制栅极自对准。本发明还提供了一种存储单元，其中控制栅极（54）小于浮动栅极（52），并且间隔物（81）紧邻控制栅极（54）存在。

7. 发明申请

US20060237769A1 Floating gate isolation and method of making the same 失效
标题翻译：浮闸隔离及其制作方法
公开(公告)号：US20060237769A1
公开(公告)日：2006-10-26
申请号：US10542833
申请日：2003-12-16
申请人： Robertus Van Schaijk , Michiel Slotboom
发明人： Robertus Van Schaijk , Michiel Slotboom
IPC分类号： H01L29/788 , H01L21/8238
CPC分类号： H01L21/28273 , H01L27/115 , H01L27/11521 , H01L29/7881
摘要： The present invention relates to a method for forming a set of floating gates which are isolated from each other by means of slits, as well as semiconductor devices using the floating gate. The present invention provides a method for manufacturing an array of semiconductor devices on a substrate (10), each device having a floating gate (36), comprising: first forming isolation zones (14) in the substrate (10), thereafter forming a floating gate separator (32) on the isolation zones (14) at locations where separations between adjacent floating gates (36) are to be formed, after forming the floating gate separator (32), forming the floating gates (36) on the substrate (10) between parts of the floating gate separator (32), and thereafter removing the floating gate separator (32) so as to obtain slits in between neighboring floating gates (36). This method has an advantage over prior art in that less residues of floating gate material, or less floating gate material shorts between adjacent floating gates occur. Furthermore, the gate profile is damaged less than in prior art slit processing methods.
摘要翻译：本发明涉及用于形成通过狭缝彼此隔离的一组浮置栅极的方法，以及使用该浮栅的半导体器件。本发明提供了一种用于在衬底（10）上制造半导体器件阵列的方法，每个器件具有浮置栅极（36），包括：首先在衬底（10）中形成隔离区（14），之后形成浮置在形成浮栅分离器（32）之后，在形成浮动栅极（36）之间的位置的位置处，在隔离区（14）上的隔离区（14）上形成栅极分离器（32），在基板），然后移除浮动分离器（32），以便在相邻的浮动栅极（36）之间获得狭缝。该方法相对于现有技术具有优点，因为浮栅之间的较少残留物或较少浮置栅极材料在相邻浮栅之间短路。此外，栅极轮廓比现有技术的狭缝加工方法损坏少。

8. 发明授权

US06885058B2 Semiconductor device and method of manufacturing such a semiconductor device 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US06885058B2
公开(公告)日：2005-04-26
申请号：US10462846
申请日：2003-06-16
申请人： Nicole Anne Helena Freddy Wils , Michiel Slotboom , Franciscus Petrus Widdershoven
发明人： Nicole Anne Helena Freddy Wils , Michiel Slotboom , Franciscus Petrus Widdershoven
IPC分类号： H01L21/28 , H01L21/336 , H01L21/8246 , H01L21/8247 , H01L27/10 , H01L27/115 , H01L29/41 , H01L29/423 , H01L29/49 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11568 , H01L27/115 , H01L27/11521 , H01L29/42324 , H01L29/42328 , H01L29/66825 , H01L29/66833
摘要： A semiconductor device includes a semiconductor body (1) which is provided at a surface (2) with a non-volatile memory cell comprising a source (3) and a drain (4), and an access gate (14) which is electrically insulated from a gate structure (8) comprising a control gate (9), the gate structure (8) being electrically insulated from the semiconductor body (1) by a gate dielectric (11, 25). The gate dielectric (11, 25) is provided with a charge-storage region wherein data in the form of electric charge can be stored. The access gate (14) has a substantially flat surface portion (17) extending substantially parallel to the surface (2) of the semiconductor body (1) and has the shape of a block which is disposed against the gate structure (8) without overlapping the gate structure.
摘要翻译：半导体器件包括：半导体本体（1），其在表面（2）处设置有包括源极（3）和漏极（4）的非易失性存储单元;以及存取栅极（14），其电绝缘从包括控制栅极（9）的栅极结构（8），栅极结构（8）通过栅极电介质（11,25）与半导体本体（1）电绝缘。栅极电介质（11,25）设置有电荷存储区域，其中可以存储电荷形式的数据。进入门（14）具有基本上平行于半导体本体（1）的表面（2）延伸的基本平坦的表面部分（17），并且具有块状形状，该块形状抵靠栅极结构（8）而不重叠门结构。

9. 发明授权

US06984558B2 Method of manufacturing a semiconductor device with non-volatile memory comprising a memory cell with an access gate and with a control gate and a charge storage region 失效
标题翻译：制造具有非易失性存储器的半导体器件的方法，包括具有存取栅极的存储单元以及控制栅极和电荷存储区域
公开(公告)号：US06984558B2
公开(公告)日：2006-01-10
申请号：US10485496
申请日：2002-06-04
申请人： Michiel Slotboom , Franciscus Petrus Widdershoven
发明人： Michiel Slotboom , Franciscus Petrus Widdershoven
IPC分类号： H01L21/336
CPC分类号： H01L27/11568 , H01L21/28273 , H01L27/11521 , H01L29/42328 , H01L29/66825 , H01L29/7883
摘要： Method of manufacturing a semiconductor device comprising a semiconductor body (1) which is provided at a surface (2) with a non-volatile memory comprising a memory cell with a gate structure (4) with an access gate (19) and a gate structure (3) with a control gate (5) and a charge storage region situated between the control gate (5) and the semiconductor body (1), such as a floating gate (6). In this method on the surface (2) of the semiconductor body (1) a first one of said gate structures is formed with side walls (10) extending substantially perpendicular to the surface, a conductive layer is deposited (13) on and next to said first gate-structure, the conductive layer is subjected to a planarizing treatment until the first gate structure is exposed and the so planarized conductive layer is patterned so as to form at least a part of the other gate structure adjoining the first gate structure. Said patterning of the planarized conductive layer is performed in that the planarized conductive layer (14) is etched back so as to expose an upper portion (15) of the side walls of the first gate structure, a spacer (18) is formed on the exposed upper portion (15) of the side walls of first gate structure and the conductive layer (16) is etched anisotropically using the spacer as a mask. Thus very small memory cells can be realized.
摘要翻译：一种制造半导体器件的方法，包括：半导体本体（1），其在表面（2）处设置有非易失性存储器，所述非易失性存储器包括具有栅极结构（4）的存储单元，所述存储单元具有存取栅极（19）和栅极结构（5）和位于控制栅极（5）和半导体本体（1）之间的电荷存储区域（例如浮动栅极）。在这种方法中，在半导体本体（1）的表面（2）上，第一个所述栅极结构形成有大致垂直于所述表面延伸的侧壁（10），导电层被沉积（13）所述第一栅极结构，对导电层进行平坦化处理，直到第一栅极结构暴露，并且将如此平坦化的导电层图案化，以形成与第一栅极结构相邻的另一栅极结构的至少一部分。平面化导电层的所述图案化是以平坦化的导电层（14）被回蚀以便露出第一栅极结构的侧壁的上部（15）来实现的，间隔物（18）形成在使用间隔物作为掩模，各向异性地蚀刻第一栅极结构的侧壁的暴露的上部（15）和导电层（16）。因此，可以实现非常小的存储单元。

10. 发明申请

US20050207209A1 Method of manufacturing a semiconductor non-volatiel memory 失效
标题翻译：制造半导体非易失性存储器的方法
公开(公告)号：US20050207209A1
公开(公告)日：2005-09-22
申请号：US10514022
申请日：2003-05-05
申请人： Robertus Theodorus Van Schaijk , Michiel Slotboom
发明人： Robertus Theodorus Van Schaijk , Michiel Slotboom
IPC分类号： H01L21/28 , H01L21/8246 , H01L21/8247 , H01L27/105 , H01L27/115 , H01L29/423 , H01L29/788 , H01L29/792 , G11C11/00
CPC分类号： H01L27/11521 , H01L21/28273 , H01L27/115 , H01L29/42324
摘要： A method of manufacturing a semiconductor device comprising a non-volatile memory with memory transistors and selection transistors. In this method a semiconductor body is provided with strip-shaped active regions (4) which are mutually isolated by field-oxide regions (3 of 4). On the surface (2) a first system of conductors 11 is then formed which are directed perpendicularly to the active regions and are covered by an insulating layer (12), charge storage regions (13) being formed below these conductors, at the location where these conductors and the active regions cross each other. These conductors form word lines of the memory and, at the location where said conductors and the active regions cross each other, they form control gates. Next, a conductive layer (16) is deposited and planarized. The planarized conductive layer (16) is then provided with an etch mask with strips directed perpendicularly to the active regions, which strips extend above and next to the conductors (11). Then a second system of conductors (19) is etched in the planarized conductive layer. The planarized layer here covers the conductors (11) with the insulating top layer (12) completely, so that the conductors (19) of the second system extend above the conductors (11) of the first system. Thus a very compact memory can be produced, enabling data written in the memory to be read out in very short times.
摘要翻译：一种制造半导体器件的方法，包括具有存储晶体管和选择晶体管的非易失性存储器。在这种方法中，半导体本体设置有由场氧化物区域（3/4）相互隔离的带状有源区域（4）。在表面（2）上，形成垂直于有源区域的导体11的第一系统，并被绝缘层（12）覆盖，电荷存储区域（13）形成在这些导体的下面，这些导体和有源区域彼此交叉。这些导体形成存储器的字线，并且在所述导体和有源区域彼此交叉的位置处，它们形成控制栅极。接下来，沉积并平坦化导电层（16）。然后，平坦化的导电层（16）设置有具有垂直于有源区域的条带的蚀刻掩模，该条带在导体（11）的上方和下方延伸。然后在平坦化的导电层中蚀刻第二导体系统（19）。这里的平坦化层覆盖绝缘顶层（12）完全的导体（11），使得第二系统的导体（19）在第一系统的导体（11）的上方延伸。因此，可以产生非常紧凑的存储器，使得能够在非常短的时间内读出写在存储器中的数据。

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