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1. 发明授权

US06885058B2 Semiconductor device and method of manufacturing such a semiconductor device 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US06885058B2
公开(公告)日：2005-04-26
申请号：US10462846
申请日：2003-06-16
申请人： Nicole Anne Helena Freddy Wils , Michiel Slotboom , Franciscus Petrus Widdershoven
发明人： Nicole Anne Helena Freddy Wils , Michiel Slotboom , Franciscus Petrus Widdershoven
IPC分类号： H01L21/28 , H01L21/336 , H01L21/8246 , H01L21/8247 , H01L27/10 , H01L27/115 , H01L29/41 , H01L29/423 , H01L29/49 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11568 , H01L27/115 , H01L27/11521 , H01L29/42324 , H01L29/42328 , H01L29/66825 , H01L29/66833
摘要： A semiconductor device includes a semiconductor body (1) which is provided at a surface (2) with a non-volatile memory cell comprising a source (3) and a drain (4), and an access gate (14) which is electrically insulated from a gate structure (8) comprising a control gate (9), the gate structure (8) being electrically insulated from the semiconductor body (1) by a gate dielectric (11, 25). The gate dielectric (11, 25) is provided with a charge-storage region wherein data in the form of electric charge can be stored. The access gate (14) has a substantially flat surface portion (17) extending substantially parallel to the surface (2) of the semiconductor body (1) and has the shape of a block which is disposed against the gate structure (8) without overlapping the gate structure.
摘要翻译：半导体器件包括：半导体本体（1），其在表面（2）处设置有包括源极（3）和漏极（4）的非易失性存储单元;以及存取栅极（14），其电绝缘从包括控制栅极（9）的栅极结构（8），栅极结构（8）通过栅极电介质（11,25）与半导体本体（1）电绝缘。栅极电介质（11,25）设置有电荷存储区域，其中可以存储电荷形式的数据。进入门（14）具有基本上平行于半导体本体（1）的表面（2）延伸的基本平坦的表面部分（17），并且具有块状形状，该块形状抵靠栅极结构（8）而不重叠门结构。

2. 发明授权

US06642103B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US06642103B2
公开(公告)日：2003-11-04
申请号：US09980510
申请日：2001-11-02
申请人： Nicole Anne Helena Freddy Wils , Michiel Slotboom , Franciscus Petrus Widdershoven
发明人： Nicole Anne Helena Freddy Wils , Michiel Slotboom , Franciscus Petrus Widdershoven
IPC分类号： H01L21336
CPC分类号： H01L27/11568 , H01L27/115 , H01L27/11521 , H01L29/42324 , H01L29/42328 , H01L29/66825 , H01L29/66833
摘要： A semiconductor device includes a semiconductor body (1) which is provided at a surface (2) with a non-volatile memory cell comprising a source (3) and a drain (4), and an access gate (14) which is electrically insulated from a gate structure (8) comprising a control gate (9), the gate structure (8) being electrically insulated from the semiconductor body (1) by a gate dielectric (11,25). The gate dielectric (11,25) is provided with a charge-storage region wherein data in the form of electric charge can be stored. The access gate (14) has a substantially flat surface portion (17) extending substantially parallel to the surface (2) of the semiconductor body (1) and has the shape of a block which is disposed against the gate structure (8) without overlapping the gate structure (8).
摘要翻译：半导体器件包括：半导体本体（1），其在表面（2）处设置有包括源极（3）和漏极（4）的非易失性存储单元;以及存取栅极（14），其电绝缘从包括控制栅极（9）的栅极结构（8），栅极结构（8）通过栅极电介质（11,25）与半导体本体（1）电绝缘。栅极电介质（11,25）设置有电荷存储区域，其中可以存储电荷形式的数据。进入门（14）具有基本上平行于半导体本体（1）的表面（2）延伸的基本平坦的表面部分（17），并且具有块状形状，该块形状抵靠栅极结构（8）而不重叠门结构（8）。

3. 发明授权

US06969645B2 Method of manufacturing a semiconductor device comprising a non-volatile memory with memory cells 失效
标题翻译：包括具有存储单元的非易失性存储器的半导体器件的制造方法
公开(公告)号：US06969645B2
公开(公告)日：2005-11-29
申请号：US10482185
申请日：2002-07-03
申请人： Jurriaan Schmitz , Franciscus Petrus Widdershoven , Michiel Slotboom
发明人： Jurriaan Schmitz , Franciscus Petrus Widdershoven , Michiel Slotboom
IPC分类号： H01L21/8247 , H01L21/28 , H01L21/336 , H01L27/115 , H01L29/423 , H01L29/788 , H01L29/792 , H01L21/8238
CPC分类号： H01L21/28273 , H01L29/42328
摘要： A method of manufacturing a semiconductor device comprising a non-volatile memory with memory cells (Mij) including a select transistor (T1) with a select gate (1) and including a memory transistor (T2) with a floating gate (2) and a control gate (3). In a semiconductor body (10), active semiconductor regions are formed which are mutually insulated by field oxide regions (12). Next, the surface (11) is provided with a gate oxide layer (14) and a first layer of a conductive material wherein the select gate (1) is etched. Subsequently, the walls of the select gate extending perpendicularly to the surface are provided with an isolating material (17). The gate oxide next to the select gate is replaced by a layer of tunnel oxide (18). Next, a second layer of a conductive material (21), an interlayer dielectric (25) and a third layer of a conductive material (26) are deposited. The control gate (3) extending above and next to the select gate is formed in the third layer. Using the control gate as a mask, the floating gate (2) is subsequently etched in the second layer of conductive material. In this method, the second layer is deposited in a larger thickness than the select gate, after which this layer is planarized prior to the deposition of the interlayer dielectric and the third layer of conductive material. In this manner, a compact memory cell can be manufactured.
摘要翻译：一种制造包括非易失性存储器的半导体器件的方法，所述非易失性存储器具有包括具有选择栅极（1）并且包括具有浮置栅极（2）的存储晶体管（T 2）的选择晶体管（T 1）的存储器单元（Mij）和控制门（3）。在半导体本体（10）中，形成由场氧化物区域（12）相互绝缘的有源半导体区域。接下来，表面（11）设置有栅极氧化物层（14）和其中蚀刻选择栅极（1）的导电材料的第一层。随后，垂直于表面延伸的选择栅的壁设置有隔离材料（17）。选择栅极旁边的栅极氧化层被隧道氧化物层（18）代替。接下来，沉积第二层导电材料（21），层间电介质（25）和第三层导电材料（26）。在第三层中形成在选择栅极上方和下方延伸的控制栅极（3）。使用控制栅极作为掩模，随后在第二层导电材料中蚀刻浮栅（2）。在该方法中，第二层被沉积成比选择栅极更大的厚度，然后在沉积层间电介质和第三层导电材料之前将该层平坦化。以这种方式，可以制造紧凑的存储单元。

4. 发明授权

US06984558B2 Method of manufacturing a semiconductor device with non-volatile memory comprising a memory cell with an access gate and with a control gate and a charge storage region 失效
标题翻译：制造具有非易失性存储器的半导体器件的方法，包括具有存取栅极的存储单元以及控制栅极和电荷存储区域
公开(公告)号：US06984558B2
公开(公告)日：2006-01-10
申请号：US10485496
申请日：2002-06-04
申请人： Michiel Slotboom , Franciscus Petrus Widdershoven
发明人： Michiel Slotboom , Franciscus Petrus Widdershoven
IPC分类号： H01L21/336
CPC分类号： H01L27/11568 , H01L21/28273 , H01L27/11521 , H01L29/42328 , H01L29/66825 , H01L29/7883
摘要： Method of manufacturing a semiconductor device comprising a semiconductor body (1) which is provided at a surface (2) with a non-volatile memory comprising a memory cell with a gate structure (4) with an access gate (19) and a gate structure (3) with a control gate (5) and a charge storage region situated between the control gate (5) and the semiconductor body (1), such as a floating gate (6). In this method on the surface (2) of the semiconductor body (1) a first one of said gate structures is formed with side walls (10) extending substantially perpendicular to the surface, a conductive layer is deposited (13) on and next to said first gate-structure, the conductive layer is subjected to a planarizing treatment until the first gate structure is exposed and the so planarized conductive layer is patterned so as to form at least a part of the other gate structure adjoining the first gate structure. Said patterning of the planarized conductive layer is performed in that the planarized conductive layer (14) is etched back so as to expose an upper portion (15) of the side walls of the first gate structure, a spacer (18) is formed on the exposed upper portion (15) of the side walls of first gate structure and the conductive layer (16) is etched anisotropically using the spacer as a mask. Thus very small memory cells can be realized.
摘要翻译：一种制造半导体器件的方法，包括：半导体本体（1），其在表面（2）处设置有非易失性存储器，所述非易失性存储器包括具有栅极结构（4）的存储单元，所述存储单元具有存取栅极（19）和栅极结构（5）和位于控制栅极（5）和半导体本体（1）之间的电荷存储区域（例如浮动栅极）。在这种方法中，在半导体本体（1）的表面（2）上，第一个所述栅极结构形成有大致垂直于所述表面延伸的侧壁（10），导电层被沉积（13）所述第一栅极结构，对导电层进行平坦化处理，直到第一栅极结构暴露，并且将如此平坦化的导电层图案化，以形成与第一栅极结构相邻的另一栅极结构的至少一部分。平面化导电层的所述图案化是以平坦化的导电层（14）被回蚀以便露出第一栅极结构的侧壁的上部（15）来实现的，间隔物（18）形成在使用间隔物作为掩模，各向异性地蚀刻第一栅极结构的侧壁的暴露的上部（15）和导电层（16）。因此，可以实现非常小的存储单元。

5. 发明授权

US06980472B2 Device and method to read a 2-transistor flash memory cell 有权
标题翻译：读取2晶体管闪存单元的器件和方法
公开(公告)号：US06980472B2
公开(公告)日：2005-12-27
申请号：US10498449
申请日：2002-12-05
申请人： Anthonie Meindert Herman Ditewig , Franciscus Petrus Widdershoven , Roger Cuppens
发明人： Anthonie Meindert Herman Ditewig , Franciscus Petrus Widdershoven , Roger Cuppens
IPC分类号： G11C16/06 , G11C5/00 , G11C16/02 , G11C16/04 , G11C16/26 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： G11C16/26
摘要： The present invention relates to electronic memories, more particularly to an improved method and apparatus to read the content of compact 2-transistor flash memory cells.A method of reading a 2-transistor flash memory cell 1 is provided. The memory cell 1 comprises a storage transistor 2 with a storage gate 6 and a selecting transistor 3 with a select gate 7. The method comprises leaving the storage gate 6 floating while the select gate 7 is switched from a first voltage to a second voltage, whereby the first voltage is lower than the second voltage.A device according to the present invention comprises a switching circuit for leaving the storage gate 6 floating while the select gate 7 is switched from the first voltage to the second voltage, the first voltage being lower than the second voltage.
摘要翻译：本发明涉及电子存储器，更具体地说，涉及一种读取紧凑型2-晶体管闪存单元的内容的改进方法和装置。提供读取2晶体管闪存单元1的方法。存储单元1包括具有存储栅极6的存储晶体管2和具有选择栅极7的选择晶体管3。该方法包括在选择栅极7从第一电压切换到第二电压的同时使存储栅极6浮动，由此第一电压低于第二电压。根据本发明的装置包括用于在选择栅极7从第一电压切换到第二电压时使存储栅极6离开的开关电路，第一电压低于第二电压。

6. 发明授权

US07741182B2 Method of fabricating a dual gate FET 有权
标题翻译：制造双栅极FET的方法
公开(公告)号：US07741182B2
公开(公告)日：2010-06-22
申请号：US11815100
申请日：2006-01-23
申请人： Wibo Daniel Van Noort , Franciscus Petrus Widdershoven , Radu Surdeanu
发明人： Wibo Daniel Van Noort , Franciscus Petrus Widdershoven , Radu Surdeanu
IPC分类号： H01L21/336
CPC分类号： H01L29/785 , H01L29/66795 , H01L29/7854
摘要： The invention provides a method of fabricating an extremely short-length dual-gate FET, using conventional semi-conductor processing techniques, with extremely small and reproducible fins with a pitch and a width that are both smaller than can be obtained with photolithographic techniques. On a protrusion (2) on a substrate (1), a first layer (3) and a second layer (4) are formed, after which the top surface of the protrusion (2) is exposed. A portion of the first layer (3) is selectively removed relative to the protrusion (2) and the second layer (4), thereby creating a fin (6) and a trench (5). Also a method is presented to form a plurality of fins (6) and trenches (5). The dual-gate FET is created by forming a gate electrode (7) in the trench(es) (5) and a source and drain region. Further a method is presented to fabricate an extremely short-length asymmetric dual-gate FET with two gate electrodes that can be biased separately.
摘要翻译：本发明提供了一种使用常规半导体处理技术制造极短的双栅极FET的方法，其具有非常小且可重现的鳍，其间距和宽度都小于可以用光刻技术获得的。在基板（1）上的突起（2）上形成第一层（3）和第二层（4），然后露出突起（2）的上表面。相对于突起（2）和第二层（4），第一层（3）的一部分被选择性地去除，从而形成翅片（6）和沟槽（5）。还提出了形成多个翅片（6）和沟槽（5）的方法。通过在沟槽（5）中形成栅电极（7）和源极和漏极区域来产生双栅极FET。此外，提出了一种制造具有可分别偏置的两个栅电极的极短的非对称双栅极FET的方法。

7. 发明申请

US20080285333A1 Electric Device Comprising Phase Change Material 有权
标题翻译：包括相变材料的电气设备
公开(公告)号：US20080285333A1
公开(公告)日：2008-11-20
申请号：US10599270
申请日：2005-03-16
申请人： Martijn Henri Richard Lankhorst , Erwin Rinaldo Meinders , Robertus Adrianus Maria Wolters , Franciscus Petrus Widdershoven
发明人： Martijn Henri Richard Lankhorst , Erwin Rinaldo Meinders , Robertus Adrianus Maria Wolters , Franciscus Petrus Widdershoven
IPC分类号： G11C11/00
CPC分类号： G11C11/56 , G11C11/5678 , G11C13/0004 , H01L27/2436 , H01L27/2463 , H01L45/06 , H01L45/1226 , H01L45/124 , H01L45/1286 , H01L45/148 , H01L45/1675 , H01L45/1691
摘要： The electric device (100) according to the invention has a resistor comprising a layer (7, 107) of a phase change material which is changeable between a first phase with a first electrical resistivity and a second phase with a second electrical resistivity different from the first electrical resistivity. The phase change material is a fast growth material. The electric device (100) further comprises a switching signal generator (400) for switching the resistor between at least three different electrical resistance values by changing a corresponding portion of the layer (7, 107) of the phase change material from the first phase to the second phase.
摘要翻译：根据本发明的电子设备（100）具有电阻器，该电阻器包括相变材料的层（7,107），所述相变材料层可在具有第一电阻率的第一相和第二相之间变化，所述第二相具有不同于第一电阻率。相变材料是快速生长材料。电气设备（100）还包括切换信号发生器（400），用于通过将相变材料的层（7,107）的相对应部分从第一阶段改变为至少三个不同的电阻值来切换电阻器第二阶段

8. 发明授权

US06559711B2 Circuit for providing a constant current 有权
公开(公告)号：US06559711B2
公开(公告)日：2003-05-06
申请号：US09902219
申请日：2001-07-10
申请人： Franciscus Petrus Widdershoven , Anne Johan Annema
发明人： Franciscus Petrus Widdershoven , Anne Johan Annema
IPC分类号： G05F110
CPC分类号： G05F3/30
摘要： Two substantially identical currents (I1,a, I1,b) are subtracted from each other, while being generated by elements (10, 11) in such a way that noise in the current value of said two currents (I1,a, I1,b) is determined by shot noise. The differential current, determined only by shot noise, is supplied to a capacitor (13). A second current (I2) is used to charge a second capacitor (22, 29). It is periodically determined whether the value of a voltage across the first capacitor (13) is within or outside a range bounded by the (negative and positive values of the) voltage of the second capacitor (22, 29) which has been charged over the same period of time. The currents (I1,b, Ib) are set in dependence on the result of the comparison. The signal to set the currents (I1,b, Ib) also serves as control signal for an element (43) connected as a constant current source. The setting signal and thus the constant current (I0) delivered by the element (43) connected as a current source is to a high degree independent of the temperature sensitivity of different components of the circuit and is determined essentially solely by the ratio of values of similar components (10, 11, 20, 27, 43) of the circuit. By choosing components whose ratio appears in a value of the constant current (I0) delivered by the circuit and which have the same temperature dependence, it is achieved that the temperature dependence disappears completely or substantially completely from the constant current (I0) delivered by the circuit.

9. 发明授权

US08115239B2 Electric device comprising phase change material 有权
标题翻译：包含相变材料的电气装置
公开(公告)号：US08115239B2
公开(公告)日：2012-02-14
申请号：US10599270
申请日：2005-03-16
申请人： Martijn Henri Richard Lankhorst , Erwin Rinaldo Meinders , Robertus Adrianus Maria Wolters , Franciscus Petrus Widdershoven
发明人： Martijn Henri Richard Lankhorst , Erwin Rinaldo Meinders , Robertus Adrianus Maria Wolters , Franciscus Petrus Widdershoven
IPC分类号： H01L29/76
CPC分类号： G11C11/56 , G11C11/5678 , G11C13/0004 , H01L27/2436 , H01L27/2463 , H01L45/06 , H01L45/1226 , H01L45/124 , H01L45/1286 , H01L45/148 , H01L45/1675 , H01L45/1691
摘要： The electric device according to the invention has a resistor comprising a layer of a phase change material which is changeable between a first phase with a first electrical resistivity and a second phase with a second electrical resistivity different from the first electrical resistivity. The phase change material is a fast growth material. The electric device further comprises a switching signal generator for switching the resistor between at least three different electrical resistance values by changing a corresponding portion of the layer of the phase change material from the first phase to the second phase.
摘要翻译：根据本发明的电子装置具有电阻器，该电阻器包括相变材料层，所述相变材料层可以在具有第一电阻率的第一相位和具有不同于第一电阻率的第二电阻率的第二相位之间变化。相变材料是快速生长材料。电子装置还包括切换信号发生器，用于通过将相变材料层的相应部分从第一阶段改变到第二阶段来在至少三个不同的电阻值之间切换电阻器。

10. 发明申请

US20100314699A1 ELECTROCHEMICAL SENSOR DEVICE, METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：电化学传感器装置，其制造方法
公开(公告)号：US20100314699A1
公开(公告)日：2010-12-16
申请号：US12517858
申请日：2007-12-07
申请人： Mohammed Meftah , Franciscus Petrus Widdershoven
发明人： Mohammed Meftah , Franciscus Petrus Widdershoven
IPC分类号： H01L29/66 , H01L21/50
CPC分类号： H01L24/73 , G01N27/414 , G01N33/5438 , H01L2924/13091 , H01L2924/00
摘要： An electrochemical sensor device (100) for analysing a sample, the device (100) comprising an electronic chip (101) comprising a sensor portion (102) being sensitive for particles of the sample, a carrier element (103, 104) bonded to the electronic chip (101) to define a fluidic path together with the electronic chip (101), and a counter electrode (105) provided in a surface portion of the carrier element (103, 104).
摘要翻译：一种用于分析样品的电化学传感器装置（100），所述装置（100）包括电子芯片（101），所述电子芯片包括对样品颗粒敏感的传感器部分（102），粘合到所述样品的载体元件（103,104）电子芯片（101）与电子芯片（101）一起限定流体路径，以及设置在载体元件（103,104）的表面部分中的对电极（105）。

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