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1. 发明申请

US20220012055A1 APPARATUS, COMPUTER-READABLE MEDIUM, AND METHOD FOR REDUCING BOUNDS CHECKING OVERHEAD BY INSTRUMENTING POINTER ARITHMETIC 有权
公开(公告)号：US20220012055A1
公开(公告)日：2022-01-13
申请号：US17485347
申请日：2021-09-25
申请人： Michael Lemay , David M. Durham
发明人： Michael Lemay , David M. Durham
IPC分类号： G06F9/30
摘要： Methods, apparatus, systems, and articles of manufacture are disclosed that perform bounds checking on authorized memory allocations during pointer arithmetic. In some examples, instruction decode circuitry decodes an update pointer instruction for a pointer. In some examples, bounds checking circuitry determines an authorized allocation for the pointer, determines one or more exclusion zones and poison zones for the pointer. In some examples, bounds checking circuitry updates the pointer and generates a fault if the pointer points to one of the exclusion zones and poisons the pointer if the pointer points to one of the poison zones.

2. 发明申请

US20210200546A1 HARDWARE APPARATUSES, METHODS, AND SYSTEMS FOR INDIVIDUALLY REVOCABLE CAPABILITIES FOR ENFORCING TEMPORAL MEMORY SAFETY 有权
公开(公告)号：US20210200546A1
公开(公告)日：2021-07-01
申请号：US16729358
申请日：2019-12-28
申请人： Michael LEMAY , Vedvyas SHANBHOGUE , Deepak GUPTA , Ravi SAHITA , David M. DURHAM , Willem PINCKAERS , Enrico PERLA
发明人： Michael LEMAY , Vedvyas SHANBHOGUE , Deepak GUPTA , Ravi SAHITA , David M. DURHAM , Willem PINCKAERS , Enrico PERLA
IPC分类号： G06F9/30 , G06F9/38 , G06F9/448 , G06F9/46 , G06F16/901
摘要： Systems, methods, and apparatuses relating to circuitry to implement individually revocable capabilities for enforcing temporal memory safety are described. In one embodiment, a hardware processor comprises an execution unit to execute an instruction to request access to a block of memory through a pointer to the block of memory, and a memory controller circuit to allow access to the block of memory when an allocated object tag in the pointer is validated with an allocated object tag in an entry of a capability table in memory that is indexed by an index value in the pointer, wherein the memory controller circuit is to clear the allocated object tag in the capability table when a corresponding object is deallocated.

3. 发明申请

US20170249260A1 SYSTEM FOR ADDRESS MAPPING AND TRANSLATION PROTECTION 审中-公开
公开(公告)号：US20170249260A1
公开(公告)日：2017-08-31
申请号：US15088739
申请日：2016-04-01
申请人： RAVI L. SAHITA , GILBERT NEIGER , VEDVYAS SHANBHOGUE , DAVID M. DURHAM , ANDREW V. ANDERSON , DAVID A. KOUFATY , ASIT K. MALLICK , ARUMUGAM THIYAGARAJAH , BARRY E. HUNTLEY , DEEPAK K. GUPTA , MICHAEL LEMAY , JOSEPH F. CIHULA , BAIJU V. PATEL
发明人： RAVI L. SAHITA , GILBERT NEIGER , VEDVYAS SHANBHOGUE , DAVID M. DURHAM , ANDREW V. ANDERSON , DAVID A. KOUFATY , ASIT K. MALLICK , ARUMUGAM THIYAGARAJAH , BARRY E. HUNTLEY , DEEPAK K. GUPTA , MICHAEL LEMAY , JOSEPH F. CIHULA , BAIJU V. PATEL
IPC分类号： G06F12/14 , G06F12/10 , G06F21/62 , G06F3/06
摘要： This disclosure is directed to a system for address mapping and translation protection. In one embodiment, processing circuitry may include a virtual machine manager (VMM) to control specific guest linear address (GLA) translations. Control may be implemented in a performance sensitive and secure manner, and may be capable of improving performance for critical linear address page walks over legacy operation by removing some or all of the cost of page walking extended page tables (EPTs) for critical mappings. Alone or in combination with the above, certain portions of a page table structure may be selectively made immutable by a VMM or early boot process using a sub-page policy (SPP). For example, SPP may enable non-volatile kernel and/or user space code and data virtual-to-physical memory mappings to be made immutable (e.g., non-writable) while allowing for modifications to non-protected portions of the OS paging structures and particularly the user space.

4. 发明申请

US20140157349A1 Verified Sensor Data Processing 有权
标题翻译：验证的传感器数据处理
公开(公告)号：US20140157349A1
公开(公告)日：2014-06-05
申请号：US13690666
申请日：2012-11-30
申请人： Scott H. Robinson , Jason Martin , Howard C. Herbert , Michael LeMay , Karanvir Ken S. Grewal , Keith L. Shippy , Geoffrey Strongin
发明人： Scott H. Robinson , Jason Martin , Howard C. Herbert , Michael LeMay , Karanvir Ken S. Grewal , Keith L. Shippy , Geoffrey Strongin
IPC分类号： H04L29/06
CPC分类号： H04L63/20 , G06K9/00228 , H04L63/105 , H04L67/24
摘要： Sensor data may be filtered in a secure environment. The filtering may limit distribution of the sensor data. Filtering may modify the sensor data, for example, to prevent identification of a person depicted in a captured image or to prevent acquiring a user's precise location. Filtering may also add or require other data use controls to access the data. Attestation that a filter policy is being applied and working properly or not may be provided as well.
摘要翻译：传感器数据可能会在安全的环境中进行过滤。滤波可能会限制传感器数据的分布。过滤可以修改传感器数据，例如，以防止识别拍摄图像中描绘的人，或阻止获取用户的精确位置。过滤还可以添加或要求其他数据使用控制来访问数据。也可以提供过滤器策略正在应用和正常工作的证明。

5. 发明申请

US20230043506A1 APPARATUS AND METHOD FOR EFFICIENT PROCESS-BASED COMPARTMENTALIZATION 有权
公开(公告)号：US20230043506A1
公开(公告)日：2023-02-09
申请号：US17873668
申请日：2022-07-26
申请人： DAVID M. DURHAM , JACOB DOWECK , MICHAEL LEMAY , DEEPAK GUPTA
发明人： DAVID M. DURHAM , JACOB DOWECK , MICHAEL LEMAY , DEEPAK GUPTA
IPC分类号： G06F12/1027
摘要： An apparatus and method for efficient process-based compartmentalization. For example, one embodiment of a processor comprises: execution circuitry to execute instructions and process data; memory management circuitry coupled to the execution circuitry, the memory management circuitry to manage access to a system memory by a plurality of related processes using one or more process-specific translation structures and one or more shared translation structures to be shared by the related processes; and one or more control registers to store a process-specific base address pointer associated with a first process of the plurality of related processes and to store a shared base address pointer to identify the shared translation structures; wherein the memory management circuitry is to use the process-specific base address pointer in combination with a first linear address provided by the first process to walk the process-specific translation structures to identify any permissions and/or physical address associated with the first linear address, wherein if permissions are identified, the memory management circuitry is to use the permissions in place of any permissions specified in the shared translation structures.

6. 发明申请

US20170185773A1 TECHNIQUES FOR DETECTING MALWARE WITH MINIMAL PERFORMANCE DEGRADATION 有权
公开(公告)号：US20170185773A1
公开(公告)日：2017-06-29
申请号：US14757945
申请日：2015-12-24
申请人： MICHAEL LEMAY , DAVID M. DURHAM
发明人： MICHAEL LEMAY , DAVID M. DURHAM
IPC分类号： G06F21/56 , H04L29/06
CPC分类号： G06F21/566 , G06F21/567 , G06F2221/032 , H04L63/1416 , H04L63/145
摘要： Various embodiments are generally directed to techniques for detecting malware in a manner that mitigates the consumption of processing and/or storage resources of a processing device. An apparatus may include a first processor component of a processing device to generate entries in a chronological order within a first page modification log maintained within a first storage divided into multiple pages, each entry to indicate a write access made by the first processor component to a page of the multiple pages; a retrieval component of a graphics controller of the processing device to recurringly retrieve indications from the first page modification log of at least one recently written page of the multiple pages; and a scan component of the graphics controller to recurringly scan the at least one recently written page to detect malware within the at least one recently written page.

7. 发明申请

US20160092673A1 HARDWARE SHADOW STACK SUPPORT FOR LEGACY GUESTS 有权
标题翻译：硬件阴影堆栈支持LEGACY GUESTS
公开(公告)号：US20160092673A1
公开(公告)日：2016-03-31
申请号：US14498075
申请日：2014-09-26
申请人： Michael LeMay , Barry E. Huntley
发明人： Michael LeMay , Barry E. Huntley
IPC分类号： G06F21/52 , G06F9/455
CPC分类号： G06F21/52 , G06F8/30 , G06F8/31 , G06F9/4484 , G06F9/45533 , G06F9/45558 , G06F11/3419 , G06F21/56 , G06F2009/45587
摘要： Technologies for shadow stack support for legacy guests include a computing device having a processor with shadow stack support. During execution of a call instruction, the processor determines whether a legacy stack pointer is within bounds and generates a virtual machine exit if the legacy stack pointer is out-of-bounds. If not out-of-bounds, the processor pushes a return address onto the legacy stack and onto a shadow stack protected by a hypervisor. During execution of a return instruction, the processor determines whether top return addresses of the legacy stack and the shadow stack match, and generates a virtual machine exit if the return addresses do not match. If the return addresses match, the processor pops the return addresses off of the legacy stack and off of the shadow stack. The stack out-of-bounds and the stack mismatch virtual machine exits may be handled by the hypervisor. Other embodiments are described and claimed.
摘要翻译：用于传统客户端的影子堆栈支持技术包括具有处理器的计算设备，该处理器具有阴影栈支持。在执行调用指令期间，处理器确定传统堆栈指针是否在边界内，如果传统堆栈指针超出边界，则会生成虚拟机退出。如果不是超出范围，处理器将返回地址推送到传统堆栈上，并将其保存到由管理程序保护的影子堆栈上。在执行返回指令期间，处理器确定传统堆栈和影子堆叠的顶部返回地址是否匹配，并且如果返回地址不匹配则生成虚拟机退出。如果返回地址匹配，处理器会将返回地址从传统堆栈中弹出并离开阴影栈。虚拟机管理程序可以处理堆栈超出范围和堆栈不匹配的虚拟机退出。描述和要求保护其他实施例。

8. 发明申请

US20160055571A1 SELECTIVE SHARING OF USER INFORMATION BASED ON CONTEXTUAL RELATIONSHIP INFORMATION, SUCH AS TO CROWD-SOURCE GIFTS OF INTEREST TO A RECIPIENT 审中-公开
标题翻译：基于相关关系信息的用户信息的选择性共享，如对受益人的兴趣爱好的礼物
公开(公告)号：US20160055571A1
公开(公告)日：2016-02-25
申请号：US14780535
申请日：2014-06-23
申请人： Rita H WOUHAYBI , Timothy G COPPERNOLL , Jose K SIA Jr. , Richard T BECKWITH , Maria BEZAITIS , Scott H ROBINSON , Vinay PHEGADE , Michael LEMAY
发明人： Rita H WOUHAYBI , Timothy G COPPERNOLL , Jose K SIA Jr. , Richard T BECKWITH , Maria BEZAITIS , Scott H ROBINSON , Vinay PHEGADE , Michael LEMAY
IPC分类号： G06Q30/06 , G07C13/00 , G06F17/30
CPC分类号： G06Q30/0635 , G06F16/285 , G06F16/9535 , G06Q30/02 , G06Q30/0214 , G06Q30/0601 , G06Q30/0613 , G06Q30/0631 , G06Q30/0641 , G07C13/00
摘要： Selective/controlled disclosure of user information to private workspaces of other users/invitees based on context/contextual relations, and a shared workspace or market to collaborate amongst the other users (e.g., to crowd-source gifts of interest to the recipient). Contextual disclosure may be based on common context or commonality under a set of conditions, such as a topic, which may include known topics of relationships amongst the users and/or undiscovered contexts. As an example, items of interest to each user are identified and clustered, keywords are assigned to the clusters indicative of topics/subjects of interests to the respective users, recipient keywords are compared to keywords of an invitee to identify common keywords as shared interests, and items of interest to the recipient that relate to the common keywords are disclosed to the invitee as a personalized wish-list. Keyword weighting and/or keyword/item level privacy designations may be provided to further control disclosure.
摘要翻译：基于上下文/上下文关系向其他用户/受邀者的私有工作空间选择/控制地披露用户信息，以及共享的工作空间或市场以在其他用户之间进行协作（例如，将收件人感兴趣的馈赠给收件人）。上下文公开可以基于一组条件下的通用上下文或通用性，例如主题，其可以包括用户之间的关系的已知主题和/或未发现的上下文。作为示例，识别和聚集每个用户感兴趣的项目，将关键字分配给指示相应用户的主题/主题的集群，将收件人关键字与受邀者的关键字进行比较，以将共同关键字识别为共享兴趣，并且与所述公共关键字相关的所述收件人感兴趣的项目作为个性化愿望列表被公开给被邀请者。可以提供关键字加权和/或关键字/项目级别隐私指定以进一步控制公开。

9. 发明授权

US10515023B2 System for address mapping and translation protection 有权
公开(公告)号：US10515023B2
公开(公告)日：2019-12-24
申请号：US15088739
申请日：2016-04-01
申请人： Ravi L. Sahita , Gilbert Neiger , Vedvyas Shanbhogue , David M. Durham , Andrew V. Anderson , David A. Koufaty , Asit K. Mallick , Arumugam Thiyagarajah , Barry E. Huntley , Deepak K. Gupta , Michael Lemay , Joseph F. Cihula , Baiju V. Patel
发明人： Ravi L. Sahita , Gilbert Neiger , Vedvyas Shanbhogue , David M. Durham , Andrew V. Anderson , David A. Koufaty , Asit K. Mallick , Arumugam Thiyagarajah , Barry E. Huntley , Deepak K. Gupta , Michael Lemay , Joseph F. Cihula , Baiju V. Patel
IPC分类号： G06F12/00 , G06F12/14 , G06F12/1009 , G06F9/455 , G06F12/1027 , G06F21/78
摘要： This disclosure is directed to a system for address mapping and translation protection. In one embodiment, processing circuitry may include a virtual machine manager (VMM) to control specific guest linear address (GLA) translations. Control may be implemented in a performance sensitive and secure manner, and may be capable of improving performance for critical linear address page walks over legacy operation by removing some or all of the cost of page walking extended page tables (EPTs) for critical mappings. Alone or in combination with the above, certain portions of a page table structure may be selectively made immutable by a VMM or early boot process using a sub-page policy (SPP). For example, SPP may enable non-volatile kernel and/or user space code and data virtual-to-physical memory mappings to be made immutable (e.g., non-writable) while allowing for modifications to non-protected portions of the OS paging structures and particularly the user space.

10. 发明申请

US20160179665A1 CONTROL OF ENTRY INTO PROTECTED MEMORY VIEWS 有权
标题翻译：进入受保护的存储器视图的控制
公开(公告)号：US20160179665A1
公开(公告)日：2016-06-23
申请号：US14581730
申请日：2014-12-23
申请人： Michael LeMay , Ravi L. Sahita , Barry E. Huntley , David M. Durham , Vedvyas Shanbhogue
发明人： Michael LeMay , Ravi L. Sahita , Barry E. Huntley , David M. Durham , Vedvyas Shanbhogue
IPC分类号： G06F12/08 , G06F9/455
CPC分类号： G06F12/08 , G06F9/45558 , G06F12/1009 , G06F12/1491 , G06F21/79 , G06F2009/45583 , G06F2009/45591 , G06F2212/151 , G06F2212/657
摘要： Generally, this disclosure provides systems, devices, methods and computer readable media for controlled memory view switching. The system may include a memory module comprising a shared address space between a first memory view and a second memory view. The system may also include a virtual machine monitor (VMM) to maintain a list of Controlled View Switch (CVS) descriptors. The system may further include a processor to receive a memory view switch request and to execute an instruction to save processor state information and switch from the first memory view to the second memory view, wherein the second memory view is specified by an extended page table pointer (EPTP) provided by one of the CVS descriptors.
摘要翻译：通常，本公开提供了用于受控存储器视图切换的系统，设备，方法和计算机可读介质。该系统可以包括存储器模块，该存储器模块包括第一存储器视图和第二存储器视图之间的共享地址空间。该系统还可以包括维护受控视图切换（CVS）描述符的列表的虚拟机监视器（VMM）。该系统还可以包括处理器，用于接收存储器视图切换请求并且执行用于保存处理器状态信息并从第一存储器视图切换到第二存储器视图的指令，其中第二存储器视图由扩展页表指针（EPTP）由其中一个CVS描述符提供。

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