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1. 发明申请

US20210200546A1 HARDWARE APPARATUSES, METHODS, AND SYSTEMS FOR INDIVIDUALLY REVOCABLE CAPABILITIES FOR ENFORCING TEMPORAL MEMORY SAFETY 有权
公开(公告)号：US20210200546A1
公开(公告)日：2021-07-01
申请号：US16729358
申请日：2019-12-28
申请人： Michael LEMAY , Vedvyas SHANBHOGUE , Deepak GUPTA , Ravi SAHITA , David M. DURHAM , Willem PINCKAERS , Enrico PERLA
发明人： Michael LEMAY , Vedvyas SHANBHOGUE , Deepak GUPTA , Ravi SAHITA , David M. DURHAM , Willem PINCKAERS , Enrico PERLA
IPC分类号： G06F9/30 , G06F9/38 , G06F9/448 , G06F9/46 , G06F16/901
摘要： Systems, methods, and apparatuses relating to circuitry to implement individually revocable capabilities for enforcing temporal memory safety are described. In one embodiment, a hardware processor comprises an execution unit to execute an instruction to request access to a block of memory through a pointer to the block of memory, and a memory controller circuit to allow access to the block of memory when an allocated object tag in the pointer is validated with an allocated object tag in an entry of a capability table in memory that is indexed by an index value in the pointer, wherein the memory controller circuit is to clear the allocated object tag in the capability table when a corresponding object is deallocated.

2. 发明申请

US20190228145A1 APPARATUSES, METHODS, AND SYSTEMS FOR VERIFICATION OF INPUT-OUTPUT MEMORY MANAGEMENT UNIT TO DEVICE ATTACHMENT 审中-公开
公开(公告)号：US20190228145A1
公开(公告)日：2019-07-25
申请号：US16370921
申请日：2019-03-30
申请人： Vedvyas Shanbhogue , Ravi Sahita , Abhishek Basak , Pradeep Pappachan , Utkarsh Kakaiya , Ravi Sahita , Rupin Vakharwala
发明人： Vedvyas Shanbhogue , Ravi Sahita , Abhishek Basak , Pradeep Pappachan , Utkarsh Kakaiya , Ravi Sahita , Rupin Vakharwala
IPC分类号： G06F21/44 , G06F13/16 , G06F3/06
摘要： Systems, methods, and apparatuses relating to performing an attachment of an input-output memory management unit (IOMMU) to a device, and a verification of the attachment. In one embodiment, a protocol and IOMMU extensions are used by a secure arbitration mode (SEAM) module and/or circuitry to determine if the IOMMU that is attached to the device requested to be mapped to a trusted domain.

3. 发明申请

US20180004675A1 APPLICATION EXECUTION ENCLAVE MEMORY METHOD AND APPARATUS 审中-公开
公开(公告)号：US20180004675A1
公开(公告)日：2018-01-04
申请号：US15200796
申请日：2016-07-01
申请人： VEDVYAS SHANBHOGUE , ITTAI ANATI , FRANCIS X. MCKEEN , KRYSTOF C. ZMUDZINSKI , MELTEM OZSOY
发明人： VEDVYAS SHANBHOGUE , ITTAI ANATI , FRANCIS X. MCKEEN , KRYSTOF C. ZMUDZINSKI , MELTEM OZSOY
IPC分类号： G06F12/1009 , G06F12/14 , G06F12/0802 , G06F3/06
CPC分类号： G06F12/1009 , G06F3/0623 , G06F3/0631 , G06F3/0673 , G06F12/1425 , G06F12/1475 , G06F2212/1052 , G06F2212/657
摘要： Apparatuses, methods and storage medium associated with application execution enclave memory page cache management, are disclosed herein. In embodiments, an apparatus may include a processor with processor supports for application execution enclaves; memory organized into a plurality of host physical memory pages; and a virtual machine monitor to be operated by the processor to manage operation of virtual machines. Management of operation of the virtual machines may include facilitation of mapping of virtual machine-physical memory pages of the virtual machines to the host physical memory pages, including maintenance of an unallocated subset of the host physical memory pages to receive increased security protection for selective allocation to the virtual machines, for virtualization and selective allocation to application execution enclaves of applications of the virtual machines. Other embodiments may be described and/or claimed.

4. 发明申请

US20170249260A1 SYSTEM FOR ADDRESS MAPPING AND TRANSLATION PROTECTION 审中-公开
公开(公告)号：US20170249260A1
公开(公告)日：2017-08-31
申请号：US15088739
申请日：2016-04-01
申请人： RAVI L. SAHITA , GILBERT NEIGER , VEDVYAS SHANBHOGUE , DAVID M. DURHAM , ANDREW V. ANDERSON , DAVID A. KOUFATY , ASIT K. MALLICK , ARUMUGAM THIYAGARAJAH , BARRY E. HUNTLEY , DEEPAK K. GUPTA , MICHAEL LEMAY , JOSEPH F. CIHULA , BAIJU V. PATEL
发明人： RAVI L. SAHITA , GILBERT NEIGER , VEDVYAS SHANBHOGUE , DAVID M. DURHAM , ANDREW V. ANDERSON , DAVID A. KOUFATY , ASIT K. MALLICK , ARUMUGAM THIYAGARAJAH , BARRY E. HUNTLEY , DEEPAK K. GUPTA , MICHAEL LEMAY , JOSEPH F. CIHULA , BAIJU V. PATEL
IPC分类号： G06F12/14 , G06F12/10 , G06F21/62 , G06F3/06
摘要： This disclosure is directed to a system for address mapping and translation protection. In one embodiment, processing circuitry may include a virtual machine manager (VMM) to control specific guest linear address (GLA) translations. Control may be implemented in a performance sensitive and secure manner, and may be capable of improving performance for critical linear address page walks over legacy operation by removing some or all of the cost of page walking extended page tables (EPTs) for critical mappings. Alone or in combination with the above, certain portions of a page table structure may be selectively made immutable by a VMM or early boot process using a sub-page policy (SPP). For example, SPP may enable non-volatile kernel and/or user space code and data virtual-to-physical memory mappings to be made immutable (e.g., non-writable) while allowing for modifications to non-protected portions of the OS paging structures and particularly the user space.

5. 发明授权

US09330020B2 System, apparatus, and method for transparent page level instruction translation 有权
标题翻译：用于透明页面级指令转换的系统，设备和方法
公开(公告)号：US09330020B2
公开(公告)日：2016-05-03
申请号：US14142309
申请日：2013-12-27
申请人： Paul Caprioli , Vedvyas Shanbhogue , Koichi Yamada
发明人： Paul Caprioli , Vedvyas Shanbhogue , Koichi Yamada
IPC分类号： G06F12/00 , G06F12/10
CPC分类号： G06F12/1027 , G06F12/1009
摘要： Detailed herein are systems, apparatuses, and methods for transparent page level instruction translation. Exemplary embodiments include an instruction translation lookaside buffer (iTLB), wherein each iTLB entry includes a linear address of a page in memory, a physical address of the page in memory, and a remapping indicator.
摘要翻译：这里详细描述了用于透明页面级指令转换的系统，装置和方法。示例性实施例包括指令转换后备缓冲器（iTLB），其中每个iTLB条目包括存储器中的页面的线性地址，存储器中的页面的物理地址以及重映射指示符。

6. 发明申请

US20140297962A1 INSTRUCTIONS AND LOGIC TO PROVIDE ADVANCED PAGING CAPABILITIES FOR SECURE ENCLAVE PAGE CACHES 有权
标题翻译：指示和逻辑提供先进的分页功能，以确保安全的页面缓存
公开(公告)号：US20140297962A1
公开(公告)日：2014-10-02
申请号：US13854107
申请日：2013-03-31
申请人： CARLOS V ROZAS , ILYA ALEXANDROVICH , ITTAI ANATI , ALEX BERENZON , MICHAEL A GOLDSMITH , BARRY E HUNTLEY , ANTON IVANOV , SIMON P JOHNSON , REBEKAH M. LESLIE-HURD , FRANCIS X. MCKEEN , GILBERT NEIGER , RINAT RAPPOPORT , SCOTT DION RODGERS , UDAY R. SAVAGAONKAR , VINCENT R. SCARLATA , VEDVYAS SHANBHOGUE , WESLEY H SMITH , WILLIAM COLIN WOOD
发明人： CARLOS V ROZAS , ILYA ALEXANDROVICH , ITTAI ANATI , ALEX BERENZON , MICHAEL A GOLDSMITH , BARRY E HUNTLEY , ANTON IVANOV , SIMON P JOHNSON , REBEKAH M. LESLIE-HURD , FRANCIS X. MCKEEN , GILBERT NEIGER , RINAT RAPPOPORT , SCOTT DION RODGERS , UDAY R. SAVAGAONKAR , VINCENT R. SCARLATA , VEDVYAS SHANBHOGUE , WESLEY H SMITH , WILLIAM COLIN WOOD
IPC分类号： G06F12/08 , G06F12/10
CPC分类号： G06F12/0875 , G06F12/0808 , G06F12/1027 , G06F2212/1016 , G06F2212/402
摘要： Instructions and logic provide advanced paging capabilities for secure enclave page caches. Embodiments include multiple hardware threads or processing cores, a cache to store secure data for a shared page address allocated to a secure enclave accessible by the hardware threads. A decode stage decodes a first instruction specifying said shared page address as an operand, and execution units mark an entry corresponding to an enclave page cache mapping for the shared page address to block creation of a new translation for either of said first or second hardware threads to access the shared page. A second instruction is decoded for execution, the second instruction specifying said secure enclave as an operand, and execution units record hardware threads currently accessing secure data in the enclave page cache corresponding to the secure enclave, and decrement the recorded number of hardware threads when any of the hardware threads exits the secure enclave.
摘要翻译：说明和逻辑为安全的飞地页面缓存提供了高级分页功能。实施例包括多个硬件线程或处理核心，用于存储分配给由硬件线程可访问的安全空间的共享页面地址的安全数据的高速缓存。解码级将指定所述共享页地址的第一指令解码为操作数，并且执行单元标记对应于共享页地址的飞地页高速缓存映射的条目，以阻止所述第一或第二硬件线程中的任一个的新转换的创建访问共享页面。第二指令被解码以执行，第二指令指定所述安全飞地作为操作数，并且执行单元记录当前访问与安全飞地相对应的飞地页面缓存中的安全数据的硬件线程，并且当任何的硬件线程退出安全飞地。

7. 发明申请

US20140189326A1 MEMORY MANAGEMENT IN SECURE ENCLAVES 有权
标题翻译：内存管理在安全的包装
公开(公告)号：US20140189326A1
公开(公告)日：2014-07-03
申请号：US13729371
申请日：2012-12-28
申请人： Rebekah Leslie , Carlos V. Rozas , Vincent R. Scarlata , Simon P. Johnson , Uday R. Savagaonkar , Barry E. Huntley , Vedvyas Shanbhogue , Ittai Anati , Francis X. Mckeen , Michael A. Goldsmith , Ilya Alexandrovich , Alex Berenzon , Wesley H. Smith
发明人： Rebekah Leslie , Carlos V. Rozas , Vincent R. Scarlata , Simon P. Johnson , Uday R. Savagaonkar , Barry E. Huntley , Vedvyas Shanbhogue , Ittai Anati , Francis X. Mckeen , Michael A. Goldsmith , Ilya Alexandrovich , Alex Berenzon , Wesley H. Smith
IPC分类号： G06F9/30
CPC分类号： G06F9/3004 , G06F9/30047 , G06F9/30076 , G06F9/44 , G06F12/084 , G06F12/0875 , G06F12/1483 , G06F2212/452
摘要： Embodiments of an invention for memory management in secure enclaves are disclosed. In one embodiment, a processor includes an instruction unit and an execution unit. The instruction unit is to receive a first instruction and a second instruction. The execution unit is to execute the first instruction, wherein execution of the first instruction includes allocating a page in an enclave page cache to a secure enclave. The execution unit is also to execute the second instruction, wherein execution of the second instruction includes confirming the allocation of the page.
摘要翻译：公开了用于安全飞行器中的存储器管理的发明的实施例。在一个实施例中，处理器包括指令单元和执行单元。指令单元接收第一指令和第二指令。执行单元执行第一指令，其中第一指令的执行包括将飞地页面缓存中的页面分配到安全飞地。执行单元还执行第二指令，其中第二指令的执行包括确认页的分配。

8. 发明申请

US20140189325A1 PAGING IN SECURE ENCLAVES 有权
标题翻译：寻找安全的包装
公开(公告)号：US20140189325A1
公开(公告)日：2014-07-03
申请号：US13729277
申请日：2012-12-28
申请人： Francis X. Mckeen , Michael A. Goldsmith , Barry E. Huntley , Simon P. Johnson , Rebekah Leslie , Carlos V. Rozas , Uday R. Savagaonkar , Vincent R. Scarlata , Vedvyas Shanbhogue , Wesley H. Smith , Ittai Anati , Ilya Alexandrovich , Alex Berenzon
发明人： Francis X. Mckeen , Michael A. Goldsmith , Barry E. Huntley , Simon P. Johnson , Rebekah Leslie , Carlos V. Rozas , Uday R. Savagaonkar , Vincent R. Scarlata , Vedvyas Shanbhogue , Wesley H. Smith , Ittai Anati , Ilya Alexandrovich , Alex Berenzon
IPC分类号： G06F9/30
CPC分类号： G06F12/0804 , G06F9/30047 , G06F12/0875 , G06F12/1408 , G06F2212/1052 , G06F2212/402
摘要： Embodiments of an invention for paging in secure enclaves are disclosed. In one embodiment, a processor includes an instruction unit and an execution unit. The instruction unit is to receive a first instruction. The execution unit is to execute the first instruction, wherein execution of the first instruction includes evicting a first page from an enclave page cache.
摘要翻译：公开了用于在安全飞行器中寻呼的发明的实施例。在一个实施例中，处理器包括指令单元和执行单元。指令单元接收第一条指令。执行单元执行第一指令，其中第一指令的执行包括从飞地页面缓存中逐出第一页。

9. 发明授权

US08510569B2 Providing integrity verification and attestation in a hidden execution environment 有权
公开(公告)号：US08510569B2
公开(公告)日：2013-08-13
申请号：US12639616
申请日：2009-12-16
申请人： Ned Smith , Vedvyas Shanbhogue , Arvind Kumar , Purushottam Goel
发明人： Ned Smith , Vedvyas Shanbhogue , Arvind Kumar , Purushottam Goel
IPC分类号： G06F9/30 , G06F21/22
CPC分类号： G06F21/554 , G06F21/44 , G06F21/57 , G06F21/64
摘要： In one embodiment, a processor includes a microcode storage including processor instructions to create and execute a hidden resource manager (HRM) to execute in a hidden environment that is not visible to system software. The processor may further include an extend register to store security information including a measurement of at least one kernel code module of the hidden environment and a status of a verification of the at least one kernel code module. Other embodiments are described and claimed.

10. 发明申请

US20090222792A1 AUTOMATIC MODIFICATION OF EXECUTABLE CODE 有权
标题翻译：自动修改可执行代码
公开(公告)号：US20090222792A1
公开(公告)日：2009-09-03
申请号：US12039486
申请日：2008-02-28
申请人： Vedvyas Shanbhogue , Ravi L. Sahita , Uday R. Savagaonkar
发明人： Vedvyas Shanbhogue , Ravi L. Sahita , Uday R. Savagaonkar
IPC分类号： G06F9/44
CPC分类号： G06F9/4484 , G06F2209/542
摘要： A method for automatically modifying an executable file for a software agent is provided. The method comprises detecting original static entry and exit points in the executable file and generating corresponding transformed points; modifying the executable file by linking the executable file to the integrity services environment and embedding a signed agent manifest; loading the modified executable file into memory and registering a target list with the software agent's hypervisor, wherein the target list provides mappings between protected and active page tables; detecting dynamic entry and exit points in the executable file and generating corresponding transformed points; switching to a protected context, in response to a transformed exit point being invoked, and switching to an active context, in response a transformed entry point being invoked; and de-registering the software agent with the memory protection module, in response to the software agent being unloaded.
摘要翻译：提供了一种用于自动修改软件代理的可执行文件的方法。该方法包括检测可执行文件中的原始静态入口点和出口点，并产生相应的变换点; 通过将可执行文件链接到完整性服务环境并嵌入签名的代理清单来修改可执行文件; 将修改的可执行文件加载到存储器中并且与所述软件代理的管理程序注册目标列表，其中所述目标列表提供受保护页面和活动页面表之间的映射; 检测可执行文件中的动态入口点和出口点，并生成相应的转换点; 响应于被转换的退出点被调用，切换到受保护的上下文，并且响应于被转换的入口点被切换到活动上下文; 以及响应于所述软件代理被卸载，将所述软件代理与所述存储器保护模块取消注册。

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