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1. 发明授权

US08103989B2 Method and system for changing circuits in an integrated circuit 有权
标题翻译：用于改变集成电路中的电路的方法和系统
公开(公告)号：US08103989B2
公开(公告)日：2012-01-24
申请号：US12037421
申请日：2008-02-26
申请人： Nathan A. Dotson , Jonathan Y. Chen , David L. Rude , Vern A. Victoria
发明人： Nathan A. Dotson , Jonathan Y. Chen , David L. Rude , Vern A. Victoria
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： A method for modifying an integrated circuit and integrated circuits are provided. The method includes: providing an integrated circuit design comprising a plurality of circuit books having a first threshold voltage; and replacing at least one of the plurality of circuit books with at least one gate array book having a second threshold voltage that is lower than the first threshold voltage.
摘要翻译：提供了一种用于修改集成电路和集成电路的方法。该方法包括：提供包括具有第一阈值电压的多个电路簿的集成电路设计; 以及用具有低于第一阈值电压的第二阈值电压的至少一个门阵列簿代替多个电路簿中的至少一个。

2. 发明授权

US07739538B2 Double data rate chaining for synchronous DDR interfaces 失效
标题翻译：双数据速率链接同步DDR接口
公开(公告)号：US07739538B2
公开(公告)日：2010-06-15
申请号：US11426651
申请日：2006-06-27
申请人： Michael Fee , Patrick J. Meaney , Christopher J. Berry , Jonathan Y. Chen , Alan P. Wagstaff
发明人： Michael Fee , Patrick J. Meaney , Christopher J. Berry , Jonathan Y. Chen , Alan P. Wagstaff
IPC分类号： G06F5/06 , G11C8/16
CPC分类号： G06F13/4217
摘要： A system and method in which the receiving chip separately latches each half of the data received from the double data rate bus. Each half is launched as soon as it is available; one on the normal chip cycle time and the other is launched from a Master (L1) latch a half cycle into the normal chip cycle time. The first launched half of the data proceeds through the chip along its standard design chip path to be captured by the chips driving interface latch and launched again after one cycle of latency on the chip. The second half of the data proceeds through the chip one half cycle behind the first half, and is latched a half clock cycle later part way through the path into a Slave (L2) latch. On the next edge of the local clock, the data then continues from the L2 latch to the driving double data rate interface. This allows a half cycle set up time for the second half of the data so that it can be launched again, maintaining a one-cycle time on the chip.
摘要翻译：一种系统和方法，其中接收芯片分别锁存从双数据速率总线接收的数据的每一半。每一半都可以立即启动; 一个在正常的芯片周期时间，另一个从主（L1）锁存器半个周期启动到正常的芯片周期时间。首先推出的一半数据通过芯片沿其标准设计芯片路径进行，由芯片驱动接口锁存器捕获，并在芯片上的一个延迟周期后再次启动。数据的后半部分通过芯片在上半部分后半个周期进行，并且稍后通过进入从（L2）锁存器的路径被锁存半个时钟周期。在本地时钟的下一个边缘，数据然后从L2锁存器继续到驱动双数据速率接口。这允许半周期的半周期设置时间，以便可以再次启动，在芯片上保持一个周期的时间。

3. 发明授权

US07734944B2 Mechanism for windaging of a double rate driver 有权
标题翻译：双速率驱动程序的机制
公开(公告)号：US07734944B2
公开(公告)日：2010-06-08
申请号：US11426648
申请日：2006-06-27
申请人： Jonathan Y. Chen , Jeffrey A. Magee , David A. Webber
发明人： Jonathan Y. Chen , Jeffrey A. Magee , David A. Webber
IPC分类号： G06F5/06 , G06F13/42 , H04L7/00
CPC分类号： G06F1/12
摘要： A double data rate launch system and method in which the two-to-one multiplexer select signal delay is programmable and can be adjusted individually for each system. This allows the amount of delay to be minimized based on the actual set up time required, not the worst-case set-up time. The select signal to the multiplexer is delayed sufficiently to compensate for non-uniformity of duty cycle of data at the inputs to the multiplexer. Compensation of the non-uniformity allows the data on the wire to have a uniform duty cycle for all data transferred regardless of which latch is sourcing the data. The multiplexer that selects data from the two latches which are launching data on the edge of different clocks has a select line that is delayed by a variable amount to tune the select such that the data is clean at the input to the multiplexer on all ports.
摘要翻译：双数据速率发射系统和方法，其中两对一多路复用器选择信号延迟是可编程的，并且可以针对每个系统单独调整。这允许根据所需的实际设置时间而不是最坏的设置时间来最小化延迟量。到复用器的选择信号被充分延迟以补偿多路复用器的输入处的数据的占空比的不均匀性。不均匀性的补偿允许导线上的数据对于所有传输的数据具有统一的占空比，而不考虑哪个锁存器来源数据。选择来自两个锁存器的数据的多路复用器，这些数据是在不同时钟边沿发射数据的，具有延迟一个可变量的选择线，以调整选择，使得数据在所有端口上的多路复用器的输入处是干净的。

4. 发明授权

US07254656B2 Method and service and computer program code for broadcast of interface group bring-up in a multiprocessor computer system having multiple nodes 有权
标题翻译：在具有多个节点的多处理器计算机系统中，用于广播接口组的方法和服务以及计算机程序代码
公开(公告)号：US07254656B2
公开(公告)日：2007-08-07
申请号：US10987657
申请日：2004-11-13
申请人： Derrin M. Berger , Jonathan Y. Chen , Thomas E. Gilbert
发明人： Derrin M. Berger , Jonathan Y. Chen , Thomas E. Gilbert
IPC分类号： G06F13/00
CPC分类号： G06F13/4027
摘要： A method and hardware design is disclosed for allowing the bring-up of a large scale system of interfaces that need to undergo a sequence of calibration steps. The method involves the use of a flexible broadcast scheme whereby groups of interfaces within a chip are assigned to groups to which commands can be broadcast. The scheme allows for the maximum amount of flexibility, allowing interfaces to be assigned to multiple groups which can overlap and be subsets of one another, and still allows for groups to be excluded from broadcast commands and be access individually. A method is also disclosed for using a chip-global status summary that can be accessed as any other register on the chip and can report calibration results for an entire chip with only one command. According to the invention a service utilizing the method embodied with code for implementing the method can now be provided.
摘要翻译：公开了用于允许需要经历一系列校准步骤的大规模系统的接口的方法和硬件设计。该方法涉及使用灵活广播方案，由此将芯片内的接口组分配给可以广播命令的组。该方案允许最大的灵活性，允许将接口分配给可以重叠并且彼此子集的多个组，并且仍然允许将组排除在广播命令之外并且被单独访问。还公开了一种用于使用芯片全局状态概要的方法，其可以作为芯片上的任何其他寄存器访问，并且可以仅用一个命令报告整个芯片的校准结果。根据本发明，现在可以提供利用具有用于实现该方法的代码体现的方法的服务。

5. 发明授权

US06954870B2 Method for receiver delay detection and latency minimization for a source synchronous wave pipelined interface 失效
标题翻译：用于源同步波流水线接口的接收机延迟检测和延迟最小化的方法
公开(公告)号：US06954870B2
公开(公告)日：2005-10-11
申请号：US10096382
申请日：2002-03-12
申请人： Jonathan Y. Chen , Frank D. Ferraiolo , Kevin C. Gower , Patrick J. Meaney , William J. Scarpero, Jr.
发明人： Jonathan Y. Chen , Frank D. Ferraiolo , Kevin C. Gower , Patrick J. Meaney , William J. Scarpero, Jr.
IPC分类号： G06F1/12 , G06F3/00 , H04L7/00 , H04L7/10
CPC分类号： H04L7/10 , H04L7/0008 , H04L7/005
摘要： A method of calibrating an elastic interface is provided to automatically achieve a minimal cycle delay through the interface. An existing self-alignment interface (i.e. elastic interface) is used to de-skew within a cycle and stage the data to have it arrive on a given, programmed target cycle. However, this target cycle must be calculated in advance and may be larger than it needs to be, causing more latency on the interface. This method is used to determine the earliest target cycle (with or without additional guard-band). This target cycle is used to adjust the interface automatically to achieve this earliest target cycle. The determination of earliest target cycle can be done once, continuously, or using a sample window. The method also can be used for interfaces that have frequency multipliers or phase shifts at its boundaries.
摘要翻译：提供校准弹性界面的方法以通过界面自动实现最小的循环延迟。现有的自对准接口（即弹性接口）用于在一个周期内去偏移，并且在给定的编程的目标周期上对数据进行分段以使其达到。但是，这个目标周期必须提前计算，并且可能会大于需要的时间，从而在接口上造成更多的延迟。该方法用于确定最早的目标周期（带或不带附加保护带）。该目标周期用于自动调整接口以实现最早的目标周期。最早的目标周期的确定可以进行一次，连续或使用样本窗口。该方法还可用于在其边界具有频率乘法器或相移的接口。

6. 发明授权

US07739545B2 System and method to support use of bus spare wires in connection modules 失效
标题翻译：支持在连接模块中使用总线备用电缆的系统和方法
公开(公告)号：US07739545B2
公开(公告)日：2010-06-15
申请号：US11531430
申请日：2006-09-13
申请人： Mark A. Check , Jonathan Y. Chen , Thomas G. Foote , Timothy J. Slegel
发明人： Mark A. Check , Jonathan Y. Chen , Thomas G. Foote , Timothy J. Slegel
IPC分类号： G06F11/00
CPC分类号： G01R31/31855 , G01R31/31717
摘要： In a computer system with multiple chips connected via a connection module with high speed elastic interface buses that support bus repair is enhanced by use of a spare net. Support is provided to ensure that the spare net can be tested in the same way that every normal bus net can be tested at all supported environments. It ensure that the system controller can find out what connections are bad and how to apply the controls to repair them for all tests and in the field for the customer.
摘要翻译：在具有通过连接模块连接的多个芯片的计算机系统中，通过使用备用网络来增强支持总线修理的高速弹性接口总线。提供支持，以确保备用网络的测试方式与每个正常总线网络在所有支持环境下都可以进行测试相同。它确保系统控制器可以找出哪些连接不好，以及如何应用控件来对所有测试进行修复，并为客户提供现场维护。

7. 发明申请

US20080075680A1 Culture of microorganisms endogenous to plants and products thereof 审中-公开
标题翻译：植物内源性微生物培养及其产物
公开(公告)号：US20080075680A1
公开(公告)日：2008-03-27
申请号：US11898512
申请日：2007-09-12
申请人： Jonathan Y. Chen
发明人： Jonathan Y. Chen
IPC分类号： A61K8/00 , A61P43/00 , C12N1/02
CPC分类号： C12N1/20 , A61K8/97 , A61K8/99 , A61Q7/00
摘要： The culture of microorganisms endogenous to plants is a process for increasing the number of such microorganisms and collecting the enriched culture media for nutritional, pharmaceutical and cosmetic use. The process includes the steps of: (a) separating plant components (e.g., leaves, fruit, etc.) into smaller parts; (b) immersing the smaller plant parts in a culture medium of an aqueous solution of sodium chloride and sucrose; (c) permitting the immersed parts to stand in the culture medium for between about 7-14 days; (d) removing the smaller plant parts from the culture medium; (e) dividing the culture medium into two portions; (f) diluting each of the portions 1:2 with water; (g) permitting the diluted portions to stand between about 7-14 days to ferment; (h) filtering the diluted portions; and (i) collecting the supernatant. Steps (e) through (g) may be repeated as often as desired. The process may also include maintaining the concentration of sucrose.
摘要翻译：植物内生的微生物培养物是增加这种微生物数量并收集用于营养，药物和化妆品使用的富集培养基的方法。该方法包括以下步骤：（a）将植物成分（例如叶，水果等）分离成更小的部分; （b）将较小的植物部分浸入氯化钠和蔗糖水溶液的培养基中; （c）使浸没的部件在培养基中放置约7-14天; （d）从培养基中除去较小的植物部分; （e）将培养基分成两部分; （f）用水稀释各部分1：2; （g）使稀释部分放置在约7-14天之间以发酵; （h）过滤稀释部分; 和（i）收集上清液。步骤（e）至（g）可以根据需要经常重复。该方法还可以包括维持蔗糖的浓度。

8. 发明申请

US20070300096A1 Late Data Launch for a Double Data Rate Elastic Interface 失效
标题翻译：延迟数据启动双数据速率弹性接口
公开(公告)号：US20070300096A1
公开(公告)日：2007-12-27
申请号：US11426671
申请日：2006-06-27
申请人： Christopher J. Berry , Jonathan Y. Chen , Michael Fee , Patrick J. Meaney , Alan P. Wagstaff
发明人： Christopher J. Berry , Jonathan Y. Chen , Michael Fee , Patrick J. Meaney , Alan P. Wagstaff
IPC分类号： G06F1/12
CPC分类号： G06F13/4059
摘要： A double data rate interface in which the set-up interval is extended for a data path in which data is delayed relative to the other data path. Data is latched into a register comprised of mid cycle type latches, such as for example L2* latches. For example, if the delayed half of the data is not available until the second half of the double data rate cycle, the second half of the data is allowed to have a set-up interval around the mid cycle point while the on-chip timing logic launches the least delayed half of the data on the clock edge after it is set up, without waiting for the expiration of the set up interval of the delayed data.
摘要翻译：双数据速率接口，其中针对数据相对于另一数据路径延迟数据路径的设置间隔进行扩展。数据被锁存到由中间循环型锁存器组成的寄存器中，例如L2 *锁存器。例如，如果延迟的一半数据在双倍数据速率周期的下半部分之前不可用，则数据的后半部分被允许具有围绕中间周期点的建立间隔，同时片内定时在建立之后，逻辑在时钟沿启动最少延迟的一半数据，而不用等待延迟数据的设置间隔的到期。

9. 发明申请

US20070300032A1 Early Directory Access of A Double Data Rate Elastic Interface 失效
标题翻译：双数据速率弹性接口的早期目录访问
公开(公告)号：US20070300032A1
公开(公告)日：2007-12-27
申请号：US11426675
申请日：2006-06-27
申请人： Christopher J. Berry , Jonathan Y. Chen , Michael Fee , Patrick J. Meaney , Alan P. Wagstaff
发明人： Christopher J. Berry , Jonathan Y. Chen , Michael Fee , Patrick J. Meaney , Alan P. Wagstaff
IPC分类号： G06F13/00
CPC分类号： G06F13/4059 , G06F12/0855 , G06F12/0864
摘要： A system and method to organize and use data sent over a double data rate interface so that the system operation does not experience a time penalty. The first cycle of data is used independently of the second cycle so that latency is not jeopardized. There are many applications. In a preferred embodiment for an L2 cache, the system transmits congruence class data in the first half and can start to access the L2 cache directory with the congruence class data.
摘要翻译：一种用于组织和使用通过双数据速率接口发送的数据的系统和方法，使得系统操作不会经历时间惩罚。数据的第一个循环独立于第二个周期使用，以便等待时间不会受到损害。有很多应用程序。在L2高速缓存的优选实施例中，系统在前半部分发送同余类数据，并且可以开始以一致类数据访问L2高速缓存目录。

10. 发明申请

US20110173584A1 REDUCTION OF LOGIC AND DELAY THROUGH LATCH POLARITY INVERSION 有权
标题翻译：通过锁定极性反转来减少逻辑和延迟
公开(公告)号：US20110173584A1
公开(公告)日：2011-07-14
申请号：US12685803
申请日：2010-01-12
申请人： Jonathan Y. Chen , Jose L. Neves
发明人： Jonathan Y. Chen , Jose L. Neves
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： A method for reducing logic and delay within a logic structure that includes searching logic structures to be analyzed, finding a plurality of latches within a logic structure to be analyzed, determining if any respective latches of the plurality of latches have sufficiently positive slack within an input and output path thereof and optionally excluding the respective latches from being analyzed, determining if there is at least one remaining latch to be analyzed, and determining whether inverters are disposed within an input path and an output path of the at least one remaining latch. The method further includes obtaining logic functions of the input path and output path of the at least one remaining latch when inverters are found, modifying the logic functions using DeMorgan's Theorems, determining whether timing violations exist with the modified logic functions, and annotating hardware description language based on the modified logic functions when no timing violations exist.
摘要翻译：一种用于减少逻辑结构内的逻辑和延迟的方法，包括搜索待分析的逻辑结构，在要分析的逻辑结构内找到多个锁存器，确定多个锁存器中的任何相应的锁存器是否在输入内具有足够的正的松弛并且可选地排除相应的锁存器的分析，确定是否存在至少一个待分析的剩余锁存器，以及确定逆变器是否设置在所述至少一个剩余锁存器的输入路径和输出路径内。该方法还包括：当发现逆变器时获得至少一个剩余锁存器的输入路径和输出路径的逻辑功能，使用DeMorgan's定理修改逻辑功能，确定定时违反是否存在于修改后的逻辑功能上，以及注释硬件描述语言基于修改的逻辑功能，当没有定时违反时。

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