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1. 发明授权

US06754196B1 Method and apparatus for increasing the effective bandwidth within a digital wireless network 失效
标题翻译：用于增加数字无线网络内的有效带宽的方法和装置
公开(公告)号：US06754196B1
公开(公告)日：2004-06-22
申请号：US09063476
申请日：1998-04-20
申请人： John Daane , Michael D. Rostoker , Sandeep Jaggi
发明人： John Daane , Michael D. Rostoker , Sandeep Jaggi
IPC分类号： H04Q724
CPC分类号： H04W72/0453
摘要： A plurality of devices communicate information over a wireless network at radio frequencies. The information includes digital audio, video and data. Bandwidth among the devices is dynamically allocated, the allocation being based upon the needs of the devices. One embodiment of the wireless network is a Time Division Multiple Access network. Another embodiment is a wireless Ethernet. Yet another embodiment is a Frequency Division Multiplexed network.
摘要翻译：多个设备通过无线电频率的无线网络传送信息。信息包括数字音频，视频和数据。动态分配设备之间的带宽，根据设备的需要进行分配。无线网络的一个实施例是时分多址网络。另一个实施例是无线以太网。另一个实施例是频分复用网络。

2. 发明授权

US06418353B1 Automating photolithography in the fabrication of integrated circuits 失效
标题翻译：在制造集成电路时自动化光刻
公开(公告)号：US06418353B1
公开(公告)日：2002-07-09
申请号：US09064802
申请日：1998-04-22
申请人： Michael D. Rostoker , Nicholas F. Pasch , Ashok K. Kapoor
发明人： Michael D. Rostoker , Nicholas F. Pasch , Ashok K. Kapoor
IPC分类号： G06F1900
CPC分类号： G03F7/705 , G03F7/70433 , G03F7/70625
摘要： Automated photolithography of integrated circuit wafers is enabled with a processor connected to a Rayleigh derator, a form factor generator, a logic synthesizer, a layout generator, a lithography module and a wafer process. The Rayleigh derator receives manufacturing information resulting from yield data in the wafer process, and this manufacturing data is then used to derate the theoretical minimum feature size available for etching wafer masks given a known light source and object lens numerical aperture. This minimum feature size is then used by a form factor generator in sizing transistors in a net list to their smallest manufacturable size. A logic synthesizer then converts the net list into a physical design using a layout generator combined with user defined constraints. This physical design is then used by the mask lithography module to generate wafer masks for use in the semiconductor manufacturing. Manufacturing data including process and. yield parameters is then transferred back to the Rayleigh processor for use in the designing of subsequent circuits. In this way, a direct coupling exists between the measurement of wafer process parameters and the automated sizing of semiconductor devices, enabling the production of circuits having the smallest manufacturable device sizes available for the given lithography and wafer process.
摘要翻译：集成电路晶片的自动光刻可通过连接到瑞利分离器，形状因子发生器，逻辑合成器，布局发生器，光刻模块和晶片工艺的处理器来实现。 Rayleigh变矩器接收由晶片工艺中的屈服数据产生的制造信息，然后使用该制造数据降低可用于蚀刻具有已知光源和物镜数值孔径的晶片掩模的理论最小特征尺寸。然后，这种最小特征尺寸由形状因子发生器用于将网络列表中的晶体管调整到其最小可制造尺寸。然后，逻辑合成器将网络列表转换为使用布局生成器与用户定义的约束组合的物理设计。然后该掩模光刻模块将该物理设计用于半导体制造中使用的晶片掩模。制造数据包括流程和。然后将产量参数转移回瑞利处理器用于后续电路的设计。以这种方式，在晶片工艺参数的测量和半导体器件的自动化尺寸之间存在直接耦合，使得能够生产具有可用于给定光刻和晶片工艺的最小可制造器件尺寸的电路。

3. 发明授权

US06312980B1 Programmable triangular shaped device having variable gain 失效
标题翻译：具有可变增益的可编程三角形器件
公开(公告)号：US06312980B1
公开(公告)日：2001-11-06
申请号：US09092827
申请日：1998-06-05
申请人： Michael D. Rostoker , James S. Koford , Ranko Scepanovic , Edwin R. Jones , Gobi R. Padmanahben , Ashok K. Kapoor , Valeriv B. Kudryavtsev , Alexander E. Andreev , Stanislav V. Aleshin , Alexander S. Podkolzin
发明人： Michael D. Rostoker , James S. Koford , Ranko Scepanovic , Edwin R. Jones , Gobi R. Padmanahben , Ashok K. Kapoor , Valeriv B. Kudryavtsev , Alexander E. Andreev , Stanislav V. Aleshin , Alexander S. Podkolzin
IPC分类号： H01L2182
CPC分类号： H01L27/108 , G06F17/5072 , G06F17/5077 , G11C5/025 , G11C5/063 , H01L23/528 , H01L27/11 , H01L27/1104 , H01L27/11807 , H01L29/0657 , H01L2924/0002 , Y10S438/965 , H01L2924/00
摘要： Several inventions are disclosed. A cell architecture using hexagonal shaped cells is disclosed. The architecture is not limited to hexagonal shaped cells. Cells may be defined by clusters of two or more hexagons, by triangles, by parallelograms, and by other polygons enabling a variety of cell shapes to be accommodated. Polydirectional non-orthogonal three layer metal routing is disclosed. The architecture may be combined with the tri-directional routing for a particularly advantageous design. In the tri-directional routing arraingement, electrical conductors for interconnecting terminals of microelectronic cells of an integrated circuit preferrably extend in three directions that are angularly displaced from each other by 60°. The conductors that extend in the three directions are preferrably formed in three different layers. A method of minimizing wire length in a semiconductor device is disclosed. A method of minimizing intermetal capacitance in a semiconductor device is disclosed. A novel device called a “tri-ister” is disclosed. Triangular devices are disclosed, including triangular NAND gates, triangular AND gates, and triangular OR gates. A triangular op amp and triode are disclosed. A triangular sense amplifier is disclosed. A DRAM memory array and an SRAM memory array, based upon triangular or parallelogram shaped cells, are disclosed, including a method of interconnecting such arrays. A programmable variable drive transistor is disclosed. CAD algorithms and methods are disclosed for designing and making semiconductor devices, which are particularly applicable to the disclosed architecture and tri-directional three metal layer routing.
摘要翻译：披露了几个发明。公开了一种使用六角形电池的电池结构。该体系结构不限于六角形细胞。单元可以由两个或更多个六边形的簇，通过三角形，平行四边形以及能够容纳各种单元格形状的其他多边形来定义。公开了多向非正交三层金属布线。该架构可以与三向路由组合以用于特别有利的设计。在三向布线布线中，用于集成电路的微电子单元的互连端子的电导体优选地在彼此成角度地移位60°的三个方向上延伸。沿三个方向延伸的导体优选地以三个不同的层形成。公开了一种使半导体器件中的导线长度最小化的方法。公开了一种使半导体器件中的金属间电容最小化的方法。公开了一种称为“三元器件”的新型器件。公开了三角形器件，包括三角形与非门，三角形与门和三角形或门。公开了三角形运算放大器和三极管。公开了三角形读出放大器。公开了一种基于三角形或平行四边形形状的单元的DRAM存储器阵列和SRAM存储器阵列，其包括互连这种阵列的方法。公开了一种可编程可变驱动晶体管。公开了用于设计和制造半导体器件的CAD算法和方法，其特别适用于所公开的架构和三向三金属层布线。

4. 发明授权

US5914955A Switched network hub on a chip 失效
标题翻译：交换网络集线器在芯片上
公开(公告)号：US5914955A
公开(公告)日：1999-06-22
申请号：US412861
申请日：1995-03-28
申请人： Michael D. Rostoker , John P. Daane , Sanjay Desai , D. Tony Stelliga
发明人： Michael D. Rostoker , John P. Daane , Sanjay Desai , D. Tony Stelliga
IPC分类号： G06F13/12 , H04L12/26 , H04L12/403 , H04L12/56 , H04N5/00 , H04N7/24 , H04N7/26 , H04N7/50 , H04Q11/04 , H04L12/40
CPC分类号： G06F13/128 , H04L12/2602 , H04L12/40032 , H04L12/5601 , H04L12/5602 , H04L43/00 , H04L45/745 , H04L47/10 , H04L47/11 , H04L47/263 , H04L49/109 , H04L49/206 , H04L49/25 , H04L49/3081 , H04L49/355 , H04L49/501 , H04L49/555 , H04L49/557 , H04L49/90 , H04L49/901 , H04L49/9057 , H04L49/9063 , H04L49/9078 , H04L49/9094 , H04N19/00 , H04N19/42 , H04N19/61 , H04N21/2381 , H04N21/4143 , H04N21/4305 , H04N21/437 , H04N21/4381 , H04N21/4385 , H04N21/4788 , H04N21/64 , H04N21/64307 , H04Q11/0478 , H04L2012/5613 , H04L2012/5614 , H04L2012/5616 , H04L2012/5628 , H04L2012/5632 , H04L2012/5635 , H04L2012/5636 , H04L2012/5637 , H04L2012/5638 , H04L2012/5647 , H04L2012/5652 , H04L2012/5653 , H04L2012/5664 , H04L2012/5681 , H04L43/0817 , H04L43/0852 , H04L43/10 , H04L43/106 , H04L49/20 , H04L49/30 , H04L49/3009 , H04L49/505 , H04N19/70 , H04Q2213/13034 , H04Q2213/13097 , H04Q2213/13141 , H04Q2213/13174 , H04Q2213/13204 , H04Q2213/13216 , H04Q2213/13296 , H04Q2213/13322 , H04Q2213/13332 , H04Q2213/13353
摘要： A network adapter formed on a single semiconductor substrate. The network adapter includes a host bus interface circuit adapted to be connected to a host data bus. A buffer memory is connected to the host bus interface circuit and temporarily stores digital information received from the host data bus. The digital information received from the host data bus are reformatted into packets according to a network protocol by a reformatting circuits. A processor and a network interface circuit are connected to the reformatting circuits. The processor controls the reformatting of the digital information. The network interface circuit is adapted to be connected to a digital network employing the network protocol.
摘要翻译：形成在单个半导体衬底上的网络适配器。网络适配器包括适于连接到主机数据总线的主机总线接口电路。缓冲存储器连接到主机总线接口电路，并临时存储从主机数据总线接收的数字信息。从主机数据总线接收的数字信息通过重新格式化电路根据网络协议重新格式化为数据包。处理器和网络接口电路连接到重新格式化电路。处理器控制数字信息的重新格式化。网络接口电路适于使用网络协议连接到数字网络。

5. 发明授权

US5874327A Fabricating a semiconductor device using precursor CMOS semiconductor substrate of a given configuration 失效
标题翻译：使用给定配置的前驱CMOS半导体衬底制造半导体器件
公开(公告)号：US5874327A
公开(公告)日：1999-02-23
申请号：US711283
申请日：1996-09-09
申请人： Michael D. Rostoker , Nicholas F. Pasch
发明人： Michael D. Rostoker , Nicholas F. Pasch
IPC分类号： H01L21/266 , H01L21/3105 , H01L21/8238
CPC分类号： H01L21/31051 , H01L21/266 , H01L21/3105 , H01L21/31053 , H01L21/823871 , Y10S438/981
摘要： Methods of planarizing one or more layers having an irregular top surface topology in a semiconductor device based on an underlying MOS structure are disclosed. Methods of creating doped wells or regions for the underlying MOS structure are also disclosed, using thick oxide growths on the surface of the substrate to mask implantation of ions into the wells. A technique for creating a pair of adjacent complementary oppositely-doped wells, such as for a CMOS structure, using a thick oxide growths as a mask is also disclosed. One of the methods of planarizing the one or more layers involves depositing, densifying and re-flowing a layer of glass on top of the topological layer. Another method of planarizing the one or more layers involves depositing, densifying and chemical-mechanically polishing the deposited and densified glass, thereby avoiding an additional temperature cycle (i.e., for re-flowing the glass) which would adversely affect underlying diffusions.
摘要翻译：公开了基于下面的MOS结构在半导体器件中平面化具有不规则顶表面拓扑的一个或多个层的方法。还公开了为底层MOS结构产生掺杂阱或区域的方法，其使用在衬底表面上的厚氧化物生长来掩蔽将离子注入到阱中。还公开了一种用于产生一对相邻的互补相对掺杂阱的技术，例如使用厚氧化物生长作为掩模的CMOS结构。对一个或多个层进行平坦化的方法之一包括在拓扑层顶部沉积，致密化和再流动玻璃层。平面化一个或多个层的另一种方法包括沉积，致密化和化学机械抛光沉积的和致密化的玻璃，从而避免对底层扩散产生不利影响的附加温度循环（即，用于重新流动玻璃）。

6. 发明授权

US5870313A Optimization processing for integrated circuit physical design automation system using parallel moving windows 失效
标题翻译：使用平行移动窗口的集成电路物理设计自动化系统的优化处理
公开(公告)号：US5870313A
公开(公告)日：1999-02-09
申请号：US987865
申请日：1997-12-09
申请人： Douglas B. Boyle , James S. Koford , Ranko Scepanovic , Edwin R. Jones , Michael D. Rostoker
发明人： Douglas B. Boyle , James S. Koford , Ranko Scepanovic , Edwin R. Jones , Michael D. Rostoker
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： One or more non-overlapping moving windows are positioned over a placement of cells for an integrated circuit chip to delineate respective subsets of cells. A fitness improvement operation such as simulated evolution is performed on the subsets simultaneously using parallel processors. The windows are either moved to specifically identified high interconnect congestion areas of the placement, or are moved across the placement in a raster type pattern such that each area of the placement is processed at least once. Exchange of misplaced cells between subsets can be accomplished by dimensioning the windows and designing the window movement pattern such that the subsets overlap. Alternatively, such exchange can be accomplished by using two sets of windows of different sizes. As yet another alternative, the improvement operation can allow misplaced cells to move to a border area outside a window. Each misplaced cell is placed on a list, and then moved to the centroid of a net of cells to which it is connected, which can be outside the subset that originally included the misplaced cell.
摘要翻译：一个或多个非重叠移动窗口位于用于集成电路芯片的单元的放置上以描绘相应的单元子集。使用并行处理器同时对子集执行诸如模拟演化的健身改善操作。窗口被移动到该位置的专门识别的高互连拥塞区域，或以栅格类型模式移动到该位置，使得该位置的每个区域至少被处理一次。可以通过对窗口进行尺寸设计和设计窗口移动图案以使得子集重叠来实现子集之间的错放单元的交换。或者，这种交换可以通过使用两组不同大小的窗口来完成。作为另一替代方案，改进操作可以允许错放的单元移动到窗外的边界区域。每个放错的单元格放在一个列表上，然后移动到它所连接的单元格网格的质心，它可能在最初包含放错单元格的子集之外。

7. 发明授权

US5838904A Random number generating apparatus for an interface unit of a carrier sense with multiple access and collision detect (CSMA/CD) ethernet data network 失效
标题翻译：用于具有多路访问和冲突检测（CSMA / CD）以太网数据网络的载波侦听接口单元的随机数生成装置
公开(公告)号：US5838904A
公开(公告)日：1998-11-17
申请号：US847717
申请日：1997-04-28
申请人： Michael D. Rostoker , D. Tony Stelliga , Dave Paolino , Willem A. H. Engelse
发明人： Michael D. Rostoker , D. Tony Stelliga , Dave Paolino , Willem A. H. Engelse
IPC分类号： G06F7/58 , H04L12/413 , H04L12/46 , H04L12/56 , H04Q11/04 , G06F13/36
CPC分类号： H04L12/413 , G06F7/584 , H04L12/4608 , H04Q11/0478 , G06F2207/581 , G06F2207/583 , H04L2012/5615 , H04L2012/5616 , H04L2012/5618 , H04L2012/5652 , H04L2012/5653
摘要： A random number generating apparatus for an interface unit of a Carrier Sense with Multiple Access and Collision Detect (CSMA/CD) Ethernet data network. The interface unit includes a transmit backoff unit for implementing a backoff algorithm in response to a network collision signal and a random number. The apparatus comprises a dual mode random number generator and a multiplexer for switching the random number generator between modes in accordance with the serial address bits of a data packet being processed by the interface unit. The random number generator includes a 25 stage linear feedback shift register. The multiplexer has two signal inputs connected to outputs of the 18th and 22nd stages of the shift register respectively, a switch input connected to receive the serial address bits and an output connected in circuit to an input of the shift register.
摘要翻译：一种用于具有多路访问和冲突检测（CSMA / CD）以太网数据网络的载波侦听接口单元的随机数生成装置。接口单元包括用于响应于网络冲突信号和随机数实现退避算法的发送回退单元。该装置包括双模随机数发生器和多路复用器，用于根据由接口单元正在处理的数据分组的串行地址位来在模式之间切换随机数发生器。随机数发生器包括一个25级线性反馈移位寄存器。复用器具有分别连接到移位寄存器的第18和第22级的输出端的两个信号输入端，连接到接收串行地址位的开关输入端和连接到移位寄存器的输入端的输出端。

8. 发明授权

US5832279A Advanced programmable interrupt controller (APIC) with high speed serial data bus 失效
标题翻译：高级可编程中断控制器（APIC），具有高速串行数据总线
公开(公告)号：US5832279A
公开(公告)日：1998-11-03
申请号：US863373
申请日：1997-05-27
申请人： Michael D. Rostoker , Sushant Verman , Richard Egan , Jerry Chow
发明人： Michael D. Rostoker , Sushant Verman , Richard Egan , Jerry Chow
IPC分类号： G06F9/48 , G06F13/24 , G06F9/46
CPC分类号： G06F9/4812 , G06F13/24 , Y02B60/1228 , Y02B60/144
摘要： A high speed Advanced Programmable Interrupt Controller (APIC) system includes a plurality of local units for prioritizing and passing interrupts, an Input/Output (I/O) unit for feeding interrupts to the local units, and a serial link data transmission system for interconnecting the I/O unit and the local units. The I/O unit and each local unit have a parallel I/O interface. The serial link transmission system includes a parallel signal bus connected to the parallel I/O interface of the I/O unit; a plurality of first serial link transceivers having parallel I/O interfaces connected to the parallel signal bus, and serial I/O interfaces respectively; a plurality of second serial link transceivers having parallel I/O interfaces connected to the parallel I/O interfaces of the local units, and serial I/O interfaces respectively; and a plurality of serial transmission lines interconnecting the serial I/O interfaces of first serial link transceivers and the serial I/O interfaces of second serial link transceivers respectively.
摘要翻译：高速高级可编程中断控制器（APIC）系统包括用于对中断进行优先排序和通过的多个本地单元，用于向本地单元馈送中断的输入/输出（I / O）单元和用于互连的串行链路数据传输系统 I / O单元和本地单元。 I / O单元和本地单元具有并行I / O接口。串行链路传输系统包括连接到I / O单元的并行I / O接口的并行信号总线; 具有分别连接到并行信号总线和串行I / O接口的并行I / O接口的多个第一串行链路收发器; 具有连接到本地单元的并行I / O接口的并行I / O接口的多个第二串行链路收发器和串行I / O接口; 以及分别将第一串行链路收发器的串行I / O接口和第二串行链路收发器的串行I / O接口互连的多个串行传输线。

9. 发明授权

US5815403A Fail-safe distributive processing method for producing a highest fitness cell placement for an integrated circuit chip 失效
标题翻译：用于产生用于集成电路芯片的最佳适应度单元布局的故障安全分配处理方法
公开(公告)号：US5815403A
公开(公告)日：1998-09-29
申请号：US229954
申请日：1994-04-19
申请人： Edwin R. Jones , James S. Koford , Douglas B. Boyle , Ranko Scepanovic , Michael D. Rostoker
发明人： Edwin R. Jones , James S. Koford , Douglas B. Boyle , Ranko Scepanovic , Michael D. Rostoker
IPC分类号： G06F9/50 , G06F17/50
CPC分类号： G06F9/5033 , G06F17/5072 , G06F2209/5017
摘要： A physical design automation system for producing a highest fitness cell placement for an integrated circuit chip includes a decomposition/recomposition processor for decomposing a cell placement optimization process into a plurality of tasks and recomposing the highest fitness cell placement from results of performing the tasks. A plurality of worker processors independently perform the tasks and produce results. A host processor distributively assigns the tasks to the worker processors in response to work requests received therefrom. Each worker processor sends a work request to the host processor after completing a task. The host processor maintains a list of unassigned tasks, assigned tasks and completed tasks, and revises the list to redesignate assigned tasks as unassigned tasks upon determining that the list includes no unassigned tasks and at least one assigned task, thus making the system immune to the failure of one or more processors.
摘要翻译：用于产生用于集成电路芯片的最佳适应度单元布置的物理设计自动化系统包括分解/重组处理器，用于将小区布置优化过程分解成多个任务，并且从执行任务的结果重新构建最佳适合度单元布局。多个工作者处理器独立执行任务并产生结果。主机处理器响应于从其接收到的工作请求，向任务处理器分配任务。完成任务后，每个工作处理器向主处理器发送工作请求。主处理器维护未分配任务，分配的任务和完成的任务的列表，并且在确定列表不包含未分配的任务和至少一个分配的任务时，修改列表以重新指定被分配的任务作为未分配的任务，从而使系统免受一个或多个处理器的故障。

10. 发明授权

US5777374A Integrated circuit interconnect structure with back reflection suppressing electronic "speed bumps" 失效
公开(公告)号：US5777374A
公开(公告)日：1998-07-07
申请号：US578324
申请日：1995-12-26
申请人： Michael D. Rostoker , Nicholas F. Pasch
发明人： Michael D. Rostoker , Nicholas F. Pasch
IPC分类号： H01L23/522 , H01L29/00 , H01L23/48 , H01L23/52 , H01L23/58
CPC分类号： H01L23/522 , H01L23/5222 , H01L2924/0002 , H01L2924/3011
摘要： A polysilicon interconnect is formed on a microelectronic circuit substrate for conducting signals from a driver to a non-polycrystalline silicon contact which has higher impedance than the interconnect. A plurality of electronic "speed bumps" are spaced along the interconnect for disturbing or disrupting signals propagating along the interconnect toward the contact and thereby reducing undesirable back reflection and ringing. The speed bumps can include capacitance altering elements in the form of dielectric strips, or resistance altering elements in the form of low resistance doped areas or high resistance amorphous areas. The speed bumps can include first and second elements having different values of capacitance or resistance which are spaced along the interconnect in alternating relation.

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