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1. 发明授权

US5663076A Automating photolithography in the fabrication of integrated circuits 失效
标题翻译：在制造集成电路时自动化光刻
公开(公告)号：US5663076A
公开(公告)日：1997-09-02
申请号：US512678
申请日：1995-08-08
申请人： Michael D. Rostoker , Nicholas F. Pasch , Ashok K. Kapoor
发明人： Michael D. Rostoker , Nicholas F. Pasch , Ashok K. Kapoor
IPC分类号： G03F7/20 , H01L21/66
CPC分类号： G03F7/705 , G03F7/20 , G03F7/70433
摘要： Automated photolithography of integrated circuit wafers is enabled with a processor connected to a Rayleigh derator, a form factor generator, a logic synthesizer, a layout generator, a lithography module and a wafer process. The Rayleigh derator receives manufacturing information resulting from yield data in the wafer process, and this manufacturing data is then used to derate the theoretical minimum feature size available for etching wafer masks given a known light source and object lens numerical aperture. This minimum feature size is then used by a form factor generator in sizing transistors in a net list to their smallest manufacturable size. A logic synthesizer then converts the net list into a physical design using a layout generator combined with user defined constraints. This physical design is then used by the mask lithography module to generate wafer masks for use in the semiconductor manufacturing. Manufacturing data including process and yield parameters is then transferred back to the Rayleigh processor for use in the designing of subsequent circuits. In this way, a direct coupling exists between the measurement of wafer process parameters and the automated sizing of semiconductor devices, enabling the production of circuits having the smallest manufacturable device sizes available for the given lithography and wafer process.
摘要翻译：集成电路晶片的自动光刻可通过连接到瑞利分离器，形状因子发生器，逻辑合成器，布局发生器，光刻模块和晶片工艺的处理器来实现。 Rayleigh变矩器接收由晶片工艺中的屈服数据产生的制造信息，然后使用该制造数据降低可用于蚀刻具有已知光源和物镜数值孔径的晶片掩模的理论最小特征尺寸。然后，这种最小特征尺寸由形状因子发生器用于将网络列表中的晶体管调整到其最小可制造尺寸。然后，逻辑合成器将网络列表转换为使用布局生成器与用户定义的约束组合的物理设计。然后该掩模光刻模块将该物理设计用于半导体制造中使用的晶片掩模。然后将包括处理和产量参数的制造数据传送回瑞利处理器，以用于后续电路的设计。以这种方式，在晶片工艺参数的测量和半导体器件的自动化尺寸之间存在直接耦合，使得能够生产具有可用于给定光刻和晶片工艺的最小可制造器件尺寸的电路。

2. 发明授权

US06418353B1 Automating photolithography in the fabrication of integrated circuits 失效
标题翻译：在制造集成电路时自动化光刻
公开(公告)号：US06418353B1
公开(公告)日：2002-07-09
申请号：US09064802
申请日：1998-04-22
申请人： Michael D. Rostoker , Nicholas F. Pasch , Ashok K. Kapoor
发明人： Michael D. Rostoker , Nicholas F. Pasch , Ashok K. Kapoor
IPC分类号： G06F1900
CPC分类号： G03F7/705 , G03F7/70433 , G03F7/70625
摘要： Automated photolithography of integrated circuit wafers is enabled with a processor connected to a Rayleigh derator, a form factor generator, a logic synthesizer, a layout generator, a lithography module and a wafer process. The Rayleigh derator receives manufacturing information resulting from yield data in the wafer process, and this manufacturing data is then used to derate the theoretical minimum feature size available for etching wafer masks given a known light source and object lens numerical aperture. This minimum feature size is then used by a form factor generator in sizing transistors in a net list to their smallest manufacturable size. A logic synthesizer then converts the net list into a physical design using a layout generator combined with user defined constraints. This physical design is then used by the mask lithography module to generate wafer masks for use in the semiconductor manufacturing. Manufacturing data including process and. yield parameters is then transferred back to the Rayleigh processor for use in the designing of subsequent circuits. In this way, a direct coupling exists between the measurement of wafer process parameters and the automated sizing of semiconductor devices, enabling the production of circuits having the smallest manufacturable device sizes available for the given lithography and wafer process.
摘要翻译：集成电路晶片的自动光刻可通过连接到瑞利分离器，形状因子发生器，逻辑合成器，布局发生器，光刻模块和晶片工艺的处理器来实现。 Rayleigh变矩器接收由晶片工艺中的屈服数据产生的制造信息，然后使用该制造数据降低可用于蚀刻具有已知光源和物镜数值孔径的晶片掩模的理论最小特征尺寸。然后，这种最小特征尺寸由形状因子发生器用于将网络列表中的晶体管调整到其最小可制造尺寸。然后，逻辑合成器将网络列表转换为使用布局生成器与用户定义的约束组合的物理设计。然后该掩模光刻模块将该物理设计用于半导体制造中使用的晶片掩模。制造数据包括流程和。然后将产量参数转移回瑞利处理器用于后续电路的设计。以这种方式，在晶片工艺参数的测量和半导体器件的自动化尺寸之间存在直接耦合，使得能够生产具有可用于给定光刻和晶片工艺的最小可制造器件尺寸的电路。

3. 再颁专利

USRE38900E1 Automating photolithography in the fabrication of integrated circuits 有权
标题翻译：在制造集成电路时自动化光刻
公开(公告)号：USRE38900E1
公开(公告)日：2005-11-29
申请号：US09273171
申请日：1999-03-19
申请人： Michael D. Rostoker , Nicholas F. Pasch , Ashok K. Kapoor
发明人： Michael D. Rostoker , Nicholas F. Pasch , Ashok K. Kapoor
IPC分类号： G03F7/20 , H01L21/66
CPC分类号： G03F7/705 , G03F7/20 , G03F7/70433
摘要： Automated photolithography of integrated circuit wafers is enabled with a processor connected to a Rayleigh derator, a form factor generator, a logic synthesizer, a layout generator, a lithography module and a wafer process. The Rayleigh derator receives manufacturing information resulting from yield data in the wafer process, and this manufacturing data is then used to derate the theoretical minimum feature size available for etching wafer masks given a known light source and object lens numerical aperture. This minimum feature size is then used by a form factor generator in sizing transistors in a net list to their smallest manufacturable size. A logic synthesizer then converts the net list into a physical design using a layout generator combined with user defined constraints. This physical design is then used by the mask lithography module to generate wafer masks for use in the semiconductor manufacturing. Manufacturing data including process and yield parameters is then transferred back to the Rayleigh processor for use in the designing of subsequent circuits. In this way, a direct coupling exists between the measurement of wafer process parameters and the automated sizing of semiconductor devices, enabling the production of circuits having the smallest manufacturable device sizes available for the given lithography and wafer process.
摘要翻译：集成电路晶片的自动光刻可通过连接到瑞利分离器，形状因子发生器，逻辑合成器，布局发生器，光刻模块和晶片工艺的处理器来实现。 Rayleigh变矩器接收由晶片工艺中的屈服数据产生的制造信息，然后使用该制造数据降低可用于蚀刻具有已知光源和物镜数值孔径的晶片掩模的理论最小特征尺寸。然后，这种最小特征尺寸由形状因子发生器用于将网络列表中的晶体管调整到其最小可制造尺寸。然后，逻辑合成器将网络列表转换为使用布局生成器与用户定义的约束组合的物理设计。然后该掩模光刻模块将该物理设计用于半导体制造中使用的晶片掩模。然后将包括处理和产量参数的制造数据传送回瑞利处理器，以用于后续电路的设计。以这种方式，在晶片工艺参数的测量和半导体器件的自动化尺寸之间存在直接耦合，使得能够生产具有可用于给定光刻和晶片工艺的最小可制造器件尺寸的电路。

4. 发明授权

US5393712A Process for forming low dielectric constant insulation layer on integrated circuit structure 失效
标题翻译：在集成电路结构上形成低介电常数绝缘层的工艺
公开(公告)号：US5393712A
公开(公告)日：1995-02-28
申请号：US84829
申请日：1993-06-28
申请人： Michael D. Rostoker , Nicholas F. Pasch , Ashok K. Kapoor
发明人： Michael D. Rostoker , Nicholas F. Pasch , Ashok K. Kapoor
IPC分类号： H01L21/316 , H01L21/768 , H01L21/02
CPC分类号： H01L21/02304 , H01L21/02129 , H01L21/02203 , H01L21/02271 , H01L21/02343 , H01L21/02362 , H01L21/31695 , H01L21/76801 , H01L21/7682 , H01L21/76832 , H01L21/76829 , H01L2221/1047
摘要： A process is described for forming a low dielectric constant insulation layer on an integrated circuit structure on a semiconductor wafer by first forming a composite layer, comprising one or more extractable materials and one or more matrix-forming insulation materials, over an integrated circuit structure on a semiconductor wafer, and then selectively removing the extractable material from the matrix-forming material without damaging the remaining matrix material, thereby leaving behind a porous matrix of the insulation material. In one embodiment, the composite layer is formed from a gel. The extractable material is removed by first dissolving it in a first liquid which is not a solvent for the matrix-forming material to form a solution. This solution is then removed from the matrix-forming material by rinsing the matrix in a second liquid miscible with the first solvent and which also is not a solvent from the matrix-forming material. The second liquid is then preferably removed from the matrix-forming material either by lyophilizing (freeze drying) or by raising the pressure and temperature above the critical point of the second liquid.
摘要翻译：描述了一种用于在半导体晶片上的集成电路结构上形成低介电常数绝缘层的工艺，首先在集成电路结构上形成复合层，该复合层包括一种或多种可提取材料和一种或多种矩阵形成绝缘材料半导体晶片，然后从基质形成材料中选择性地除去可提取材料，而不损坏剩余的基体材料，从而留下绝缘材料的多孔基体。在一个实施方案中，复合层由凝胶形成。通过首先将其溶解在不是基质形成材料的溶剂形成溶液的第一液体中来除去可萃取材料。然后通过在与第一溶剂混溶的第二液体中冲洗基质并且也不是基质形成材料的溶剂，从基质形成材料中除去该溶液。然后优选通过冻干（冷冻干燥）或通过将压力和温度升高到高于第二液体的临界点的方式从基质形成材料中除去第二液体。

5. 发明授权

US06312980B1 Programmable triangular shaped device having variable gain 失效
标题翻译：具有可变增益的可编程三角形器件
公开(公告)号：US06312980B1
公开(公告)日：2001-11-06
申请号：US09092827
申请日：1998-06-05
申请人： Michael D. Rostoker , James S. Koford , Ranko Scepanovic , Edwin R. Jones , Gobi R. Padmanahben , Ashok K. Kapoor , Valeriv B. Kudryavtsev , Alexander E. Andreev , Stanislav V. Aleshin , Alexander S. Podkolzin
发明人： Michael D. Rostoker , James S. Koford , Ranko Scepanovic , Edwin R. Jones , Gobi R. Padmanahben , Ashok K. Kapoor , Valeriv B. Kudryavtsev , Alexander E. Andreev , Stanislav V. Aleshin , Alexander S. Podkolzin
IPC分类号： H01L2182
CPC分类号： H01L27/108 , G06F17/5072 , G06F17/5077 , G11C5/025 , G11C5/063 , H01L23/528 , H01L27/11 , H01L27/1104 , H01L27/11807 , H01L29/0657 , H01L2924/0002 , Y10S438/965 , H01L2924/00
摘要： Several inventions are disclosed. A cell architecture using hexagonal shaped cells is disclosed. The architecture is not limited to hexagonal shaped cells. Cells may be defined by clusters of two or more hexagons, by triangles, by parallelograms, and by other polygons enabling a variety of cell shapes to be accommodated. Polydirectional non-orthogonal three layer metal routing is disclosed. The architecture may be combined with the tri-directional routing for a particularly advantageous design. In the tri-directional routing arraingement, electrical conductors for interconnecting terminals of microelectronic cells of an integrated circuit preferrably extend in three directions that are angularly displaced from each other by 60°. The conductors that extend in the three directions are preferrably formed in three different layers. A method of minimizing wire length in a semiconductor device is disclosed. A method of minimizing intermetal capacitance in a semiconductor device is disclosed. A novel device called a “tri-ister” is disclosed. Triangular devices are disclosed, including triangular NAND gates, triangular AND gates, and triangular OR gates. A triangular op amp and triode are disclosed. A triangular sense amplifier is disclosed. A DRAM memory array and an SRAM memory array, based upon triangular or parallelogram shaped cells, are disclosed, including a method of interconnecting such arrays. A programmable variable drive transistor is disclosed. CAD algorithms and methods are disclosed for designing and making semiconductor devices, which are particularly applicable to the disclosed architecture and tri-directional three metal layer routing.
摘要翻译：披露了几个发明。公开了一种使用六角形电池的电池结构。该体系结构不限于六角形细胞。单元可以由两个或更多个六边形的簇，通过三角形，平行四边形以及能够容纳各种单元格形状的其他多边形来定义。公开了多向非正交三层金属布线。该架构可以与三向路由组合以用于特别有利的设计。在三向布线布线中，用于集成电路的微电子单元的互连端子的电导体优选地在彼此成角度地移位60°的三个方向上延伸。沿三个方向延伸的导体优选地以三个不同的层形成。公开了一种使半导体器件中的导线长度最小化的方法。公开了一种使半导体器件中的金属间电容最小化的方法。公开了一种称为“三元器件”的新型器件。公开了三角形器件，包括三角形与非门，三角形与门和三角形或门。公开了三角形运算放大器和三极管。公开了三角形读出放大器。公开了一种基于三角形或平行四边形形状的单元的DRAM存储器阵列和SRAM存储器阵列，其包括互连这种阵列的方法。公开了一种可编程可变驱动晶体管。公开了用于设计和制造半导体器件的CAD算法和方法，其特别适用于所公开的架构和三向三金属层布线。

6. 发明授权

US5654563A Microelectronic integrated circuit including triangular semiconductor "or" g 失效
标题翻译：微电子集成电路包括三角半导体“或”门极器件“
公开(公告)号：US5654563A
公开(公告)日：1997-08-05
申请号：US567894
申请日：1995-12-06
申请人： Michael D. Rostoker , James S. Koford , Ranko Scepanovic , Edwin R. Jones , Gobi R. Padmanahben , Ashok K. Kapoor , Valeriy B. Kudryavtsev , Alexander E. Andreev , Stanislav V. Aleshin , Alexander S. Podkolzin
发明人： Michael D. Rostoker , James S. Koford , Ranko Scepanovic , Edwin R. Jones , Gobi R. Padmanahben , Ashok K. Kapoor , Valeriy B. Kudryavtsev , Alexander E. Andreev , Stanislav V. Aleshin , Alexander S. Podkolzin
IPC分类号： H01L23/528 , H01L27/088 , H01L29/06 , H01L29/78 , H01L25/00 , H01L29/772
CPC分类号： H01L29/0692 , H01L23/528 , H01L27/088 , H01L29/7831 , H01L2924/0002
摘要： A microelectronic integrated circuit includes a semiconductor substrate, and a plurality of microelectronic devices formed on the substrate. Each device has a periphery defined by a triangle, and includes an active area formed within the periphery, a central terminal formed in a central portion of the active area, and interconnected first to third terminals formed in the active area adjacent to vertices of the triangle respectively. First to third gates are formed between the first to third terminals respectively and the central terminal, and have contacts formed outside the active area adjacent to the sides of the triangle. The power supply connections to the central terminal and the first to third terminals, the conductivity type (NMOS or PMOS), and the addition of a pull-up or a pull-down resistor is selected for each device to provide a desired OR, NOR, AND or NAND function. One or two of the first to third terminals, rather than the central terminal, can be used for output to provide an AND/OR logic function. The devices are interconnected using three direction routing based on hexagonal geometry.
摘要翻译：微电子集成电路包括半导体衬底和形成在衬底上的多个微电子器件。每个装置具有由三角形限定的周边，并且包括形成在周边内的有效区域，形成在有源区域的中心部分中的中心端子，以及形成在与三角形顶点相邻的有源区域中的互连的第一至第三端子分别。第一至第三栅极分别形成在第一至第三端子和中心端子之间，并且具有形成在与三角形的侧面相邻的有源区域外部的触点。为每个器件选择与中心端子和第一至第三端子的电源连接，导电类型（NMOS或PMOS）以及上拉或下拉电阻的添加，以提供所需的OR，NOR ，AND或NAND功能。第一至第三终端中的一个或两个，而不是中心终端，可用于输出以提供与/或逻辑功能。这些设备使用基于六边形几何的三向路由进行互连。

7. 发明授权

US5650653A Microelectronic integrated circuit including triangular CMOS "nand" gate device 失效
标题翻译：微电子集成电路包括三角形CMOS“nand”门极器件
公开(公告)号：US5650653A
公开(公告)日：1997-07-22
申请号：US561107
申请日：1995-11-21
申请人： Michael D. Rostoker , James S. Koford , Ranko Scepanovic , Edwin R. Jones , Gobi R. Padmanahben , Ashok K. Kapoor , Valeriy B. Kudryavtsev , Alexander E. Andreev , Stanislav V. Aleshin , Alexander S. Podkolzin
发明人： Michael D. Rostoker , James S. Koford , Ranko Scepanovic , Edwin R. Jones , Gobi R. Padmanahben , Ashok K. Kapoor , Valeriy B. Kudryavtsev , Alexander E. Andreev , Stanislav V. Aleshin , Alexander S. Podkolzin
IPC分类号： H01L27/092 , H01L27/118 , H01L29/423 , H01L29/78 , H01L29/76 , H01L27/10 , H01L31/062 , H01L31/113
CPC分类号： H01L27/0922 , H01L27/11807 , H01L29/4238 , H01L29/7831
摘要： A microelectronic integrated circuit includes a semiconductor substrate, and a plurality of CMOS microelectronic devices formed on the substrate. Each device includes a triangular ANY element of a first conductivity type (PMOS or NMOS), and a triangular ALL element of a second conductivity type (NMOS or PMOS), the ANY and ALL elements each having a plurality of inputs and an output that are electrically interconnected respectively. The ANY element is basically an OR element, and the ALL element is basically an AND element. However, the power supply connections and the selection of conductivity type (NMOS or PMOS) for the ANY and ALL elements can be varied to provide the device as having a desired NAND, AND, NOR or OR configuration, in which the ANY element acts as a pull-up and the ALL element acts as a pull-down, or vice-versa.
摘要翻译：微电子集成电路包括半导体衬底和形成在衬底上的多个CMOS微电子器件。每个器件包括第一导电类型（PMOS或NMOS）的三角形ANY元件和第二导电类型（NMOS或PMOS）的三角形ALL元件，每个ANY和ALL元件都具有多个输入端和输出端电连接。 ANY元素基本上是一个OR元素，ALL元素基本上是AND元素。然而，可以改变ANY和ALL元件的电源连接和导电类型（NMOS或PMOS）的选择，以使器件具有所需的NAND，AND，NOR或OR配置，其中ANY元件作为上拉和ALL元素作为下拉，反之亦然。

8. 发明授权

US5640049A Metal interconnect structures for use with integrated circuit devices to form integrated circuit structures 失效
公开(公告)号：US5640049A
公开(公告)日：1997-06-17
申请号：US565766
申请日：1995-11-30
申请人： Michael D. Rostoker , Ashok K. Kapoor
发明人： Michael D. Rostoker , Ashok K. Kapoor
IPC分类号： H01L23/522 , H01L23/532 , H01L25/065 , H01L27/14 , H01L23/46 , H01L23/48 , H01L29/04
CPC分类号： H01L23/53223 , H01L23/5226 , H01L23/53242 , H01L23/53252 , H01L25/0657 , H01L2225/06513 , H01L2225/06541 , H01L2225/06593 , H01L2924/0002 , Y10S438/975
摘要： An integrated circuit structure is described wherein individual integrated circuit devices such as MOS or bipolar transistors are constructed on and in a semiconductor substrate and one or more layers of metal interconnects are constructed on and in a second substrate, preferably of similar thickness, and the two substrates are then aligned and bonded together to thereby provide electrical interconnections of individual integrated circuit devices on the semiconductor substrate with appropriate metal interconnects on the second substrate to provide the desired integrated circuit structure without, however, contributing unduly to the overall size of the integrated circuit structure comprising the die or chip. The one or more layers of metal interconnects are formed on the second substrate by the steps of forming a pattern of metal contacts in the second substrate and level with the surface of the substrate; forming a metal layer over the substrate, preferably of a different metal than the metal contacts; patterning the metal layer to form vias; forming a first layer of dielectric material on the surface of the substrate over the exposed portions of the metal contacts and around the metal vias; forming a further metal layer over the first layer of dielectric material and the metal vias, preferably using a different metal than used for the metal vias; patterning the further metal layer into metal interconnects; and depositing a second layer of dielectric material over the exposed portions of the first layer of dielectric material and around the metal interconnects. If desired, the steps of forming the vias and the layer of metal interconnects (as well as the associated dielectric layers) may be repeated as many times as desired or needed to form the desired number of metal interconnect layers for the needed wiring structure. In a preferred embodiment, over the uppermost metal layer is formed a layer of low melting alloy material (solder) prior to the step of patterning this metal layer to facilitate the electrical connection of the metal interconnect structure to low melting alloyable material (solder) formed over a corresponding structure of integrated circuit (semiconductor) devices formed on a semiconductor substrate.

9. 发明授权

US5742086A Hexagonal DRAM array 失效
标题翻译：六角形DRAM阵列
公开(公告)号：US5742086A
公开(公告)日：1998-04-21
申请号：US517153
申请日：1995-08-21
申请人： Michael D. Rostoker , James S. Koford , Ranko Scepanovic , Edwin R. Jones , Gobi R. Padmanahben , Ashok K. Kapoor , Valeriy B. Kudryavtsev , Alexander E. Andreev , Stanislav V. Aleshin , Alexander S. Podkolzin
发明人： Michael D. Rostoker , James S. Koford , Ranko Scepanovic , Edwin R. Jones , Gobi R. Padmanahben , Ashok K. Kapoor , Valeriy B. Kudryavtsev , Alexander E. Andreev , Stanislav V. Aleshin , Alexander S. Podkolzin
IPC分类号： G06F17/50 , G11C5/02 , G11C5/06 , H01L23/522 , H01L23/528 , H01L27/02 , H01L27/092 , H01L27/108 , H01L27/11 , H01L27/118 , H01L29/06 , H03K19/0944 , H03K19/0948 , H01L29/78 , H01L29/41
CPC分类号： G06F17/5072 , G06F17/5077 , G11C5/025 , G11C5/063 , H01L23/5222 , H01L23/528 , H01L27/0207 , H01L27/0922 , H01L27/108 , H01L27/11 , H01L27/1104 , H01L27/11807 , H03K19/09441 , H03K19/0948 , H01L29/0657 , H01L2924/0002
摘要： Several inventions are disclosed. A cell architecture using hexagonal shaped cells is disclosed. The architecture is not limited to hexagonal shaped cells. Cells may be defined by clusters of two or more hexagons, by triangles, by parallelograms, and by other polygons enabling a variety of cell shapes to be accommodated. Polydirectional non-orthogonal three layer metal routing is disclosed. The architecture may be combined with the tri-directional routing for a particularly advantageous design. In the tri-directional routing arraingement, electrical conductors for interconnecting terminals of microelectronic cells of an integrated circuit preferrably extend in three directions that are angularly displaced from each other by 60.degree.. The conductors that extend in the three directions are preferrably formed in three different layers. A method of minimizing wire length in a semiconductor device is disclosed. A method of minimizing intermetal capacitance in a semiconductor device is disclosed. A novel device called a "tri-ister" is disclosed. Triangular devices are disclosed, including triangular NAND gates, triangular AND gates, and triangular OR gates. A triangular op amp and triode are disclosed. A triangular sense amplifier is disclosed. A DRAM memory array and an SRAM memory array, based upon triangular or parallelogram shaped cells, are disclosed, including a method of interconnecting such arrays. A programmable variable drive transistor is disclosed. CAD algorithms and methods are disclosed for designing and making semiconductor devices, which are particularly applicable to the disclosed architecture and tri-directional three metal layer routing.
摘要翻译：披露了几个发明。公开了一种使用六角形电池的电池结构。该体系结构不限于六角形细胞。单元可以由两个或更多个六边形的簇，通过三角形，平行四边形以及能够容纳各种单元格形状的其他多边形来定义。公开了多向非正交三层金属布线。该架构可以与三向路由组合以用于特别有利的设计。在三向布线布置中，集成电路的微电子单元的互连端的电导体优选地在三个方向上相互延伸60°。沿三个方向延伸的导体优选地以三个不同的层形成。公开了一种使半导体器件中的导线长度最小化的方法。公开了一种使半导体器件中的金属间电容最小化的方法。公开了一种称为“三元器件”的新型器件。公开了三角形器件，包括三角形与非门，三角形与门和三角形或门。公开了三角形运算放大器和三极管。公开了三角形读出放大器。公开了一种基于三角形或平行四边形形状的单元的DRAM存储器阵列和SRAM存储器阵列，其包括互连这种阵列的方法。公开了一种可编程可变驱动晶体管。公开了用于设计和制造半导体器件的CAD算法和方法，其特别适用于所公开的架构和三向三金属层布线。

10. 发明授权

US5973376A Architecture having diamond shaped or parallelogram shaped cells 失效
标题翻译：具有菱形或平行四边形的细胞的建筑
公开(公告)号：US5973376A
公开(公告)日：1999-10-26
申请号：US517406
申请日：1995-08-21
申请人： Michael D. Rostoker , James S. Koford , Ranko Scepanovic , Edwin R. Jones , Gobi R. Padmanahben , Ashok K. Kapoor , Valeriy B. Kudryavtsev , Alexander E. Andreev , Stanislav V. Aleshin , Alexander S. Podkolzin
发明人： Michael D. Rostoker , James S. Koford , Ranko Scepanovic , Edwin R. Jones , Gobi R. Padmanahben , Ashok K. Kapoor , Valeriy B. Kudryavtsev , Alexander E. Andreev , Stanislav V. Aleshin , Alexander S. Podkolzin
IPC分类号： G06F17/50 , G11C5/02 , G11C5/06 , H01L23/522 , H01L23/528 , H01L27/02 , H01L27/092 , H01L27/108 , H01L27/11 , H01L27/118 , H01L29/06 , H03K19/0944 , H03K19/0948 , H01L31/352 , H01L23/52 , H01L29/78
CPC分类号： G06F17/5072 , G06F17/5077 , G11C5/025 , G11C5/063 , H01L23/5222 , H01L23/528 , H01L27/0207 , H01L27/0922 , H01L27/108 , H01L27/11 , H01L27/1104 , H01L27/11807 , H03K19/09441 , H03K19/0948 , H01L29/0657 , H01L2924/0002
摘要： Several inventions are disclosed. A cell architecture using hexagonal shaped cells is disclosed. The architecture is not limited to hexagonal shaped cells. Cells may be defined by clusters of two or more hexagons, by triangles, by parallelograms, and by other polygons enabling a variety of cell shapes to be accommodated. Polydirectional non-orthogonal three layer metal routing is disclosed. The architecture may be combined with the tri-directional routing for a particularly advantageous design. In the tri-directional routing arraingement, electrical conductors for interconnecting terminals of microelectronic cells of an integrated circuit preferrably extend in three directions that are angularly displaced from each other by 60.degree.. The conductors that extend in the three directions are preferrably formed in three different layers. A method of minimizing wire length in a semiconductor device is disclosed. A method of minimizing intermetal capacitance in a semiconductor device is disclosed. A novel device called a "tri-ister" is disclosed. Triangular devices are disclosed, including triangular NAND gates, triangular AND gates, and triangular OR gates. A triangular op amp and triode are disclosed. A triangular sense amplifier is disclosed. A DRAM memory array and an SRAM memory array, based upon triangular or parallelogram shaped cells, are disclosed, including a method of interconnecting such arrays. A programmable variable drive transistor is disclosed. CAD algorithms and methods are disclosed for designing and making semiconductor devices, which are particularly applicable to the disclosed architecture and tri-directional three metal layer routing.
摘要翻译：披露了几个发明。公开了一种使用六角形电池的电池结构。该体系结构不限于六角形细胞。单元可以由两个或更多个六边形的簇，通过三角形，平行四边形以及能够容纳各种单元格形状的其他多边形来定义。公开了多向非正交三层金属布线。该架构可以与三向路由组合以用于特别有利的设计。在三向布线布置中，集成电路的微电子单元的互连端的电导体优选地在三个方向上相互延伸60°。沿三个方向延伸的导体优选地以三个不同的层形成。公开了一种使半导体器件中的导线长度最小化的方法。公开了一种使半导体器件中的金属间电容最小化的方法。公开了一种称为“三元器件”的新型器件。公开了三角形器件，包括三角形与非门，三角形与门和三角形或门。公开了三角形运算放大器和三极管。公开了三角形读出放大器。公开了一种基于三角形或平行四边形形状的单元的DRAM存储器阵列和SRAM存储器阵列，其包括互连这种阵列的方法。公开了一种可编程可变驱动晶体管。公开了用于设计和制造半导体器件的CAD算法和方法，其特别适用于所公开的架构和三向三金属层布线。

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