专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5742510A Simultaneous placement and routing (SPAR) method for integrated circuit physical design automation system 失效
标题翻译：用于集成电路物理设计自动化系统的同时放置和布线（SPAR）方法
公开(公告)号：US5742510A
公开(公告)日：1998-04-21
申请号：US604181
申请日：1996-02-21
申请人： Michael D. Rostoker , James S. Koford , Edwin R. Jones , Douglas B. Boyle , Ranko Scepanovic
发明人： Michael D. Rostoker , James S. Koford , Edwin R. Jones , Douglas B. Boyle , Ranko Scepanovic
IPC分类号： G06F17/50 , G06F19/00
CPC分类号： G06F17/5072
摘要： In a physical design automation system for producing an optimized cell placement for an integrated circuit chip, a placement optimization methodology is decomposed into a plurality of cell placement optimization processes that are performed simultaneously by parallel processors on input data representing the chip. The results of the optimization processes are recomposed to produce an optimized cell placement. The fitness of the optimized cell placement is analyzed, and the parallel processors are controlled to selectively repeat performing the optimization processes for further optimizing the optimized cell placement if the fitness does not satisfy a predetermined criterion. The system can be applied to initial placement, routing, placement improvement and other problems. The processors can perform the same optimization process on different placements, or on areas of a single placement. Alternatively, the processors can perform different optimization processes simultaneously on a single initial placement, with the resulting processed placement having the highest fitness being selected as the optimized placement. The processors can further selectively reprocess areas of a placement having high cell interconnect congestion or other low fitness parameters.
摘要翻译：在用于生成用于集成电路芯片的优化的单元布置的物理设计自动化系统中，布局优化方法被分解成由并行处理器在表示芯片的输入数据上同时执行的多个单元布局优化处理。重组优化过程的结果以产生优化的细胞放置。分析优化的单元布局的适应性，并且如果适合度不满足预定标准，则并行处理器被控制以选择性地重复执行优化处理以进一步优化优化的单元布局。该系统可以应用于初始放置，布线，布局改进等问题。处理器可以对不同的展示位置或单个展示位置执行相同的优化过程。或者，处理器可以在单个初始放置上同时执行不同的优化过程，所得到的经处理的放置具有最佳适合度作为优化的位置。处理器可以进一步选择性地重新处理具有高单元互连拥塞或其他低适应度参数的位置的区域。

2. 发明授权

US5557533A Cell placement alteration apparatus for integrated circuit chip physical design automation system 失效
标题翻译：集成电路芯片物理设计自动化系统的电池放置改造装置
公开(公告)号：US5557533A
公开(公告)日：1996-09-17
申请号：US229821
申请日：1994-04-19
申请人： James S. Koford , Ranko Scepanovic , Edwin R. Jones , Douglas B. Boyle , Michael D. Rostoker
发明人： James S. Koford , Ranko Scepanovic , Edwin R. Jones , Douglas B. Boyle , Michael D. Rostoker
IPC分类号： G06F17/50 , G06F15/18
CPC分类号： G06F17/5072
摘要： A large number of possible placements of cells on an integrated circuit chip are generated and evaluated to determine the placement with the highest fitness. Cells for transposition or "swapping" within each placement using genetic algorithms are selected using greedy algorithms based on the fitness of each cell. The cell fitnesses are evaluated in terms of interconnect congestion, total net wire length or other criteria. Cells are selected for genetic crossover by sorting the cells in order of fitness and multiplying the cell fitnesses by weighting factors that increase non-linearly with rank. The cells are selected using linear random number generation such that cells with higher fitnesses have a higher probability of selection. Cells having lowest fitness are selected for mutation, and transposed to random locations, to adjacent locations, with cells having second worst fitness, to the center of mass of the respective interconnect nets, or with two or more cells in a cyclical manner.
摘要翻译：生成并评估集成电路芯片上大量可能的单元格放置，以确定具有最高适应度的位置。使用基于每个单元的适应度的贪心算法选择使用遗传算法在每个位置内进行转置或“交换”的单元。根据互连拥塞，总净线长度或其他标准来评估细胞适应度。选择细胞进行遗传交叉，通过按照适合度的顺序排列细胞，并通过与等级线性增加的加权因子乘以细胞适应度。使用线性随机数生成来选择细胞，使得具有较高适应度的细胞具有更高的选择概率。选择具有最低适应度的细胞用于突变，并且以周期性方式转置到随机位置，相邻位置，具有第二最坏适应度的细胞到相应互连网的质心，或者以两个或更多个细胞。

3. 发明授权

US06493658B1 Optimization processing for integrated circuit physical design automation system using optimally switched fitness improvement algorithms 失效
标题翻译：集成电路物理设计自动化系统优化处理采用最佳切换的健身改进算法
公开(公告)号：US06493658B1
公开(公告)日：2002-12-10
申请号：US08229616
申请日：1994-04-19
申请人： James S. Koford , Michael D. Rostoker , Edwin R. Jones , Douglas B. Boyle , Ranko Scepanovic
发明人： James S. Koford , Michael D. Rostoker , Edwin R. Jones , Douglas B. Boyle , Ranko Scepanovic
IPC分类号： G06F1750
CPC分类号： G06F17/5072
摘要： A physical design automation system produces an optimal placement of microelectronic components or cells on an integrate circuit chip. An initial population of possible cell placements is generated, and repeatedly altered using simulated on or other fitness improvement algorithm to progressively increase the fitnesses (decrease the costs) of the placements. After each alteration step, the fitnesses of the placements are calculated, and less fit placements are discarded in favor of more fit placements. After a termination criterion is reached, the placement having the highest fitness is designated as the optimal placement. Two or more fitness improvement algorithms are available, and are optimally switched from one to the other in accordance with an optimization criterion to maximize convergence of the placements toward the optimal configuration.
摘要翻译：物理设计自动化系统在集成电路芯片上产生微电子元件或单元的最佳布置。生成可能的单元格展示的初始种群，并使用模拟或其他适合度改进算法反复更改，以逐步增加展示位置的适应性（降低成本）。在每个更改步骤之后，计算展示位置的适用性，并且放弃较不适合的展示位置，以便更适合展示位置。达到终止标准后，具有最高适应度的位置被指定为最佳位置。两种或多种健身改进算法是可用的，并且根据优化标准将它们从一个优化地切换到另一个，以最大程度地将展示位置的收敛最大化到最佳配置。

4. 发明授权

US5875117A Simultaneous placement and routing (SPAR) method for integrated circuit physical design automation system 失效
标题翻译：用于集成电路物理设计自动化系统的同时放置和布线（SPAR）方法
公开(公告)号：US5875117A
公开(公告)日：1999-02-23
申请号：US636349
申请日：1996-04-23
申请人： Edwin R. Jones , James S. Koford , Douglas B. Boyle , Ranko Scepanovic , Michael D. Rostoker
发明人： Edwin R. Jones , James S. Koford , Douglas B. Boyle , Ranko Scepanovic , Michael D. Rostoker
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： An initial placement of cells for an integrated circuit chip is decomposed into a hierarchial order of groups of cells. The groups are routed simultaneously using parallel processors, and the results are recomposed to provide a global routing that provides a detailed mapping of cell interconnect congestion in the placement. Areas of high congestion are identified, and a congestion reduction algorithm is applied using the parallel processors to alter the placement in these areas simultaneously. The overall fitness of the placement is then computed, and if it has not attained a predetermined value, the steps of identifying congested areas and applying the congestion reduction algorithm to these areas are repeated. The cumulative error created by altering the placement without repeating the global routing is estimated, and if it exceeds a predetermined value, the global routing is also repeated.
摘要翻译：用于集成电路芯片的单元的初始放置被分解成单元组的分层次序。使用并行处理器同时路由组，并且重新构造结果以提供全局路由，其提供位置中的小区互连拥塞的详细映射。识别高拥塞的区域，并且使用并行处理器来应用拥塞减小算法来同时改变这些区域中的位置。然后计算放置的总体适应度，并且如果没有达到预定值，则重复识别拥挤区域并将这些区域应用拥塞减小算法的步骤。估计通过改变位置而不重复全局路由而产生的累积误差，并且如果超过预定值，则也重复全局路由。

5. 发明授权

US5793644A Cell placement alteration apparatus for integrated circuit chip physical design automation system 失效
公开(公告)号：US5793644A
公开(公告)日：1998-08-11
申请号：US724025
申请日：1996-09-17
申请人： James S. Koford , Ranko Scepanovic , Edwin R. Jones , Douglas B. Boyle , Michael D. Rostoker
发明人： James S. Koford , Ranko Scepanovic , Edwin R. Jones , Douglas B. Boyle , Michael D. Rostoker
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A large number of possible placements of cells on an integrated circuit chip are generated and evaluated to determine the placement with the highest fitness. Cells for transposition or "swapping" within each placement using genetic algorithms are selected using greedy algorithms based on the fitness of each cell. The cell fitnesses are evaluated in terms of interconnect congestion, total net wire length or other criteria. Cells are selected for genetic crossover by sorting the cells in order of fitness and multiplying the cell fitnesses by weighting factors that increase non-linearly with rank. The cells are selected using linear random number generation such that cells with higher fitnesses have a higher probability of selection. Cells having lowest fitness are selected for mutation, and transposed to random locations, to adjacent locations, with cells having second worst fitness, to the center of mass of the respective interconnect nets, or with two or more cells in a cyclical manner.

6. 发明授权

US5781439A Method for producing integrated circuit chip having optimized cell placement 失效
标题翻译：具有优化电池放置的集成电路芯片的制造方法
公开(公告)号：US5781439A
公开(公告)日：1998-07-14
申请号：US558165
申请日：1995-11-13
申请人： Michael D. Rostoker , James S. Koford , Edwin R. Jones , Douglas B. Boyle , Ranko Scepanovic
发明人： Michael D. Rostoker , James S. Koford , Edwin R. Jones , Douglas B. Boyle , Ranko Scepanovic
IPC分类号： G06F17/50 , G06F17/00
CPC分类号： G06F17/5072
摘要： In a physical design automation system for producing an optimized cell placement for an integrated circuit chip, a placement optimization methodology is decomposed into a plurality of cell placement optimization processes that are performed simultaneously by parallel processors on input data representing the chip. The results of the optimization processes are recomposed to produce an optimized cell placement. The fitness of the optimized cell placement is analyzed, and the parallel processors are controlled to selectively repeat performing the optimization processes for further optimizing the optimized cell placement if the fitness does not satisfy a predetermined criterion. The system can be applied to initial placement, routing, placement improvement and other problems. The processors can perform the same optimization process on different placements, or on areas of a single placement. Alternatively, the processors can perform different optimization processes simultaneously on a single initial placement, with the resulting processed placement having the highest fitness being selected as the optimized placement. The processors can further selectively reprocess areas of a placement having high cell interconnect congestion or other low fitness parameters.
摘要翻译：在用于生成用于集成电路芯片的优化的单元布置的物理设计自动化系统中，布局优化方法被分解成由并行处理器在表示芯片的输入数据上同时执行的多个单元布局优化处理。重组优化过程的结果以产生优化的细胞放置。分析优化的单元布局的适应性，并且如果适合度不满足预定标准，则并行处理器被控制以选择性地重复执行优化处理以进一步优化优化的单元布局。该系统可以应用于初始放置，布线，布局改进等问题。处理器可以对不同的展示位置或单个展示位置执行相同的优化过程。或者，处理器可以在单个初始放置上同时执行不同的优化过程，所得到的经处理的放置具有最佳适合度作为优化的位置。处理器可以进一步选择性地重新处理具有高单元互连拥塞或其他低适应度参数的位置的区域。

7. 发明授权

US5963975A Single chip integrated circuit distributed shared memory (DSM) and communications nodes 失效
标题翻译：单芯片集成电路分布式共享存储器（DSM）和通信节点
公开(公告)号：US5963975A
公开(公告)日：1999-10-05
申请号：US932042
申请日：1997-09-17
申请人： Douglas B. Boyle , James S. Koford , Edwin R. Jones , Ranko Scepanovic , Michael D. Rostoker
发明人： Douglas B. Boyle , James S. Koford , Edwin R. Jones , Ranko Scepanovic , Michael D. Rostoker
IPC分类号： G06F12/08 , G06F13/00
CPC分类号： G06F12/0817
摘要： The capacity of a cache memory is substantially reduced over that required for a multi-chip distributed shared memory (DSM) implementation to enable the cache memory, a main memory, a processor and requisite logic and control circuitry to fit on a single integrated circuit chip. The increased cache miss rate created by the reduced cache memory capacity is compensated for by the reduced cache miss resolution period resulting from integrating the main memory and processor on the single chip. The reduced cache miss resolution period enables the processor clock rate to be substantially increased, so that a processor having a simple functionality such as a reduced instruction set computer (RISC) processor can be utilized and still provide the required processing speed. The RISC processor is substantially smaller than a more complicated processor that would be required to provide the same processing speed in a multi-chip DSM implementation, thereby enabling the RISC processor to fit on the chip with the other elements. A single-chip communications node that can be used in telecommunications networks other than DSM includes a memory controller for providing local and remote memory coherency, and a bidirectional interconnect unit that converts memory access instructions into memory access messages and vice-versa.
摘要翻译：高速缓冲存储器的容量比多芯片分布式共享存储器（DSM）实现所需的容量大大减少，以使得高速缓冲存储器，主存储器，处理器和必需的逻辑和控制电路能够安装在单个集成电路芯片。由降低的高速缓存存储器容量创建的增加的高速缓存未命中率由通过在单个芯片上集成主存储器和处理器而减少的高速缓存未命中分辨率周期来补偿。减小的高速缓存未命中分辨率周期使得处理器时钟速率能够显着增加，使得可以利用具有简单功能的处理器，诸如精简指令集计算机（RISC）处理器，并且仍然提供所需的处理速度。 RISC处理器远小于在多芯片DSM实现中提供相同处理速度所需的更复杂的处理器，从而使RISC处理器能够与其他元件相配合。可以用于DSM以外的电信网络中的单芯片通信节点包括用于提供本地和远程存储器一致性的存储器控制器，以及将存储器访问指令转换为存储器访问消息的反向互连的双向互连单元。

8. 发明授权

US5903461A Method of cell placement for an integrated circuit chip comprising chaotic placement and moving windows 失效
标题翻译：一种集成电路芯片的电池放置方法，包括混沌放置和移动窗口
公开(公告)号：US5903461A
公开(公告)日：1999-05-11
申请号：US862791
申请日：1997-05-23
申请人： Michael D. Rostoker , James S. Koford , Edwin R. Jones , Douglas B. Boyle , Ranko Scepanovic
发明人： Michael D. Rostoker , James S. Koford , Edwin R. Jones , Douglas B. Boyle , Ranko Scepanovic
IPC分类号： G06F17/50 , G06F19/00
CPC分类号： G06F17/5072
摘要： In a physical design automation system for producing an optimized cell placement for an integrated circuit chip, a placement optimization methodology is decomposed into a plurality of cell placement optimization processes that are performed simultaneously by parallel processors on input data representing the chip. The results of the optimization processes are recomposed to produce an optimized cell placement. The fitness of the optimized cell placement is analyzed, and the parallel processors are controlled to selectively repeat performing the optimization processes for further optimizing the optimized cell placement if the fitness does not satisfy a predetermined criterion. The system can be applied to initial placement, routing, placement improvement and other problems. The processors can perform the same optimization process on different placements, or on areas of a single placement. Alternatively, the processors can perform different optimization processes simultaneously on a single initial placement, with the resulting processed placement having the highest fitness being selected as the optimized placement. The processors can further selectively reprocess areas of a placement having high cell interconnect congestion or other low fitness parameters.
摘要翻译：在用于生成用于集成电路芯片的优化的单元布置的物理设计自动化系统中，布局优化方法被分解成由并行处理器在表示芯片的输入数据上同时执行的多个单元布局优化处理。重组优化过程的结果以产生优化的细胞放置。分析优化的单元布局的适应性，并且如果适合度不满足预定标准，则并行处理器被控制以选择性地重复执行优化处理以进一步优化优化的单元布局。该系统可以应用于初始放置，布线，布局改进等问题。处理器可以对不同的展示位置或单个展示位置执行相同的优化过程。或者，处理器可以在单个初始放置上同时执行不同的优化过程，所得到的经处理的放置具有最佳适合度作为优化的位置。处理器可以进一步选择性地重新处理具有高单元互连拥塞或其他低适应度参数的位置的区域。

9. 发明授权

US5682322A Optimization processing for integrated circuit physical design automation system using chaotic fitness improvement method 失效
标题翻译：集成电路物理设计自动化系统优化处理采用混沌健身改进方法
公开(公告)号：US5682322A
公开(公告)日：1997-10-28
申请号：US229949
申请日：1994-04-19
申请人： Douglas B. Boyle , James S. Koford , Ranko Scepanovic , Edwin R. Jones , Michael D. Rostoker
发明人： Douglas B. Boyle , James S. Koford , Ranko Scepanovic , Edwin R. Jones , Michael D. Rostoker
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： The fitness of a cell placement for an integrated circuit chip is optimized by relocating at least some of cells to new locations that provide lower interconnect congestion. For each cell, the centroid of the net of cells to which the cell is connected is computed. The cell is then moved toward the centroid by a distance that is equal to the distance from the current position of the cell to the centroid multiplied by a "chaos" factor .lambda.. The value of .lambda. is selected such that the cell relocation operations will cause the placement to converge toward an optimal configuration without chaotic diversion, but with a sufficiently high chaotic element to prevent the optimization operation from becoming stuck at local fitness maxima. The new cell locations can be modified to include the effects of cells in other locations, such as by incorporating a function of cell density gradient or force direction into the computation. This spreads out clumps of cells so that the density of cells is more uniform throughout the placement. The attraction between cells in the nets is balanced against repulsion caused by a high local cell density, providing an optimized tradeoff of wirelength, feasibility and congestion.
摘要翻译：通过将至少一些单元重定位到提供较低互连拥塞的新位置来优化用于集成电路芯片的单元布局的适应性。对于每个单元，计算连接单元的单元格网格的质心。然后，电池向质心移动一个距离，该距离等于从电池的当前位置到质心乘以“混沌”因子λ的距离。选择λ的值，使得单元重定位操作将导致放置朝向最佳配置收敛而没有混沌转移，但是具有足够高的混沌元素以防止优化操作变得卡在局部适应度最大值。可以修改新的单元位置以将单元格的效果包括在其他位置，例如通过将单元密度梯度或力方向的函数合并到计算中。这扩散了细胞团，使得细胞的密度在整个放置期间更均匀。网络中的细胞之间的吸引力与由局部细胞密度较高引起的排斥平衡，从而提供了线长，可行性和拥塞的最优化折中。

10. 发明授权

US5636125A Computer implemented method for producing optimized cell placement for integrated circiut chip 失效
标题翻译：用于集成循环芯片生产优化的电池放置的计算机实现方法
公开(公告)号：US5636125A
公开(公告)日：1997-06-03
申请号：US559206
申请日：1995-11-13
申请人： Michael D. Rostoker , James S. Koford , Edwin R. Jones , Douglas B. Boyle , Ranko Scepanovic
发明人： Michael D. Rostoker , James S. Koford , Edwin R. Jones , Douglas B. Boyle , Ranko Scepanovic
IPC分类号： G06F17/50 , G06F19/00
CPC分类号： G06F17/5072
摘要： In a physical design automation system for producing an optimized cell placement for an integrated circuit chip, a placement optimization methodology is decomposed into a plurality of cell placement optimization processes that are performed simultaneously by parallel processors on input data representing the chip. The results of the optimization processes are recomposed to produce an optimized cell placement. The fitness of the optimized cell placement is analyzed, and the parallel processors are controlled to selectively repeat performing the optimization processes for further optimizing the optimized cell placement if the fitness does not satisfy a predetermined criterion. The system can be applied to initial placement, routing, placement improvement and other problems. The processors can perform the same optimization process on different placements, or on areas of a single placement. Alternatively, the processors can perform different optimization processes simultaneously on a single initial placement, with the resulting processed placement having the highest fitness being selected as the optimized placement. The processors can further selectively reprocess areas of a placement having high cell interconnect congestion or other low fitness parameters.
摘要翻译：在用于产生用于集成电路芯片的优化的单元布局的物理设计自动化系统中，布局优化方法被分解成由并行处理器在表示芯片的输入数据上同时执行的多个单元布局优化处理。重组优化过程的结果以产生优化的细胞放置。分析优化的单元布局的适应性，并且如果适合度不满足预定标准，则并行处理器被控制以选择性地重复执行优化处理以进一步优化优化的单元布局。该系统可以应用于初始放置，布线，布局改进等问题。处理器可以对不同的展示位置或单个展示位置执行相同的优化过程。或者，处理器可以在单个初始放置上同时执行不同的优化过程，所得到的经处理的放置具有最佳适合度作为优化的位置。处理器可以进一步选择性地重新处理具有高单元互连拥塞或其他低适应度参数的位置的区域。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式