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1. 发明授权

EP0028551B1 Comparateur à mémoire, assurant la régénération de signaux électriques numériques, et système de transmission numérique utilisant un tel comparateur 失效
标题翻译：用于再生数字电子信号的记忆比较器和使用这种比较器的数字传输系统
公开(公告)号：EP0028551B1
公开(公告)日：1983-10-05
申请号：EP80401427.2
申请日：1980-10-07
申请人： THOMSON-CSF
发明人： Peltier, Michel , Gloanec, Maurice , Nuzillat, Gérard , Maurel, Vincent , Charrier, Michel
IPC分类号： H04L25/66
CPC分类号： H04L25/247

2. 发明公开

EP0028551A1 Comparateur à mémoire, assurant la régénération de signaux électriques numériques, et système de transmission numérique utilisant un tel comparateur 失效
标题翻译：存储用于使用这样的比较器的电信号和数字传输系统的再生数字比较器。
公开(公告)号：EP0028551A1
公开(公告)日：1981-05-13
申请号：EP80401427.2
申请日：1980-10-07
申请人： THOMSON-CSF
发明人： Peltier, Michel , Gloanec, Maurice , Nuzillat, Gérard , Maurel, Vincent , Charrier, Michel
IPC分类号： H04L25/66
CPC分类号： H04L25/247
摘要： L'invention concerne un dispositif régénérateur des signaux numériques transmis le long d'une ligne coaxiale.
Afin de transmettre les informations à des débits supérieurs ou égaux à 650 Mbauds, le comparateur à mémoire selon l'invention est réalisé sous forme de circuit intégré sur AsGa et en transistors MESFET à tensions de seuil négatives. Il comporte un étage comparateur de tensions à seuil ajustable, une bascule type D de mémorisation et resynchrqon- isation par rapport à une horloge externe, et un étage adap- tateurde sortie, lequel peut assurer la sommation en sortie.
Application aux systèmes dans lequel l'information est numérisée: transmissions, instrumentation.

3. 发明授权

US09608755B2 Network element clock synchronization systems and methods using optical transport network delay measurement 有权
公开(公告)号：US09608755B2
公开(公告)日：2017-03-28
申请号：US13032790
申请日：2011-02-23
申请人： Jeffrey Scott Moynihan
发明人： Jeffrey Scott Moynihan
IPC分类号： H04J3/16 , H04J3/06 , H04L27/26 , H04L25/24 , H04L9/12 , H04L7/00
CPC分类号： H04J3/1658 , H04J3/0682 , H04L7/0054 , H04L9/12 , H04L25/247 , H04L27/2653
摘要： The present disclosure provides Network Element (NE) clock synchronization using Optical Transport Network (OTN) delay measurement systems and methods such as described in ITU-T G.709 (December 2009) “Interfaces for the Optical Transport Network (OTN)” and G.798 (October 2010) “Characteristics of optical transport network hierarchy equipment functional blocks”. OTN provides a Delay Measurement (DM) function to measure fiber path latency between two network elements to within microsecond accuracy. The convergence of packet switching and OTN transport into the same network element allows the sharing of this information between the two applications. The OTN delay measurement value can be used to synchronize two network element clocks to within microsecond accuracy without the need for a costly GPS synchronization solution or reduced accuracy NTP solutions.

4. 发明授权

US07813330B2 Gap filler apparatus and method for providing cyclic delay diversity in a digital multimedia broadcasting system, and broadcasting relay network using the same 有权
标题翻译：用于在数字多媒体广播系统中提供循环延迟分集的间隙填充装置和方法，以及使用其的广播中继网络
公开(公告)号：US07813330B2
公开(公告)日：2010-10-12
申请号：US11293638
申请日：2005-12-02
申请人： Hyun-Seok Yu , Hyun-Seok Oh , Ji-Won Ha , Min-Goo Kim
发明人： Hyun-Seok Yu , Hyun-Seok Oh , Ji-Won Ha , Min-Goo Kim
IPC分类号： H04B7/216
CPC分类号： H04L27/2662 , H04B7/022 , H04B7/0671 , H04L25/247 , H04L27/2607
摘要： A gap filler apparatus providing cyclic delay diversity in a digital multimedia broadcasting (DMB) system. In the gap filler apparatus, a receiver receives an orthogonal frequency division multiplexing (OFDM) signal transmitted as a broadcasting signal. A symbol synchronization unit acquires symbol synchronization of the OFDM signal, detects a guard interval of an OFDM symbol using the symbol synchronization, determines a sample length, by which the OFDM symbol is cyclic-delayed within the guard interval, and cyclic-delays the OFDM signal by the determined sample length. An amplifier amplifies the cyclic-delayed OFDM signal. A transmitter transmits the amplified OFDM signal to a wireless network.
摘要翻译：一种在数字多媒体广播（DMB）系统中提供循环延迟分集的间隙填充装置。在间隙填充装置中，接收机接收作为广播信号发送的正交频分复用（OFDM）信号。符号同步单元获取OFDM信号的符号同步，使用符号同步检测OFDM符号的保护间隔，确定OFDM符号在保护间隔内被循环延迟的采样长度，并循环延迟OFDM 通过确定的样本长度信号。放大器放大循环延迟的OFDM信号。发射机将放大的OFDM信号发射到无线网络。

5. 发明授权

US5052022A Repeater and PLL circuit 失效
标题翻译：中继器和PLL电路
公开(公告)号：US5052022A
公开(公告)日：1991-09-24
申请号：US378281
申请日：1989-07-11
申请人： Shigeo Nishita , Ryozo Yoshino , Masato Hirai
发明人： Shigeo Nishita , Ryozo Yoshino , Masato Hirai
IPC分类号： H03L7/08 , H04J3/06 , H04L7/033 , H04L12/42 , H04L25/24 , H04L25/52
CPC分类号： H04L12/422 , H04L25/247 , H04J3/0685 , H04L7/033
摘要： A PLL circuit for generating an AC output signal synchronized with an AC input signal applied thereto with a phase offset with respect to the input signal includes, in one embodiment, a charge pump circuit capable of varying the phase offset depending on the frequency of the AC input signal. In a signal transmission network system including a plurality of nodes coupled to a signal transmission line and distanced from one another by various repeat lengths of transmission path, each node has a repeater including such PLL circuit to suppress jitter caused by individual repeat length of transmission over the transmission line and still remaining in an equalized AC signal in each node.
摘要翻译：用于产生与施加到其上的相对于输入信号相位偏移的AC输入信号同步的AC输出信号的PLL电路在一个实施例中包括能够根据AC的频率改变相位偏移的电荷泵电路输入信号。在包括耦合到信号传输线并且通过传输路径的各种重复长度的彼此远离的多个节点的信号传输网络系统中，每个节点具有包括这样的PLL电路的中继器，以抑制由各个重复传输长度引起的抖动传输线并且仍然保持在每个节点中的均衡的AC信号中。

6. 发明授权

US2759047A Pulse transmission system and regenerative repeater therefor 失效
标题翻译：脉冲传输系统和再生中继器
公开(公告)号：US2759047A
公开(公告)日：1956-08-14
申请号：US20286650
申请日：1950-12-27
申请人： BELL TELEPHONE LABOR INC
发明人： MEACHAM LARNED A
IPC分类号： H04L25/24 , H04L25/49
CPC分类号： H04L25/247 , H04L25/4925

7. 发明公开

US20240097872A1 QUADRATURE CIRCUIT INTERCONNECT ARCHITECTURE WITH CLOCK FORWARDING 审中-公开
公开(公告)号：US20240097872A1
公开(公告)日：2024-03-21
申请号：US17933557
申请日：2022-09-20
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Michael Sperling , Daniel Mark Dreps , Erik English , Jieming Qi
IPC分类号： H04L7/00 , H04L25/24
CPC分类号： H04L7/0012 , H04L25/247
摘要： An integrated circuit communication architecture is provided and includes a clock lane, a clock divider, and a first de-skew circuit. The clock lane is configured to send a clock signal at a first rate from a first chip to a second chip. The clock divider is on the second chip and is configured to receive the clock signal sent via the clock lane and to create and send a first divided clock signal and a second divided clock signal from the received clock signal. The divided clock signals are sent at reduced rates compared to the first rate. The clock divider maintains current mode logic properties for the divided clock signals. The first de-skew circuit is configured to receive and process the divided clock signals to allow for sampling of data transmitted from the first chip to the second chip.

8. 发明申请

US20120213508A1 NETWORK ELEMENT CLOCK SYNCHRONIZATION SYSTEMS AND METHODS USING OPTICAL TRANSPORT NETWORK DELAY MEASUREMENT 有权
标题翻译：网络元件时钟同步系统和使用光传输网络延迟测量的方法
公开(公告)号：US20120213508A1
公开(公告)日：2012-08-23
申请号：US13032790
申请日：2011-02-23
申请人： Jeffrey Scott MOYNIHAN
发明人： Jeffrey Scott MOYNIHAN
IPC分类号： H04B10/00 , H04B10/08
CPC分类号： H04J3/1658 , H04J3/0682 , H04L7/0054 , H04L9/12 , H04L25/247 , H04L27/2653
摘要： The present disclosure provides Network Element (NE) clock synchronization using Optical Transport Network (OTN) delay measurement systems and methods such as described in ITU-T G.709 (12/2009) “Interfaces for the Optical Transport Network (OTN)” and G.798 (10/2010) “Characteristics of optical transport network hierarchy equipment functional blocks”. OTN provides a Delay Measurement (DM) function to measure fiber path latency between two network elements to within microsecond accuracy. The convergence of packet switching and OTN transport into the same network element allows the sharing of this information between the two applications. The OTN delay measurement value can be used to synchronize two network element clocks to within microsecond accuracy without the need for a costly GPS synchronization solution or reduced accuracy NTP solutions.
摘要翻译：本公开提供了使用光传输网络（OTN）延迟测量系统的网元（NE）时钟同步和诸如在ITU-T G.709（12/2009）“Optical Transport Network（OTN）的接口”中描述的方法，以及 G.798（10/2010）“光传输网络层次设备功能块特性”。 OTN提供延迟测量（DM）功能，以测量两个网络元件之间的光纤延迟至微秒精度。分组交换和OTN传输到同一网络元素的收敛允许在两个应用之间共享该信息。 OTN延迟测量值可用于将两个网元时钟同步至微秒精度，而不需要昂贵的GPS同步解决方案或降低精度的NTP解决方案。

9. 发明申请

US20070086512A1 Hybrid forwarding apparatus and method for cooperative relaying in an OFDM network 有权
标题翻译：用于在OFDM网络中协同中继的混合转发装置和方法
公开(公告)号：US20070086512A1
公开(公告)日：2007-04-19
申请号：US11526125
申请日：2006-09-22
申请人： Basak Can , Hiroyuki Yomo , Elisabeth de Carvalho , Kathiravetpillai Sivanesan , Do-Young Kim , Marcos Katz , Dong-Seek Park , Sung-Kwon Hong
发明人： Basak Can , Hiroyuki Yomo , Elisabeth de Carvalho , Kathiravetpillai Sivanesan , Do-Young Kim , Marcos Katz , Dong-Seek Park , Sung-Kwon Hong
IPC分类号： H04J11/00
CPC分类号： H04L27/2608 , H04B7/026 , H04B7/15557 , H04L1/20 , H04L25/247
摘要： A hybrid forwarding apparatus and method for cooperative relaying in an OFDM network are provided. In a hybrid forwarding apparatus in a relay terminal, a forwarding scheme selector selects a forwarding scheme for transmission. An amplify and forward (AF) block amplifies data received from the forwarding scheme selector, if an AF scheme is selected. A decode and forward (DF) block decodes and encodes data received from the forwarding scheme selector, if a DF scheme is selected. A multiplexer provides the output data of the AF block and the DF block to an OFDM modulator.
摘要翻译：提供了一种用于OFDM网络中的协同中继的混合转发装置和方法。在中继终端的混合转发装置中，转发方案选择器选择用于传输的转发方案。如果选择了AF方案，则放大和转发（AF）块放大从转发方案选择器接收的数据。如果选择DF方案，解码和转发（DF）块对从转发方案选择器接收的数据进行解码和编码。复用器将AF块和DF块的输出数据提供给OFDM调制器。

10. 发明授权

US08116420B2 Clock-forwarding technique for high-speed links 有权
标题翻译：用于高速链路的时钟转发技术
公开(公告)号：US08116420B2
公开(公告)日：2012-02-14
申请号：US12642348
申请日：2009-12-18
申请人： Tamer M. Ali , Robert J. Drost , Chih-Kong Ken Yang
发明人： Tamer M. Ali , Robert J. Drost , Chih-Kong Ken Yang
IPC分类号： H03D3/24
CPC分类号： H04L25/247 , H03L7/0805 , H04L7/0012
摘要： A repeater circuit, such as a clock regeneration and multiplication circuit, is described. In this repeater circuit, a clock multiplier unit (CMU) generates an internal clock signal based on a forwarded clock signal, which is received on a link. Furthermore, a phase interpolator (PI) in the repeater circuit provides the output clock signal based on the forwarded clock signal and the internal clock signal. Note that the CMU and the PI filter reduce the cycle-to-cycle jitter in the forwarded clock signal and the internal clock signal, and that the output clock signal has a phase that is a weighted average of the phases of the forwarded clock signal and the internal clock signal. In addition, the relative weights of the forwarded clock signal and the internal clock signal (i.e., the amount of phase averaging and jitter filtering) may be adjusted based on a position or location on the link.
摘要翻译：描述了诸如时钟再生和乘法电路的中继器电路。在该中继器电路中，时钟倍增器单元（CMU）基于在链路上接收到的转发时钟信号产生内部时钟信号。此外，中继器电路中的相位插值器（PI）基于转发的时钟信号和内部时钟信号来提供输出时钟信号。注意，CMU和PI滤波器减少转发的时钟信号和内部时钟信号中的周期到周期抖动，并且输出时钟信号具有作为转发的时钟信号的相位的加权平均的相位，以及内部时钟信号。此外，可以基于链路上的位置或位置来调整所转发的时钟信号和内部时钟信号的相对权重（即，相位平均和抖动滤波的量）。

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