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1. 发明授权

US08860597B2 Digital to-analog converter circuitry with weighted resistance elements 有权
标题翻译：具有加权电阻元件的数模转换器电路
公开(公告)号：US08860597B2
公开(公告)日：2014-10-14
申请号：US13541405
申请日：2012-07-03
申请人： Matthew D. Sienko
发明人： Matthew D. Sienko
IPC分类号： H03M1/80 , H03M1/08
CPC分类号： H03M1/808 , H03M1/0863 , H03M1/68 , H03M1/74
摘要： Digital-to-analog converter circuitry is described. The digital-to-analog converter circuitry includes a plurality of weighted resistance elements. A first weighted resistance element includes a switch coupled to a reference voltage. The first weighted resistance element also includes a T-network coupled to the switch. The T-network approximately equalizes a first response speed of the first weighted resistance element with a response speed of a differently weighted resistance element.
摘要翻译：描述了数模转换器电路。数模转换器电路包括多个加权电阻元件。第一加权电阻元件包括耦合到参考电压的开关。第一加权电阻元件还包括耦合到开关的T网络。 T网络以不同加权的电阻元件的响应速度大致均衡第一加权电阻元件的第一响应速度。

2. 发明申请

US20130293298A1 Split Capacitors Scheme for Suppressing Overshoot Voltage Glitches in Class D Amplifier Output Stage 有权
标题翻译：用于抑制D类放大器输出级过冲电压毛刺的分流电容器方案
公开(公告)号：US20130293298A1
公开(公告)日：2013-11-07
申请号：US13628011
申请日：2012-09-26
申请人： Chenling Huang , Haibo Fei , Matthew D. Sienko
发明人： Chenling Huang , Haibo Fei , Matthew D. Sienko
IPC分类号： H03F3/217
CPC分类号： H03F3/217 , H03F1/52
摘要： A class D power amplifier is provided. The class D power amplifier includes a class D driver circuit having a plurality of output transistors, at least one active clamp circuit coupled to at least one output transistor of the plurality of output transistors, and at least one filter bank circuit coupled to the at least one active clamp circuit for controlling a voltage of the at least one output transistor. Accordingly, a voltage across a drain node and source node (VDS), a voltage across a gate node and source node (VGS), and a voltage across the gate node and drain node (VGD) of the output transistors is reduced to increase reliability of the power amplifier while consuming less power and utilizing less die area.
摘要翻译：提供D类功率放大器。 D类功率放大器包括具有多个输出晶体管的D类驱动器电路，耦合到多个输出晶体管中的至少一个输出晶体管的至少一个有源钳位电路以及耦合至少一个至少一个的至少一个滤波器组电路一个有源钳位电路，用于控制至少一个输出晶体管的电压。因此，降低了漏极节点和源极节点（VDS）两端的电压，栅极节点和源节点（VGS）两端的电压以及输出晶体管的栅极节点和漏极节点（VGD）两端的电压，以增加可靠性的功率放大器，同时消耗更少的功率并且利用更少的管芯面积。

3. 发明授权

US07884672B1 Operational amplifier and method for amplifying a signal with shared compensation components 有权
标题翻译：运算放大器和用共享补偿元件放大信号的方法
公开(公告)号：US07884672B1
公开(公告)日：2011-02-08
申请号：US11592075
申请日：2006-11-01
申请人： Joseph A. Cetin , Matthew D. Sienko
发明人： Joseph A. Cetin , Matthew D. Sienko
IPC分类号： H03F3/45
CPC分类号： H03F3/45183 , H03F3/45659 , H03F2203/45008 , H03F2203/45082 , H03F2203/45418 , H03F2203/45424
摘要： An operational amplifier and a method for amplifying a signal. Embodiments provide a convenient and effective mechanism for reducing die area, design time and design verification time by sharing compensation components between the common-mode and differential feedback networks of the operational amplifier. As such, fewer compensation components are required, thereby reducing component die area. Additionally, given that the compensation components are shared between the common-mode and differential feedback networks, the feedback networks can be stabilized together with fewer compensation components to specify and verify, thereby reducing design and design verification time. Further, embodiments provide a compensation component coupling which does not couple directly to virtual ground, thereby reducing the noise of the operational amplifier.
摘要翻译：运算放大器和放大信号的方法。实施例提供了一种用于通过在运算放大器的共模和差分反馈网络之间共享补偿分量来减少管芯面积，设计时间和设计验证时间的便利和有效的机构。因此，需要更少的补偿部件，从而减少部件模具面积。另外，假设补偿分量在共模和差分反馈网络之间共享，反馈网络可以通过更少的补偿组件来稳定，以指定和验证，从而减少设计和设计验证时间。此外，实施例提供不直接耦合到虚拟接地的补偿分量耦合，从而降低运算放大器的噪声。

4. 发明授权

US07595674B1 Universal serial bus (USB) driver circuit, system, and method 有权
标题翻译：通用串行总线（USB）驱动电路，系统和方法
公开(公告)号：US07595674B1
公开(公告)日：2009-09-29
申请号：US11380127
申请日：2006-04-25
申请人： Joseph A. Cetin , Jason F. Muriby , Matthew D. Sienko
发明人： Joseph A. Cetin , Jason F. Muriby , Matthew D. Sienko
IPC分类号： H03K5/12
CPC分类号： G06F13/4072 , H04L25/0272
摘要： A driver circuit, system, and method is provided. The driver circuit includes a plurality of delay cells or circuits, each comprising a set of flip-flop circuits coupled in series to produce a staged set of outputs onto an output port of the driver circuit. The staged outputs are sequentially applied to the output port at a time depending on the number of flip-flop circuits within each stage. The number of such circuits can be programmably modified so that the slew rate output of the driver circuit can be programmably changed. The driver circuit can be a low speed driver circuit clocked by a low speed clocking signal of, for example, 1.5 MHz, with the slew rate derived by a clocking signal of, for example, 480 MHz. The higher speed clocking signal clocks the flip-flop circuits, yet the output is staged so that the low speed driver circuit transitions between logic states using the higher speed clock, but at a must slower edge rate. Therefore, the driver circuit, system, and method avoids passive electrical components and the PVT fluctuations associated therewith.
摘要翻译：提供了一种驱动电路，系统和方法。驱动器电路包括多个延迟单元或电路，每个延迟单元或电路各自包括一组串联耦合的触发器电路，以在驱动器电路的输出端口上产生分段输出。分段输出根据每个级内的触发器电路的数量一次顺序地施加到输出端口。可以可编程地修改这些电路的数量，使得可编程地改变驱动器电路的转换速率输出。驱动器电路可以是由诸如1.5MHz的低速时钟信号而定时的低速驱动器电路，其中由例如480MHz的时钟信号导出的转换速率。较高速度的时钟信号对触发器电路进行时钟，但是输出被分级，使得低速驱动器电路在使用较高速度时钟的逻辑状态之间转换，但是必须较慢的边沿速率。因此，驱动电路，系统和方法避免了无源电气部件和与之相关的PVT波动。

5. 发明申请

US20130223649A1 LOAD CURRENT SENSING 有权
标题翻译：负载电流检测
公开(公告)号：US20130223649A1
公开(公告)日：2013-08-29
申请号：US13406775
申请日：2012-02-28
申请人： Ankit Srivastava , Matthew D. Sienko , Meysam Azin , Xiaohong Quan , Peter J. Shah
发明人： Ankit Srivastava , Matthew D. Sienko , Meysam Azin , Xiaohong Quan , Peter J. Shah
IPC分类号： H03G3/00 , H03K3/00
CPC分类号： H03F3/2173 , H03F1/523 , H03F3/45179 , H03F3/45183 , H03F3/45475 , H03F2200/426 , H03F2200/462 , H03F2200/471 , H03F2200/481 , H03F2203/45522 , H03F2203/45526
摘要： Techniques for sensing current delivered to a load by a differential output stage, e.g., in a Class D amplifier. In one aspect, voltages across sense resistors coupled in series with first and second branches of the differential output stage are low-passed filtered and digitized. The sense resistors may be coupled in series with the sources of transistors of the first and second branches, wherein the transistors are selectively switchable on and off by input voltage driving voltages. The input driving voltages may correspond to a ternary voltage waveform such that during a given phase, the two transistors coupled in series with the sense resistors may be turned off. Further aspects provide for the first and second branches having cascoded NMOS and/or PMOS transistors, and the sense resistors being provided between a pair of cascoded transistors.
摘要翻译：用于感测由差分输出级（例如D类放大器）传送到负载的电流的技术。在一个方面，与差分输出级的第一和第二分支串联耦合的检测电阻之间的电压被低通滤波和数字化。感测电阻器可以与第一和第二分支的晶体管源串联耦合，其中晶体管可以通过输入电压驱动电压有选择地开关。输入驱动电压可以对应于三元电压波形，使得在给定相位期间，可以关断与感测电阻器串联耦合的两个晶体管。另外的方面提供具有级联的NMOS和/或PMOS晶体管的第一和第二分支，并且感测电阻器被提供在一对级联晶体管之间。

6. 发明授权

US08098718B2 Apparatus and methods for digital-to-analog conversion with vector quantization 有权
标题翻译：用矢量量化进行数模转换的装置和方法
公开(公告)号：US08098718B2
公开(公告)日：2012-01-17
申请号：US12640864
申请日：2009-12-17
申请人： Matthew D. Sienko , Joseph G. Hamilton , Iain W. Finlay
发明人： Matthew D. Sienko , Joseph G. Hamilton , Iain W. Finlay
IPC分类号： H04L25/00 , H04L27/00
CPC分类号： H03M1/0668 , H03M1/74 , H03M3/502
摘要： A digital-to-analog converter (DAC) includes a mismatch shaping feedback vector quantizer configured to store state information in expanded format using One-Hot Encoding of a matrix. The expanded state format storage enables implementation of a simplified state sorter for the vector feedback mechanism of the vector quantizer. The simplified state sorter may minimize the variance of ones (or other symbols representing state values) in the matrix, and allow performing sorting in a reduced number of clock cycles. For example, sorting may be performed on a predetermined edge of single clock cycle, or on two edges of the same clock cycle. The matrix may be normalized periodically or as needed, to avoid overflow and underflow. The DAC may be used as a quantizer of a modulator of an access terminal in a cellular communication system.
摘要翻译：数模转换器（DAC）包括不匹配整形反馈矢量量化器，其被配置为使用矩阵的单热编码来以扩展格式存储状态信息。扩展状态格式存储使得能够实现向量量化器的向量反馈机制的简化状态分类器。简化状态分类器可以使矩阵中的一个（或表示状态值的其他符号）的方差最小化，并允许以减少的时钟周期进行排序。例如，可以在单个时钟周期的预定边缘上或在相同时钟周期的两个边缘上执行排序。矩阵可以周期性地或根据需要进行归一化，以避免上溢和下溢。 DAC可以用作蜂窝通信系统中的接入终端的调制器的量化器。

7. 发明授权

US09088251B2 Overcurrent protection for class D power amplifier 有权
标题翻译： D类功率放大器的过电流保护
公开(公告)号：US09088251B2
公开(公告)日：2015-07-21
申请号：US13646585
申请日：2012-10-05
申请人： Haibo Fei , Matthew D. Sienko , Chenling Huang
发明人： Haibo Fei , Matthew D. Sienko , Chenling Huang
IPC分类号： H03F3/45 , H03F1/52 , H03F3/217
CPC分类号： H03F3/45 , H03F1/523 , H03F3/217 , H03F3/2171 , H03F3/2173 , H03F2200/456 , H03F2200/462 , H03F2200/474
摘要： In an aspect of the disclosure, a class D power amplifier with an overcurrent protection (OCP) circuit is provided. The class D power amplifier includes a plurality of output transistors, and the OCP circuit is mirrored to at least one output transistor of the plurality of output transistors in a closed-loop feedback configuration for precisely controlling a sensing current of the OCP circuit with respect to an output current of the at least one output transistor. The class D power amplifier with the OCP circuit in the closed-loop feedback configuration mitigates a variation in a current threshold value for triggering interruption of the class D power amplifier.
摘要翻译：在本公开的一个方面，提供了具有过电流保护（OCP）电路的D类功率放大器。 D类功率放大器包括多个输出晶体管，并且OCP电路以闭环反馈配置被镜像到多个输出晶体管中的至少一个输出晶体管，用于精确地控制OCP电路的感测电流相对于所述至少一个输出晶体管的输出电流。具有闭环反馈配置中的OCP电路的D类功率放大器减轻了用于触发D类功率放大器中断的电流阈值的变化。

8. 发明授权

US08947163B2 Split capacitors scheme for suppressing overshoot voltage glitches in class D amplifier output stage 有权
标题翻译：用于抑制D类放大器输出级中的过冲电压毛刺的分离电容器方案
公开(公告)号：US08947163B2
公开(公告)日：2015-02-03
申请号：US13628011
申请日：2012-09-26
申请人： Chenling Huang , Haibo Fei , Matthew D. Sienko
发明人： Chenling Huang , Haibo Fei , Matthew D. Sienko
IPC分类号： H03F3/217
CPC分类号： H03F3/217 , H03F1/52
摘要： A class D power amplifier is provided. The class D power amplifier includes a class D driver circuit having a plurality of output transistors, at least one active clamp circuit coupled to at least one output transistor of the plurality of output transistors, and at least one filter bank circuit coupled to the at least one active clamp circuit for controlling a voltage of the at least one output transistor. Accordingly, a voltage across a drain node and source node (VDS), a voltage across a gate node and source node (VGS), and a voltage across the gate node and drain node (VGD) of the output transistors is reduced to increase reliability of the power amplifier while consuming less power and utilizing less die area.
摘要翻译：提供D类功率放大器。 D类功率放大器包括具有多个输出晶体管的D类驱动器电路，耦合到多个输出晶体管中的至少一个输出晶体管的至少一个有源钳位电路以及耦合至少一个至少一个的至少一个滤波器组电路一个有源钳位电路，用于控制至少一个输出晶体管的电压。因此，降低了漏极节点和源极节点（VDS）两端的电压，栅极节点和源节点（VGS）两端的电压以及输出晶体管的栅极节点和漏极节点（VGD）两端的电压，以增加可靠性的功率放大器，同时消耗更少的功率并且利用更少的管芯面积。

9. 发明申请

US20110002264A1 APPARATUS AND METHODS FOR DIGITAL-TO-ANALOG CONVERSION WITH VECTOR QUANTIZATION 有权
标题翻译：用于具有矢量量化的数字到模拟转换的装置和方法
公开(公告)号：US20110002264A1
公开(公告)日：2011-01-06
申请号：US12640864
申请日：2009-12-17
申请人： Matthew D. Sienko , Joseph G. Hamilton , Iain W. Finlay
发明人： Matthew D. Sienko , Joseph G. Hamilton , Iain W. Finlay
IPC分类号： H04W4/00 , H04N7/26
CPC分类号： H03M1/0668 , H03M1/74 , H03M3/502
摘要： A digital-to-analog converter (DAC) includes a mismatch shaping feedback vector quantizer configured to store state information in expanded format using One-Hot Encoding of a matrix. The expanded state format storage enables implementation of a simplified state sorter for the vector feedback mechanism of the vector quantizer. The simplified state sorter may minimize the variance of ones (or other symbols representing state values) in the matrix, and allow performing sorting in a reduced number of clock cycles. For example, sorting may be performed on a predetermined edge of single clock cycle, or on two edges of the same clock cycle. The matrix may be normalized periodically or as needed, to avoid overflow and underflow. The DAC may be used as a quantizer of a modulator of an access terminal in a cellular communication system.
摘要翻译：数模转换器（DAC）包括不匹配整形反馈矢量量化器，其被配置为使用矩阵的单热编码来以扩展格式存储状态信息。扩展状态格式存储使得能够实现向量量化器的向量反馈机制的简化状态分类器。简化状态分类器可以使矩阵中的一个（或表示状态值的其他符号）的方差最小化，并允许以减少的时钟周期进行排序。例如，可以在单个时钟周期的预定边缘上或在相同时钟周期的两个边缘上执行排序。矩阵可以周期性地或根据需要进行归一化，以避免上溢和下溢。 DAC可以用作蜂窝通信系统中的接入终端的调制器的量化器。

10. 发明授权

US07560987B1 Amplifier circuit with bias stage for controlling a common mode output voltage of the gain stage during device power-up 有权
标题翻译：具有偏置级的放大器电路，用于在器件上电期间控制增益级的共模输出电压
公开(公告)号：US07560987B1
公开(公告)日：2009-07-14
申请号：US11420948
申请日：2006-05-30
申请人： Joseph A. Cetin , Matthew D. Sienko , Jason F. Muriby
发明人： Joseph A. Cetin , Matthew D. Sienko , Jason F. Muriby
IPC分类号： H03F3/45
CPC分类号： H03F3/45291 , H03F3/45807 , H03F2203/45008 , H03F2203/45418 , H03F2203/45424 , H03F2203/45626 , H03F2203/45648 , H03F2203/45681 , H03F2203/45722 , H03F2203/45726 , H03F2203/45728
摘要： An improved amplifier circuit is provided herein with a gain stage and a bias stage, which may be switchably connected to the gain stage during power-up operations. The bias stage reduces a power-up time associated with the gain stage, while minimizing current consumption in the next amplifier stage and improving battery life. For example, during power-up, the bias stage may enable the output voltage of the gain stage to gradually rise from a ground potential to a desired common mode level in a highly controlled and predictable manner. By preventing “glitches” in the output voltage, the bias stage eliminates the need for inserting switches in the signal path between the output nodes of the gain stage and input nodes of the next amplifier stage.
摘要翻译：本文提供了一种改进的放大器电路，其具有增益级和偏置级，其可在上电操作期间可切换地连接到增益级。偏置级减少与增益级相关的上电时间，同时最大限度地减少下一个放大器级的电流消耗并提高电池寿命。例如，在上电期间，偏置级可以使得增益级的输出电压以高度可控和可预测的方式从地电位逐渐上升到期望的共模电平。通过防止输出电压中的“毛刺”，偏置级不需要在增益级的输出节点和下一个放大器级的输入节点之间的信号路径中插入开关。

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