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    • 1. 发明申请
    • Split Capacitors Scheme for Suppressing Overshoot Voltage Glitches in Class D Amplifier Output Stage
    • 用于抑制D类放大器输出级过冲电压毛刺的分流电容器方案
    • US20130293298A1
    • 2013-11-07
    • US13628011
    • 2012-09-26
    • Chenling HuangHaibo FeiMatthew D. Sienko
    • Chenling HuangHaibo FeiMatthew D. Sienko
    • H03F3/217
    • H03F3/217H03F1/52
    • A class D power amplifier is provided. The class D power amplifier includes a class D driver circuit having a plurality of output transistors, at least one active clamp circuit coupled to at least one output transistor of the plurality of output transistors, and at least one filter bank circuit coupled to the at least one active clamp circuit for controlling a voltage of the at least one output transistor. Accordingly, a voltage across a drain node and source node (VDS), a voltage across a gate node and source node (VGS), and a voltage across the gate node and drain node (VGD) of the output transistors is reduced to increase reliability of the power amplifier while consuming less power and utilizing less die area.
    • 提供D类功率放大器。 D类功率放大器包括具有多个输出晶体管的D类驱动器电路,耦合到多个输出晶体管中的至少一个输出晶体管的至少一个有源钳位电路以及耦合至少一个至少一个的至少一个滤波器组电路 一个有源钳位电路,用于控制至少一个输出晶体管的电压。 因此,降低了漏极节点和源极节点(VDS)两端的电压,栅极节点和源节点(VGS)两端的电压以及输出晶体管的栅极节点和漏极节点(VGD)两端的电压,以增加可靠性 的功率放大器,同时消耗更少的功率并且利用更少的管芯面积。
    • 4. 发明授权
    • Split capacitors scheme for suppressing overshoot voltage glitches in class D amplifier output stage
    • 用于抑制D类放大器输出级中的过冲电压毛刺的分离电容器方案
    • US08947163B2
    • 2015-02-03
    • US13628011
    • 2012-09-26
    • Chenling HuangHaibo FeiMatthew D. Sienko
    • Chenling HuangHaibo FeiMatthew D. Sienko
    • H03F3/217
    • H03F3/217H03F1/52
    • A class D power amplifier is provided. The class D power amplifier includes a class D driver circuit having a plurality of output transistors, at least one active clamp circuit coupled to at least one output transistor of the plurality of output transistors, and at least one filter bank circuit coupled to the at least one active clamp circuit for controlling a voltage of the at least one output transistor. Accordingly, a voltage across a drain node and source node (VDS), a voltage across a gate node and source node (VGS), and a voltage across the gate node and drain node (VGD) of the output transistors is reduced to increase reliability of the power amplifier while consuming less power and utilizing less die area.
    • 提供D类功率放大器。 D类功率放大器包括具有多个输出晶体管的D类驱动器电路,耦合到多个输出晶体管中的至少一个输出晶体管的至少一个有源钳位电路以及耦合至少一个至少一个的至少一个滤波器组电路 一个有源钳位电路,用于控制至少一个输出晶体管的电压。 因此,降低了漏极节点和源极节点(VDS)两端的电压,栅极节点和源节点(VGS)两端的电压以及输出晶体管的栅极节点和漏极节点(VGD)两端的电压,以增加可靠性 的功率放大器,同时消耗更少的功率并且利用更少的管芯面积。