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1. 发明授权

US07595674B1 Universal serial bus (USB) driver circuit, system, and method 有权
标题翻译：通用串行总线（USB）驱动电路，系统和方法
公开(公告)号：US07595674B1
公开(公告)日：2009-09-29
申请号：US11380127
申请日：2006-04-25
申请人： Joseph A. Cetin , Jason F. Muriby , Matthew D. Sienko
发明人： Joseph A. Cetin , Jason F. Muriby , Matthew D. Sienko
IPC分类号： H03K5/12
CPC分类号： G06F13/4072 , H04L25/0272
摘要： A driver circuit, system, and method is provided. The driver circuit includes a plurality of delay cells or circuits, each comprising a set of flip-flop circuits coupled in series to produce a staged set of outputs onto an output port of the driver circuit. The staged outputs are sequentially applied to the output port at a time depending on the number of flip-flop circuits within each stage. The number of such circuits can be programmably modified so that the slew rate output of the driver circuit can be programmably changed. The driver circuit can be a low speed driver circuit clocked by a low speed clocking signal of, for example, 1.5 MHz, with the slew rate derived by a clocking signal of, for example, 480 MHz. The higher speed clocking signal clocks the flip-flop circuits, yet the output is staged so that the low speed driver circuit transitions between logic states using the higher speed clock, but at a must slower edge rate. Therefore, the driver circuit, system, and method avoids passive electrical components and the PVT fluctuations associated therewith.
摘要翻译：提供了一种驱动电路，系统和方法。驱动器电路包括多个延迟单元或电路，每个延迟单元或电路各自包括一组串联耦合的触发器电路，以在驱动器电路的输出端口上产生分段输出。分段输出根据每个级内的触发器电路的数量一次顺序地施加到输出端口。可以可编程地修改这些电路的数量，使得可编程地改变驱动器电路的转换速率输出。驱动器电路可以是由诸如1.5MHz的低速时钟信号而定时的低速驱动器电路，其中由例如480MHz的时钟信号导出的转换速率。较高速度的时钟信号对触发器电路进行时钟，但是输出被分级，使得低速驱动器电路在使用较高速度时钟的逻辑状态之间转换，但是必须较慢的边沿速率。因此，驱动电路，系统和方法避免了无源电气部件和与之相关的PVT波动。

2. 发明授权

US07560987B1 Amplifier circuit with bias stage for controlling a common mode output voltage of the gain stage during device power-up 有权
标题翻译：具有偏置级的放大器电路，用于在器件上电期间控制增益级的共模输出电压
公开(公告)号：US07560987B1
公开(公告)日：2009-07-14
申请号：US11420948
申请日：2006-05-30
申请人： Joseph A. Cetin , Matthew D. Sienko , Jason F. Muriby
发明人： Joseph A. Cetin , Matthew D. Sienko , Jason F. Muriby
IPC分类号： H03F3/45
CPC分类号： H03F3/45291 , H03F3/45807 , H03F2203/45008 , H03F2203/45418 , H03F2203/45424 , H03F2203/45626 , H03F2203/45648 , H03F2203/45681 , H03F2203/45722 , H03F2203/45726 , H03F2203/45728
摘要： An improved amplifier circuit is provided herein with a gain stage and a bias stage, which may be switchably connected to the gain stage during power-up operations. The bias stage reduces a power-up time associated with the gain stage, while minimizing current consumption in the next amplifier stage and improving battery life. For example, during power-up, the bias stage may enable the output voltage of the gain stage to gradually rise from a ground potential to a desired common mode level in a highly controlled and predictable manner. By preventing “glitches” in the output voltage, the bias stage eliminates the need for inserting switches in the signal path between the output nodes of the gain stage and input nodes of the next amplifier stage.
摘要翻译：本文提供了一种改进的放大器电路，其具有增益级和偏置级，其可在上电操作期间可切换地连接到增益级。偏置级减少与增益级相关的上电时间，同时最大限度地减少下一个放大器级的电流消耗并提高电池寿命。例如，在上电期间，偏置级可以使得增益级的输出电压以高度可控和可预测的方式从地电位逐渐上升到期望的共模电平。通过防止输出电压中的“毛刺”，偏置级不需要在增益级的输出节点和下一个放大器级的输入节点之间的信号路径中插入开关。

3. 发明授权

US07884672B1 Operational amplifier and method for amplifying a signal with shared compensation components 有权
标题翻译：运算放大器和用共享补偿元件放大信号的方法
公开(公告)号：US07884672B1
公开(公告)日：2011-02-08
申请号：US11592075
申请日：2006-11-01
申请人： Joseph A. Cetin , Matthew D. Sienko
发明人： Joseph A. Cetin , Matthew D. Sienko
IPC分类号： H03F3/45
CPC分类号： H03F3/45183 , H03F3/45659 , H03F2203/45008 , H03F2203/45082 , H03F2203/45418 , H03F2203/45424
摘要： An operational amplifier and a method for amplifying a signal. Embodiments provide a convenient and effective mechanism for reducing die area, design time and design verification time by sharing compensation components between the common-mode and differential feedback networks of the operational amplifier. As such, fewer compensation components are required, thereby reducing component die area. Additionally, given that the compensation components are shared between the common-mode and differential feedback networks, the feedback networks can be stabilized together with fewer compensation components to specify and verify, thereby reducing design and design verification time. Further, embodiments provide a compensation component coupling which does not couple directly to virtual ground, thereby reducing the noise of the operational amplifier.
摘要翻译：运算放大器和放大信号的方法。实施例提供了一种用于通过在运算放大器的共模和差分反馈网络之间共享补偿分量来减少管芯面积，设计时间和设计验证时间的便利和有效的机构。因此，需要更少的补偿部件，从而减少部件模具面积。另外，假设补偿分量在共模和差分反馈网络之间共享，反馈网络可以通过更少的补偿组件来稳定，以指定和验证，从而减少设计和设计验证时间。此外，实施例提供不直接耦合到虚拟接地的补偿分量耦合，从而降低运算放大器的噪声。

4. 发明授权

US07826581B1 Linearized digital phase-locked loop method for maintaining end of packet time linearity 有权
标题翻译：线性数字锁相环方法，用于维持分组时间线性度的结束
公开(公告)号：US07826581B1
公开(公告)日：2010-11-02
申请号：US10959259
申请日：2004-10-05
申请人： Stephen M. Prather , Matthew S. Berzins , Charles A. Cornell , Steven P. Larky , Joseph A. Cetin
发明人： Stephen M. Prather , Matthew S. Berzins , Charles A. Cornell , Steven P. Larky , Joseph A. Cetin
IPC分类号： H03D3/24
CPC分类号： H04L7/0337 , H04L7/10
摘要： An apparatus and method are disclosed synchronization of a clock signal to a data signal. The apparatus includes a phase lock and tracking logic circuit configured to detect a plurality of values. Each of the plurality of values indicates a position of a data edge of the data signal. The phase lock and tracking logic circuit adds the plurality of values to generate a result and to adjust the clock signal if the result is greater than a predetermined value, or threshold. The phase lock and tracking logic circuit may be configured to maintain the clock signal linearity approximately between the end of a first data packet and the beginning of a second data packet.
摘要翻译：公开了一种将时钟信号与数据信号同步的装置和方法。该装置包括配置成检测多个值的锁相和跟踪逻辑电路。多个值中的每一个表示数据信号的数据边缘的位置。相位锁定和跟踪逻辑电路将多个值相加以产生结果并且如果结果大于预定值或阈值则调整时钟信号。相位锁定和跟踪逻辑电路可以被配置为将时钟信号的线性度大致维持在第一数据分组的结尾和第二数据分组的开始之间。

5. 发明申请

US20090172425A1 Digitally controlled dynamic power management unit for uninterruptible power supply 审中-公开
标题翻译：数字控制动态电源管理单元，用于不间断电源
公开(公告)号：US20090172425A1
公开(公告)日：2009-07-02
申请号：US12006229
申请日：2007-12-31
申请人： Joseph A. Cetin , Patrick J. Sullivan
发明人： Joseph A. Cetin , Patrick J. Sullivan
IPC分类号： G06F1/26
CPC分类号： G06F1/30
摘要： A memory system power management process includes providing a first level of power to operate a memory system while a primary power source is enabled, detecting an interruption of the primary power source, increasing a frequency of an oscillator driving a charge pump of a power converter providing the first level of power, and beginning a memory operation that increases a load on the power converter.
摘要翻译：存储器系统电源管理过程包括在主电源被使能的同时提供第一级电源来操作存储器系统，检测主电源的中断，增加驱动电源转换器的电荷泵的振荡器的频率，第一级电源，并开始增加功率转换器负载的存储器操作。

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