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    • 4. 发明授权
    • Field effect transistor
    • 场效应晶体管
    • US08072002B2
    • 2011-12-06
    • US12382941
    • 2009-03-26
    • Yuki NiyamaSeikoh YoshidaHiroshi KambayashiTakehiko NomuraMasayuki IwamiShinya Ootomo
    • Yuki NiyamaSeikoh YoshidaHiroshi KambayashiTakehiko NomuraMasayuki IwamiShinya Ootomo
    • H01L29/66
    • H01L29/2003H01L29/0843H01L29/42368H01L29/7786
    • A field effect transistor formed of a semiconductor of a III group nitride compound, includes an electron running layer formed on a substrate and formed of GaN; an electron supplying layer formed on the electron running layer and formed of AlxGa1-xN (0.01≦x≦0.4), the electron supplying layer having a band gap energy different from that of the electron running layer and being separated with a recess region having a depth reaching the electron running layer; a source electrode and a drain electrode formed on the electron supplying layer with the recess region in between; a gate insulating film layer formed on the electron supplying layer for covering a surface of the electron running layer in the recess region; and a gate electrode formed on the gate insulating film layer in the recess region. The electron supplying layer has a layer thickness between 5.5 nm and 40 nm.
    • 由III族氮化物化合物的半导体形成的场效应晶体管包括形成在衬底上并由GaN形成的电子运行层; 电子供给层,形成在电子运行层上,由Al x Ga 1-x N(0.01≦̸ x≦̸ 0.4)形成,电子供给层的带隙能量与电子运行层的能隙不同,并且与具有 达到电子运行层的深度; 形成在电子供给层上的源电极和漏电极,其间具有凹陷区域; 在所述电子供给层上形成的用于覆盖所述凹部的电子运行层的表面的栅极绝缘膜层; 以及形成在所述凹部区域中的所述栅极绝缘膜层上的栅电极。 电子供给层的层厚在5.5nm至40nm之间。
    • 5. 发明申请
    • SEMICONDUCTOR ELECTRONIC DEVICE
    • US20090200645A1
    • 2009-08-13
    • US12364966
    • 2009-02-03
    • Takuya KokawaSadahiro KatoYoshihiro SatoMasayuki Iwami
    • Takuya KokawaSadahiro KatoYoshihiro SatoMasayuki Iwami
    • H01L49/02
    • H01L29/7787H01L29/045H01L29/155H01L29/2003
    • A semiconductor electronic device comprises a substrate; a buffer layer formed on the substrate, the buffer layer including not less than two layers of composite layer in which a first semiconductor layer formed of a nitride-based compound semiconductor layer having a lattice constant smaller than a lattice constant of the substrate and a thermal expansion coefficient larger than a thermal expansion coefficient of the substrate and a second semiconductor layer formed of a nitride-based compound semiconductor having a lattice constant smaller than a lattice constant of the first semiconductor layer and a thermal expansion coefficient larger than a thermal expansion coefficient of the substrate are alternately laminated; an intermediate layer provided between the substrate and the buffer layer, the intermediate layer being formed of a nitride-based compound semiconductor having a lattice constant smaller than a lattice constant of the first semiconductor layer and a thermal expansion coefficient larger than a thermal expansion coefficient of the substrate; and a semiconductor active layer formed on the buffer layer, the semiconductor active layer being formed of a nitride-based compound semiconductor, wherein: thicknesses of the first semiconductor layers in the buffer layer are non-uniform thereamong, and at least one of the first semiconductor layer has a thickness greater than a critical thickness, the critical thickness being a thickness above which a direction of warp caused by the first semiconductor layer to the substrate is inverted.
    • 半导体电子器件包括衬底; 形成在所述基板上的缓冲层,所述缓冲层包括不少于两层的复合层,其中由氮化物基化合物半导体层形成的第一半导体层的晶格常数小于所述基板的晶格常数, 膨胀系数大于衬底的热膨胀系数,以及由具有小于第一半导体层的晶格常数的晶格常数的氮化物系化合物半导体形成的第二半导体层和大于第一半导体层的热膨胀系数的热膨胀系数 基板交替层压; 设置在所述基板和所述缓冲层之间的中间层,所述中间层由格子常数小于所述第一半导体层的晶格常数的氮化物系化合物半导体形成,所述中间层的热膨胀系数大于所述第一半导体层的热膨胀系数 基材; 以及形成在所述缓冲层上的半导体有源层,所述半导体有源层由氮化物系化合物半导体形成,其中:所述缓冲层中的所述第一半导体层的厚度不均匀,所述第一半导体层的至少一个 半导体层的厚度大于临界厚度,临界厚度是由第一半导体层向衬底引起的翘曲方向反转的厚度。
    • 7. 发明申请
    • NITRIDE SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD FOR THE SAME
    • 氮化物半导体器件及其制造方法
    • US20130069076A1
    • 2013-03-21
    • US13617156
    • 2012-09-14
    • Masayuki IWAMITakuya KOKAWA
    • Masayuki IWAMITakuya KOKAWA
    • H01L29/205H01L21/335
    • H01L29/7787H01L29/155H01L29/2003
    • Provided is a nitride semiconductor device comprising a base substrate; a buffer layer formed above the base substrate; an active layer formed on the buffer layer; and at least two electrodes formed above the active layer. The buffer layer includes one or more composite layers that each have a plurality of nitride semiconductor layers with different lattice constants, and at least one of the one or more composite layers is doped with carbon atoms and oxygen atoms in at least a portion of a carrier region of the nitride semiconductor having the largest lattice constant among the plurality of nitride semiconductor layers, the carrier region being a region in which carriers are generated due to the difference in lattice constants between this nitride semiconductor layer and the nitride semiconductor layer formed directly thereon.
    • 提供了一种氮化物半导体器件,其包括基底基板; 形成在所述基底基板上的缓冲层; 形成在缓冲层上的有源层; 以及形成在有源层上方的至少两个电极。 缓冲层包括一个或多个复合层,每个复合层各自具有不同晶格常数的多个氮化物半导体层,并且该一个或多个复合层中的至少一个在载体的至少一部分中掺杂有碳原子和氧原子 在多个氮化物半导体层中具有最大晶格常数的氮化物半导体的区域,由于该氮化物半导体层和直接形成的氮化物半导体层之间的晶格常数的差异,载流子区域是其中产生载流子的区域。
    • 8. 发明授权
    • Semiconductor electronic device having reduced threading dislocation and method of manufacturing the same
    • 具有减少穿透位错的半导体电子器件及其制造方法
    • US08338859B2
    • 2012-12-25
    • US12569429
    • 2009-09-29
    • Takuya KokawaSadahiro KatoYoshihiro SatoMasayuki Iwami
    • Takuya KokawaSadahiro KatoYoshihiro SatoMasayuki Iwami
    • H01L21/02H01L21/338
    • H01L29/7783H01L29/2003H01L29/66462
    • A semiconductor electronic device comprises a substrate; a buffer layer formed on said substrate, having two or more layers of composite layers in which a first semiconductor layer comprising nitride based compound semiconductor having smaller lattice constant and greater coefficient of thermal expansion than the substrate and a second semiconductor layer comprising nitride based compound semiconductor having smaller lattice constant and smaller coefficient of thermal expansion than the first semiconductor layer are alternately laminated; a semiconductor operating layer comprising nitride based compound semiconductor formed on said buffer layer; a dislocation reducing layer comprising nitride based compound semiconductor, formed in a location between a location directly under said buffer layer and inner area of said semiconductor operating layer, and comprising a lower layer area and an upper layer area each having an uneven boundary surface, wherein threading dislocation extending from the lower layer area to the upper layer area is bent at said boundary surface.
    • 半导体电子器件包括衬底; 形成在所述基板上的缓冲层,具有两层或多层复合层,其中第一半导体层包含氮化物基化合物半导体,该氮化物基化合物半导体具有比基板更小的晶格常数和更大的热膨胀系数,第二半导体层包括氮化物基化合物半导体 具有比第一半导体层更小的晶格常数和较小的热膨胀系数交替层压; 半导体工作层,包括形成在所述缓冲层上的氮化物基化合物半导体; 形成在直接位于所述缓冲层下方的位置与所述半导体工作层的内部区域之间的位置处的氮化物基化合物半导体的位错降低层,并且包括具有不均匀边界面的下层区域和上层区域,其中, 从所述下层区延伸到所述上层区域的穿透位错在所述边界面弯曲。
    • 9. 发明授权
    • Semiconductor electronic device
    • 半导体电子器件
    • US08067787B2
    • 2011-11-29
    • US12364966
    • 2009-02-03
    • Takuya KokawaSadahiro KatoYoshihiro SatoMasayuki Iwami
    • Takuya KokawaSadahiro KatoYoshihiro SatoMasayuki Iwami
    • H01L21/02
    • H01L29/7787H01L29/045H01L29/155H01L29/2003
    • A semiconductor electronic device comprises a substrate; a buffer layer formed on the substrate, the buffer layer including not less than two layers of composite layer in which a first semiconductor layer formed of a nitride-based compound semiconductor layer having a lattice constant smaller than a lattice constant of the substrate and a thermal expansion coefficient larger than a thermal expansion coefficient of the substrate and a second semiconductor layer formed of a nitride-based compound semiconductor having a lattice constant smaller than a lattice constant of the first semiconductor layer and a thermal expansion coefficient larger than a thermal expansion coefficient of the substrate are alternately laminated; an intermediate layer provided between the substrate and the buffer layer, the intermediate layer being formed of a nitride-based compound semiconductor having a lattice constant smaller than a lattice constant of the first semiconductor layer and a thermal expansion coefficient larger than a thermal expansion coefficient of the substrate; and a semiconductor active layer formed on the buffer layer, the semiconductor active layer being formed of a nitride-based compound semiconductor, wherein: thicknesses of the first semiconductor layers in the buffer layer are non-uniform thereamong, and at least one of the first semiconductor layer has a thickness greater than a critical thickness, the critical thickness being a thickness above which a direction of warp caused by the first semiconductor layer to the substrate is inverted.
    • 半导体电子器件包括衬底; 形成在所述基板上的缓冲层,所述缓冲层包括不少于两层的复合层,其中由氮化物基化合物半导体层形成的第一半导体层的晶格常数小于所述基板的晶格常数, 膨胀系数大于衬底的热膨胀系数,以及由具有小于第一半导体层的晶格常数的晶格常数的氮化物系化合物半导体形成的第二半导体层和大于第一半导体层的热膨胀系数的热膨胀系数 基板交替层压; 设置在所述基板和所述缓冲层之间的中间层,所述中间层由格子常数小于所述第一半导体层的晶格常数的氮化物系化合物半导体形成,所述中间层的热膨胀系数大于所述第一半导体层的热膨胀系数 基材; 以及形成在所述缓冲层上的半导体有源层,所述半导体有源层由氮化物系化合物半导体形成,其中:所述缓冲层中的所述第一半导体层的厚度不均匀,所述第一半导体层的至少一个 半导体层的厚度大于临界厚度,临界厚度是由第一半导体层向衬底引起的翘曲方向反转的厚度。