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1. 发明授权

US08450782B2 Field effect transistor, method of manufacturing field effect transistor, and method of forming groove 有权
标题翻译：场效应晶体管，制造场效应晶体管的方法和形成沟槽的方法
公开(公告)号：US08450782B2
公开(公告)日：2013-05-28
申请号：US13075843
申请日：2011-03-30
申请人： Yoshihiro Sato , Takehiko Nomura , Nariaki Ikeda , Takuya Kokawa , Masayuki Iwami , Sadahiro Kato
发明人： Yoshihiro Sato , Takehiko Nomura , Nariaki Ikeda , Takuya Kokawa , Masayuki Iwami , Sadahiro Kato
IPC分类号： H01L29/76
CPC分类号： H01L29/0847 , H01L21/02381 , H01L21/02458 , H01L21/0254 , H01L21/02579 , H01L21/0262 , H01L29/2003 , H01L29/4232 , H01L29/518 , H01L29/66462 , H01L29/7787
摘要： A field effect transistor includes a high resistance layer on a substrate, a semiconductor operation layer that is formed on the high resistance layer and includes a channel layer that has the carbon concentration of not more than 1×1018 cm−3 and has the layer thickness of more than 10 nm and not more than 100 nm, a recess that is formed up to the inside of the channel layer in the semiconductor operation layer, source and drain electrodes that are formed on the semiconductor operation layer with the recess intervening therebetween, a gate insulating film that is formed on the semiconductor operation layer so as to cover the recess, and a gate electrode that is formed on the gate insulating film in the recess.
摘要翻译：场效应晶体管包括在基板上的高电阻层，形成在高电阻层上并具有碳浓度不大于1×10 18 cm -3且具有层厚度的沟道层的半导体操作层大于10nm且不大于100nm的凹槽，形成在半导体操作层中的沟道层内部的凹部，形成在半导体操作层上的沟槽间的沟槽间的沟槽间的沟槽，栅极绝缘膜，其形成在半导体操作层上以覆盖凹部;以及栅电极，其形成在凹部中的栅极绝缘膜上。

2. 发明申请

US20090278172A1 GaN based semiconductor element 有权
标题翻译： GaN基半导体元件
公开(公告)号：US20090278172A1
公开(公告)日：2009-11-12
申请号：US12382010
申请日：2009-03-05
申请人： Shusuke Kaya , Seikoh Yoshida , Sadahiro Kato , Takehiko Nomura , Nariaki Ikeda , Masayuki Iwami , Yoshihiro Sato , Hiroshi Kambayashi , Yuki Niiyama , Masatoshi Ikeda
发明人： Shusuke Kaya , Seikoh Yoshida , Sadahiro Kato , Takehiko Nomura , Nariaki Ikeda , Masayuki Iwami , Yoshihiro Sato , Hiroshi Kambayashi , Yuki Niiyama , Masatoshi Ikeda
IPC分类号： H01L29/205
CPC分类号： H01L29/0847 , H01L29/0657 , H01L29/2003 , H01L29/205 , H01L29/4236 , H01L29/42376 , H01L29/66462 , H01L29/7787
摘要： The field effect transistor includes a laminated structure in which a buffer layer, and an electron transporting layer (undoped GaN layer), and an electron supplying layer (undoped AlGaN layer) are laminated in sequence on a sapphire substrate. An npn laminated structure is formed on a source region of the electron supplying layer, and a source electrode is formed on the npn laminated structure. A drain electrode is formed in a drain region of the electron supplying layer, and an insulating film is formed in an opening region formed in the gate region. When a forward voltage greater than a threshold is applied to the gate electrode, an inversion layer is formed and the drain current flows. By changing a thickness and an impurity concentration of the p-type GaN layer, the threshold voltage can be controlled. The electrical field concentration between the gate electrode and the drain electrode is relaxed due to the drift layer, and voltage resistance improves.
摘要翻译：场效应晶体管包括其中缓冲层和电子传输层（未掺杂的GaN层）和电子供应层（未掺杂的AlGaN层）依次叠置在蓝宝石衬底上的叠层结构。在电子供给层的源极区域上形成npn层叠结构，在npn层叠结构上形成源电极。在电子供给层的漏极区域中形成漏电极，并且在形成在栅极区域的开口区域中形成绝缘膜。当向栅电极施加大于阈值的正向电压时，形成反型层，漏极电流流动。通过改变p型GaN层的厚度和杂质浓度，可以控制阈值电压。由于漂移层，栅极电极和漏电极之间的电场浓度被松弛，并且耐电压提高。

3. 发明申请

US20090140295A1 GaN-based semiconductor device and method of manufacturing the same 有权
标题翻译： GaN基半导体器件及其制造方法
公开(公告)号：US20090140295A1
公开(公告)日：2009-06-04
申请号：US12292164
申请日：2008-11-13
申请人： Shusuke Kaya , Seikoh Yoshida , Sadahiro Kato , Takehiko Nomura , Nariaki Ikeda , Masayuki Iwami , Yoshihiro Sato , Hiroshi Kambayashi , Koh Li
发明人： Shusuke Kaya , Seikoh Yoshida , Sadahiro Kato , Takehiko Nomura , Nariaki Ikeda , Masayuki Iwami , Yoshihiro Sato , Hiroshi Kambayashi , Koh Li
IPC分类号： H01L29/737 , H01L21/28 , H01L21/265
CPC分类号： H01L29/7787 , H01L29/0611 , H01L29/2003 , H01L29/4175 , H01L29/66462
摘要： A GaN-based semiconductor device includes a silicon substrate; an active layer of a GaN-based semiconductor formed on the silicon substrate; a trench formed in the active layer and extending from a top surface of the active layer to the silicon substrate; a first electrode formed on an internal wall surface of the trench so that the first electrode extends from the top surface of the active layer to the silicon substrate; a second electrode formed on the active layer so that a current flows between the first electrode and the second electrode via the active layer; and a bottom electrode formed on a bottom surface of the silicon substrate. The first electrode is formed of a metal capable of being in ohmic contact with the silicon substrate and the active layer.
摘要翻译： GaN基半导体器件包括硅衬底; 形成在硅衬底上的GaN基半导体的有源层; 形成在有源层中并从有源层的顶表面延伸到硅衬底的沟槽; 形成在所述沟槽的内壁表面上的第一电极，使得所述第一电极从所述有源层的顶表面延伸到所述硅衬底; 形成在有源层上的第二电极，使得电流经由有源层在第一电极和第二电极之间流动; 以及形成在硅衬底的底表面上的底部电极。第一电极由能够与硅衬底和有源层欧姆接触的金属形成。

4. 发明授权

US08304809B2 GaN-based semiconductor device and method of manufacturing the same 有权
标题翻译： GaN基半导体器件及其制造方法
公开(公告)号：US08304809B2
公开(公告)日：2012-11-06
申请号：US12292164
申请日：2008-11-13
申请人： Shusuke Kaya , Seikoh Yoshida , Masatoshi Ikeda, legal representative , Sadahiro Kato , Takehiko Nomura , Nariaki Ikeda , Masayuki Iwami , Yoshihiro Sato , Hiroshi Kambayashi , Koh Li
发明人： Shusuke Kaya , Seikoh Yoshida , Sadahiro Kato , Takehiko Nomura , Nariaki Ikeda , Masayuki Iwami , Yoshihiro Sato , Hiroshi Kambayashi , Koh Li
IPC分类号： H01L29/737 , H01L21/28 , H01L21/265
CPC分类号： H01L29/7787 , H01L29/0611 , H01L29/2003 , H01L29/4175 , H01L29/66462
摘要： In a GaN-based semiconductor device, an active layer of a GaN-based semiconductor is formed on a silicon substrate. A trench is formed in the active layer and extends from a top surface of the active layer to a depth reaching the silicon substrate. A first electrode is formed on an internal wall surface of the trench and extends from the top surface of the active layer to the silicon substrate. A second electrode is formed on the active layer to define a current path between the first electrode and the second electrode via the active layer in an on-state of the device. A bottom electrode is formed on a bottom surface of the silicon substrate and defines a bonding pad for the first electrode. The first electrode is formed of metal in direct ohmic contact with both the silicon substrate and the active layer.
摘要翻译：在GaN基半导体器件中，在硅衬底上形成GaN基半导体的有源层。在有源层中形成沟槽并从有源层的顶表面延伸到达到硅衬底的深度。第一电极形成在沟槽的内壁表面上并从有源层的顶表面延伸到硅衬底。第二电极形成在有源层上，以在器件的导通状态中经由有源层在第一电极和第二电极之间限定电流路径。底部电极形成在硅衬底的底表面上，并且限定了用于第一电极的焊盘。第一电极由与硅衬底和有源层直接欧姆接触的金属形成。

5. 发明授权

US07812371B2 GaN based semiconductor element 有权
标题翻译： GaN基半导体元件
公开(公告)号：US07812371B2
公开(公告)日：2010-10-12
申请号：US12382010
申请日：2009-03-05
申请人： Shusuke Kaya , Seikoh Yoshida , Masatoshi Ikeda, legal representative , Sadahiro Kato , Takehiko Nomura , Nariaki Ikeda , Masayuki Iwami , Yoshihiro Sato , Hiroshi Kambayashi , Yuki Niiyama
发明人： Shusuke Kaya , Seikoh Yoshida , Sadahiro Kato , Takehiko Nomura , Nariaki Ikeda , Masayuki Iwami , Yoshihiro Sato , Hiroshi Kambayashi , Yuki Niiyama
IPC分类号： H01L31/072
CPC分类号： H01L29/0847 , H01L29/0657 , H01L29/2003 , H01L29/205 , H01L29/4236 , H01L29/42376 , H01L29/66462 , H01L29/7787
摘要： The field effect transistor includes a laminated structure in which a buffer layer, and an electron transporting layer (undoped GaN layer), and an electron supplying layer (undoped AlGaN layer) are laminated in sequence on a sapphire substrate. An npn laminated structure is formed on a source region of the electron supplying layer, and a source electrode is formed on the npn laminated structure. A drain electrode is formed in a drain region of the electron supplying layer, and an insulating film is formed in an opening region formed in the gate region. When a forward voltage greater than a threshold is applied to the gate electrode, an inversion layer is formed and the drain current flows. By changing a thickness and an impurity concentration of the p-type GaN layer, the threshold voltage can be controlled. The electrical field concentration between the gate electrode and the drain electrode is relaxed due to the drift layer, and voltage resistance improves.
摘要翻译：场效应晶体管包括其中缓冲层和电子传输层（未掺杂的GaN层）和电子供体层（未掺杂的AlGaN层）依次层叠在蓝宝石衬底上的叠层结构。在电子供给层的源极区域上形成npn层叠结构，在npn层叠结构上形成源电极。在电子供给层的漏极区域中形成漏电极，并且在形成在栅极区域的开口区域中形成绝缘膜。当向栅电极施加大于阈值的正向电压时，形成反型层，漏极电流流动。通过改变p型GaN层的厚度和杂质浓度，可以控制阈值电压。由于漂移层，栅极电极和漏电极之间的电场浓度被松弛，并且耐电压提高。

6. 发明授权

US08569800B2 Field effect transistor 有权
标题翻译：场效应晶体管
公开(公告)号：US08569800B2
公开(公告)日：2013-10-29
申请号：US13076980
申请日：2011-03-31
申请人： Nariaki Ikeda , Takuya Kokawa , Masayuki Iwami , Sadahiro Kato
发明人： Nariaki Ikeda , Takuya Kokawa , Masayuki Iwami , Sadahiro Kato
IPC分类号： H01L31/072 , H01L31/0336
CPC分类号： H01L29/0847 , H01L21/02381 , H01L21/02458 , H01L21/0254 , H01L21/02579 , H01L21/0262 , H01L29/2003 , H01L29/4232 , H01L29/518 , H01L29/66462 , H01L29/7787
摘要： A field effect transistor includes: a buffer layer that is formed on a substrate; a high resistance layer or a foundation layer that is formed on the buffer layer; a carbon-containing carrier concentration controlling layer that is formed on the high resistance layer or the foundation layer; a carrier traveling layer that is formed on the carrier concentration controlling layer; a carrier supplying layer that is formed on the carrier traveling layer; a recess that is formed from the carrier supplying layer up to a predetermined depth; source/drain electrodes that are formed on the carrier supplying layer with the recess intervening therebetween; a gate insulating film that is formed on the carrier supplying layer so as to cover the recess; and a gate electrode that is formed on the gate insulating film in the recess.
摘要翻译：场效应晶体管包括：形成在衬底上的缓冲层; 形成在缓冲层上的高电阻层或基底层; 形成在高电阻层或基底层上的含碳载体浓度控制层; 载体行进层，其形成在所述载流子浓度控制层上; 形成在载体行进层上的载体供给层; 由所述载体供给层形成达预定深度的凹部; 源极/漏电极，其形成在载体供给层上，其间具有凹槽; 栅极绝缘膜，形成在所述载体供给层上以覆盖所述凹部; 以及形成在凹部中的栅极绝缘膜上的栅电极。

7. 发明申请

US20100210080A1 METHOD OF MANUFACTURING GAN-BASED TRANSISTORS 有权
标题翻译：制造基于GAN的晶体管的方法
公开(公告)号：US20100210080A1
公开(公告)日：2010-08-19
申请号：US12707376
申请日：2010-02-17
申请人： Takehiko Nomura , Nariaki Ikeda , Shusuke Kaya , Sadahiro Kato
发明人： Takehiko Nomura , Nariaki Ikeda , Shusuke Kaya , Sadahiro Kato
IPC分类号： H01L21/336
CPC分类号： H01L29/66522 , H01L29/2003 , H01L29/78
摘要： A method of manufacturing a GaN-based field effect transistor is provided by which a lower resistance and a higher breakdown voltage are obtained and which is less affected by a current collapse. A method of manufacturing the GaN-based field effect transistor(s) can comprise performing an epitaxial growth of an AlN layer (102), of a buffer layer (103), of a channel layer (104), of a drift layer (105) and of an electron supplying layer (106) in such the order on to a substrate (101) respectively; forming a recess part (108) thereon; performing an alloying process for performing an annealing in order to obtain an ohmic contact; forming a passivation layer (113) at a period of performing the annealing in the alloying process in order to protect the electron supplying layer (106) on to a surface of the recess part (108), on to the electron supplying layer (106), on to a source electrode (109) and on to a drain electrode (110), respectively; removing the passivation layer (113); forming a gate insulating film on to a surface at the inner side of the recess part (108), on to the electron supplying layer (106), on to the source electrode (109) and on to the drain electrode (110), respectively; and forming a gate electrode on to the gate insulating film at a part of the recess part (108).
摘要翻译：提供一种制造GaN基场效应晶体管的方法，通过该方法获得较低的电阻和较高的击穿电压，并且其受电流崩溃的影响较小。一种制造GaN基场效应晶体管的方法可以包括执行漂移层（105）的沟道层（104）的缓冲层（103）的AlN层（102）的外延生长）和电子供应层（106）分别依次连接到基板（101）上; 在其上形成凹部（108）; 进行合金化处理以进行退火以获得欧姆接触; 在合金化工艺中进行退火的时间段，以形成钝化层（113），以保护电子供给层（106）到凹部（108）的表面上，到电子供给层（106）上，分别连接到源电极（109）和漏电极（110）上; 去除钝化层（113）; 在所述凹部（108）的内侧的表面上分别在所述电子供给层（106）上向所述源极（109）和所述漏电极（110）分别形成栅极绝缘膜 ; 以及在所述凹部（108）的一部分处在所述栅极绝缘膜上形成栅电极。

8. 发明授权

US07943496B2 Method of manufacturing GaN-based transistors 有权
标题翻译：制造GaN基晶体管的方法
公开(公告)号：US07943496B2
公开(公告)日：2011-05-17
申请号：US12707376
申请日：2010-02-17
申请人： Takehiko Nomura , Nariaki Ikeda , Shusuke Kaya , Sadahiro Kato
发明人： Takehiko Nomura , Nariaki Ikeda , Shusuke Kaya , Sadahiro Kato
IPC分类号： H01L21/265
CPC分类号： H01L29/66522 , H01L29/2003 , H01L29/78
摘要： A method of manufacturing a GaN-based field effect transistor is provided by which a lower resistance and a higher breakdown voltage are obtained and which is less affected by a current collapse. A method of manufacturing the GaN-based field effect transistor(s) can comprise performing an epitaxial growth of an AlN layer (102), of a buffer layer (103), of a channel layer (104), of a drift layer (105) and of an electron supplying layer (106) in such the order on to a substrate (101) respectively; forming a recess part (108) thereon; performing an alloying process for performing an annealing in order to obtain an ohmic contact; forming a passivation layer (113) at a period of performing the annealing in the alloying process in order to protect the electron supplying layer (106) on to a surface of the recess part (108), on to the electron supplying layer (106), on to a source electrode (109) and on to a drain electrode (110), respectively; removing the passivation layer (113); forming a gate insulating film on to a surface at the inner side of the recess part (108), on to the electron supplying layer (106), on to the source electrode (109) and on to the drain electrode (110), respectively; and forming a gate electrode on to the gate insulating film at a part of the recess part (108).
摘要翻译：提供一种制造GaN基场效应晶体管的方法，通过该方法获得较低的电阻和较高的击穿电压，并且其受电流崩溃的影响较小。一种制造GaN基场效应晶体管的方法可以包括执行漂移层（105）的沟道层（104）的缓冲层（103）的AlN层（102）的外延生长）和电子供应层（106）分别依次连接到基板（101）上; 在其上形成凹部（108）; 进行合金化处理以进行退火以获得欧姆接触; 在合金化工艺中进行退火的时间段，以形成钝化层（113），以保护电子供给层（106）到凹部（108）的表面上，到电子供给层（106）上，分别连接到源电极（109）和漏电极（110）上; 去除钝化层（113）; 在所述凹部（108）的内侧的表面上分别在所述电子供给层（106）上向所述源极（109）和所述漏电极（110）分别形成栅极绝缘膜 ; 以及在所述凹部（108）的一部分处在所述栅极绝缘膜上形成栅电极。

9. 发明申请

US20100117186A1 Semiconductor device and method of producing the same 审中-公开
标题翻译：半导体装置及其制造方法
公开(公告)号：US20100117186A1
公开(公告)日：2010-05-13
申请号：US12457904
申请日：2009-06-24
申请人： Hiroshi Kambayashi , Shusuke Kaya , Nariaki Ikeda
发明人： Hiroshi Kambayashi , Shusuke Kaya , Nariaki Ikeda
IPC分类号： H01L29/47 , H01L21/28 , H01L21/82
CPC分类号： H01L29/0657 , H01L29/2003 , H01L29/402 , H01L29/42316 , H01L29/475 , H01L29/66462 , H01L29/7787
摘要： The invention provides a semiconductor device and a method for fabricating the same capable of preventing a field plate portion from being delaminated from an insulating film by stress inherent in a semiconductor layer even if the stress is released in forming a trench in part of the semiconductor layer where the semiconductor device is to be separated and capable of having a higher breakdown property of the semiconductor device. The semiconductor device has source, drain and gate electrodes, insulating films that insulate the electrodes on an electron supplying layer and a mesa-structure formed at part where the semiconductor device is to be separated. The gate electrode has a first electrode layer having a function of the electrode and a second electrode layer having a field plate portion whose part that contacts with the insulating film is made of a metallic material that adheres well to the insulating film.
摘要翻译：本发明提供一种半导体器件及其制造方法，其能够通过半导体层中固有的应力防止场板部分与绝缘膜分层，即使在半导体层的一部分中形成沟槽时释放应力其中半导体器件将被分离并且能够具有较高的半导体器件的击穿特性。半导体器件具有源极，漏极和栅极电极，使电极在电子供给层上绝缘的绝缘膜和在半导体器件将被分离的部分处形成的台面结构。栅电极具有具有电极功能的第一电极层和具有场板部分的第二电极层，其与绝缘膜接触的部分由与绝缘膜良好结合的金属材料制成。

10. 发明授权

US08525225B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08525225B2
公开(公告)日：2013-09-03
申请号：US11511293
申请日：2006-08-29
申请人： Hiroshi Kambayashi , Nariaki Ikeda , Seikoh Yoshida
发明人： Hiroshi Kambayashi , Nariaki Ikeda , Seikoh Yoshida
IPC分类号： H01L29/739
CPC分类号： H01L29/7787 , H01L23/3171 , H01L29/2003 , H01L2924/0002 , H01L2924/13063 , H01L2924/13091 , H01L2924/00
摘要： A semiconductor device includes a plurality of electrodes arranged on a compound semiconductor layer grown on a substrate, and a surface protection film that protects a surface of a semiconductor layer on the compound semiconductor layer between the electrodes. A refractive index of the surface protection film is controlled so that a stress caused by the surface protection film on the surface of the semiconductor layer is minimized.
摘要翻译：半导体器件包括布置在生长在衬底上的化合物半导体层上的多个电极以及保护电极之间的化合物半导体层上的半导体层的表面的表面保护膜。控制表面保护膜的折射率使得由半导体层表面上的表面保护膜引起的应力最小化。

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