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1. 发明专利

JP2011071453A Light source comprising led chip, lens and lens holder 审中-公开
标题翻译：包含LED芯片，镜头和镜头支架的光源
公开(公告)号：JP2011071453A
公开(公告)日：2011-04-07
申请号：JP2009239820
申请日：2009-09-24
申请人： Masayoshi Yoshimura , 正義吉村
发明人： YOSHIMURA MASAYOSHI
IPC分类号： H01L33/58
摘要： PROBLEM TO BE SOLVED: To efficiently collect light by collecting light emitted from an LED chip without waste. SOLUTION: In this light source comprising an LED chip, a lens and a lens holder, the size of a first lens including the LED chip is set to 2.25-2.5 times of the size of the LED chip by combining three or four lenses each having a magnification of 1.25-1.38 with the LED chip, whereby collection efficiency is further improved, light emitted from the LED chip can be collected without waste, and the light can be efficiently collected. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：通过收集从LED芯片发出的光来有效地收集光，而不浪费。解决方案：在包括LED芯片，透镜和透镜架的光源中，包括LED芯片的第一透镜的尺寸被设置为LED芯片尺寸的2.25-2.5倍，通过组合三个或四个具有LED芯片的放大率为1.25-1.38的透镜，从而进一步提高收集效率，可以无废弃地收集从LED芯片发出的光，并且可以有效地收集光。版权所有（C）2011，JPO＆INPIT

2. 发明申请

US20070250284A1 Semiconductor integrated circuit and testing method for the same 审中-公开
公开(公告)号：US20070250284A1
公开(公告)日：2007-10-25
申请号：US11711644
申请日：2007-02-28
申请人： Sadami Takeoka , Mitsuyasu Ohta , Osamu Ichikawa , Masayoshi Yoshimura , Takashi Ishimura
发明人： Sadami Takeoka , Mitsuyasu Ohta , Osamu Ichikawa , Masayoshi Yoshimura , Takashi Ishimura
IPC分类号： G01R31/3187
CPC分类号： G11C29/12015 , G01R31/318552 , G01R31/31858 , G11C29/50012 , H03L7/00 , H03L7/06
摘要： A semiconductor integrated circuit of the present invention is provided with a clock control portion having a clock generation portion for generating a clock signal and an output command signal input portion for receiving a clock output command signal from the outside, and an internal circuit controlled by an output clock signal that is output from the clock control portion, and the clock control portion is configured so that it outputs the output clock signal to the internal circuit when a certain time period has passed from a time when the output command signal is received.

3. 发明授权

US07197725B2 Semiconductor integrated circuit and testing method for the same 有权
标题翻译：半导体集成电路和测试方法相同
公开(公告)号：US07197725B2
公开(公告)日：2007-03-27
申请号：US10187413
申请日：2002-07-02
申请人： Sadami Takeoka , Mitsuyasu Ohta , Osamu Ichikawa , Masayoshi Yoshimura , Takashi Ishimura
发明人： Sadami Takeoka , Mitsuyasu Ohta , Osamu Ichikawa , Masayoshi Yoshimura , Takashi Ishimura
IPC分类号： G06F17/50
CPC分类号： G11C29/12015 , G01R31/318552 , G01R31/31858 , G11C29/50012 , H03L7/00 , H03L7/06
摘要： A semiconductor integrated circuit of the present invention is provided with a clock control portion having a clock generation portion for generating a clock signal and an output command signal input portion for receiving a clock output command signal from the outside, and an internal circuit controlled by an output clock signal that is output from the clock control portion, and the clock control portion is configured so that it outputs the output clock signal to the internal circuit when a certain time period has passed from a time when the output command signal is received.
摘要翻译：本发明的半导体集成电路设置有时钟控制部分，其具有用于产生时钟信号的时钟产生部分和用于从外部接收时钟输出命令信号的输出命令信号输入部分和由外部控制的内部电路输出时钟信号，并且时钟控制部分被配置为使得当从接收到输出命令信号的时间过去一段时间时，它将输出时钟信号输出到内部电路。

4. 发明授权

US3990092A Resistance element for semiconductor integrated circuit 失效
标题翻译：半导体集成电路用电阻元件
公开(公告)号：US3990092A
公开(公告)日：1976-11-02
申请号：US540340
申请日：1975-01-13
申请人： Masayoshi Yoshimura
发明人： Masayoshi Yoshimura
IPC分类号： H01L27/06 , H01L27/08 , H01L29/8605 , H01L27/04
CPC分类号： H01L27/0652 , H01L27/0802 , H01L29/8605
摘要： A semiconductor integrated circuit contains a resistance element, wherein a low resistance region of a first conductivity type, employed for a circuit resistance, is formed within a high resistance region of a second conductivity type, opposite to the first conductivity type. The low resistance region and the high resistance region are connected in parallel, so as to prevent the formation of a parasitic transistor and a parasitic thyristor.
摘要翻译：半导体集成电路包括电阻元件，其中用于电路电阻的第一导电类型的低电阻区域形成在与第一导电类型相反的第二导电类型的高电阻区域内。低电阻区域和高电阻区域并联连接，以防止形成寄生晶体管和寄生晶闸管。

5. 发明授权

US07348595B2 Semiconductor wiring substrate, semiconductor device, method for testing semiconductor device, and method for mounting semiconductor device 失效
标题翻译：半导体配线基板，半导体装置，半导体装置的测试方法以及半导体装置的安装方法
公开(公告)号：US07348595B2
公开(公告)日：2008-03-25
申请号：US10828492
申请日：2004-04-21
申请人： Sadami Takeoka , Mitsuyasu Ohta , Osamu Ichikawa , Masayoshi Yoshimura
发明人： Sadami Takeoka , Mitsuyasu Ohta , Osamu Ichikawa , Masayoshi Yoshimura
IPC分类号： G11C5/02
CPC分类号： G01R31/28 , G01R31/318505 , G01R31/318538 , G01R31/318558 , G06F17/50 , G11C5/02 , G11C5/025 , G11C29/48 , G11C2029/3202 , H01L23/12
摘要： A semiconductor device constructed by mounting a plurality of chip intellectual properties (IPs) on a common semiconductor wiring substrate, a method for testing the device and a method for mounting the chip IPs. A silicon wiring substrate on which chip IPs can be mounted is provided. A circuit for a boundary scan test is formed on the silicon wiring substrate by connecting flip flops. The flip flops are connected to wiring and are arranged to test connections in the wiring. The entire IP On Super-Sub (IPOS) device or each chip IP may be arranged to facilitate a scan test, a built-in self-test (BIST), etc., on the internal circuit of the chip IP.
摘要翻译：通过将多个芯片智能特性（IP）安装在公共半导体布线基板上构成的半导体器件，测试器件的方法和安装芯片IP的方法。提供了可以安装芯片IP的硅布线基板。通过连接触发器在硅布线基板上形成用于边界扫描测试的电路。触发器连接到布线并被布置成测试布线中的连接。整个IP On Super Sub（IPOS）设备或每个芯片IP可以被布置成便于在芯片IP的内部电路上进行扫描测试，内置自检（BIST）等。

6. 发明授权

US07032196B2 Semiconductor wiring substrate, semiconductor device, method for testing semiconductor device, and method for mounting semiconductor device 失效
公开(公告)号：US07032196B2
公开(公告)日：2006-04-18
申请号：US10828230
申请日：2004-04-21
申请人： Sadami Takeoka , Mitsuyasu Ohta , Osamu Ichikawa , Masayoshi Yoshimura
发明人： Sadami Takeoka , Mitsuyasu Ohta , Osamu Ichikawa , Masayoshi Yoshimura
IPC分类号： G06F17/50 , H01L23/58 , G01R31/28
CPC分类号： G01R31/28 , G01R31/318505 , G01R31/318538 , G01R31/318558 , G06F17/50 , G11C5/02 , G11C5/025 , G11C29/48 , G11C2029/3202 , H01L23/12
摘要： A semiconductor device constructed by mounting a plurality of chip intellectual properties (IPs) on a common semiconductor wiring substrate, a method for testing the device and a method for mounting the chip IPs. A silicon wiring substrate on which chip IPs can be mounted is provided. A circuit for a boundary scan test is formed on the silicon wiring substrate by connecting flip flops. The flip flops are connected to wiring and are arranged to test connections in the wiring. The entire IP On Super-Sub (IPOS) device or each chip IP may be arranged to facilitate a scan test, a built-in self-test (BIST), etc., on the internal circuit of the chip IP.

7. 发明授权

US06734549B2 Semiconductor device having a device for testing the semiconductor 失效
标题翻译：具有用于测试半导体的器件的半导体器件
公开(公告)号：US06734549B2
公开(公告)日：2004-05-11
申请号：US10187269
申请日：2002-07-02
申请人： Sadami Takeoka , Mitsuyasu Ohta , Osamu Ichikawa , Masayoshi Yoshimura
发明人： Sadami Takeoka , Mitsuyasu Ohta , Osamu Ichikawa , Masayoshi Yoshimura
IPC分类号： H01L2312
CPC分类号： G01R31/28 , G01R31/318505 , G01R31/318538 , G01R31/318558 , G06F17/50 , G11C5/02 , G11C5/025 , G11C29/48 , G11C2029/3202 , H01L23/12
摘要： A semiconductor device constructed by mounting a plurality of chip intellectual properties (IPs) on a common semiconductor wiring substrate, a method for testing the device and a method for mounting the chip IPs. A silicon wiring substrate on which chip IPs can be mounted is provided. A circuit for a boundary scan test is formed on the silicon wiring substrate by connecting flip flops. The flip flops are connected to wiring and are arranged to test connections in the wiring. The entire IP On Super-Sub (IPOS) device or each chip IP may be arranged to facilitate a scan test, a built-in self-test (BIST), etc., on the internal circuit of the chip IP.
摘要翻译：通过将多个芯片智能特性（IP）安装在公共半导体布线基板上构成的半导体器件，测试器件的方法和安装芯片IP的方法。提供了可以安装芯片IP的硅布线基板。通过连接触发器在硅布线基板上形成用于边界扫描测试的电路。触发器连接到布线并被布置成测试布线中的连接。整个IP On Super Sub（IPOS）设备或每个芯片IP可以被布置成便于在芯片IP的内部电路上进行扫描测试，内置自检（BIST）等。

8. 发明授权

US4689503A Level conversion circuitry for a semiconductor integrated circuit utilizing bis CMOS circuit elements 失效
标题翻译：利用双CMOS电路元件的半导体集成电路的电平转换电路
公开(公告)号：US4689503A
公开(公告)日：1987-08-25
申请号：US575567
申请日：1984-01-31
申请人： Yukio Suzuki , Ikuro Masuda , Masahiro Iwamura , Shinji Kadono , Akira Uragami , Masayoshi Yoshimura , Toshiaki Matsubara
发明人： Yukio Suzuki , Ikuro Masuda , Masahiro Iwamura , Shinji Kadono , Akira Uragami , Masayoshi Yoshimura , Toshiaki Matsubara
IPC分类号： H03K19/00 , H03K19/0175 , H03K19/018 , H03K19/094 , H03K19/0944 , H03K19/177 , H03K19/01 , H03K19/013 , H03K19/017
CPC分类号： H03K19/09448 , H03K19/017518 , H03K19/01806 , H03K19/09425 , H03K19/09429 , H01L2924/0002
摘要： In an input level converter for TTL-CMOS level conversion (or other conversion to CMOS) for an internal logic block operating with CMOS levels, an output transistor for executing the charge or discharge of the output capacitance thereof is formed of a bipolar transistor. Thus, the propagation delay times and their capacitance-dependencies of the input level converter can be lessened. Similarly, in an output level converter for CMOS-TTL level conversion (or other conversion from CMOS) for the internal logic block operating with the CMOS levels, an output transistor for executing the charge or discharge of the output load capacitance thereof is formed of a bipolar transistor. Thus, the propagation delay times and their capacitance-dependencies of the output level converter can also be lessened.
摘要翻译：在用于CMOS电平工作的内部逻辑块的TTL-CMOS电平转换（或其他转换为CMOS）的输入电平转换器中，用于执行其输出电容的充电或放电的输出晶体管由双极晶体管形成。因此，可以减小输入电平转换器的传播延迟时间及其电容依赖性。类似地，在用于CMOS电平操作的内部逻辑块的用于CMOS-TTL电平转换（或来自CMOS的其它转换）的输出电平转换器中，用于执行其输出负载电容的充电或放电的输出晶体管由双极晶体管。因此，也可以减小输出电平转换器的传播延迟时间及其电容依赖性。

9. 发明授权

US4423433A High-breakdown-voltage resistance element for integrated circuit with a plurality of multilayer, overlapping electrodes 失效
标题翻译：具有多个多层重叠电极的集成电路的高耐击穿电压元件
公开(公告)号：US4423433A
公开(公告)日：1983-12-27
申请号：US156015
申请日：1980-06-03
申请人： Ichiro Imaizumi , Shikayuki Ochi , Masatoshi Kimura , Masayoshi Yoshimura , Takashi Yamaguchi , Toyomasa Koda
发明人： Ichiro Imaizumi , Shikayuki Ochi , Masatoshi Kimura , Masayoshi Yoshimura , Takashi Yamaguchi , Toyomasa Koda
IPC分类号： H01L27/04 , H01L21/822 , H01L29/41 , H01L29/8605 , H01L27/02
CPC分类号： H01L29/8605
摘要： A high-breakdown-voltage resistance element comprises a semiconductor body, an impurity layer disposed in a surface region of the semiconductor body to provide a resistor body, a first electrode connected to one end of the resistor body through a contact hole in a first insulating film formed on the surface of the semiconductor body, and a second electrode connected to the other end of the resistor body through another contact hole in the insulating film. A second insulating film is formed on the first and second electrodes, and a third electrode is connected to the first electrode through a contact hole in the second insulating film, so that the entire surface of the resistor body and adjacent areas are covered with the first, second and third electrodes.
摘要翻译：高耐压电阻元件包括半导体本体，设置在半导体本体的表面区域中以提供电阻体的杂质层，通过第一绝缘体中的接触孔与电阻体的一端连接的第一电极形成在半导体本体的表面上的膜，以及通过绝缘膜中的另一接触孔与电阻体的另一端连接的第二电极。第二绝缘膜形成在第一和第二电极上，第三电极通过第二绝缘膜中的接触孔连接到第一电极，使得电阻体和相邻区域的整个表面被第一电极，第二和第三电极。

10. 发明授权

US4021687A Transistor circuit for deep saturation prevention 失效
标题翻译：用于深度饱和预防的晶体管电路
公开(公告)号：US4021687A
公开(公告)日：1977-05-03
申请号：US629625
申请日：1975-11-05
申请人： Masayoshi Yoshimura
发明人： Masayoshi Yoshimura
IPC分类号： H01L21/331 , H01L21/8228 , H01L27/082 , H01L29/73 , H03K17/0422 , H03K3/33
CPC分类号： H03K17/0422 , H01L27/0821
摘要： A transistor circuit which comprises a first transistor of the N-P-N type, a second transistor of the P-N-P type and a third transistor of the N-P-N type, and in which a base of the first transistor, an emitter of the second transistor and a collector of the third transistor are electrically connected with one another, while a collector of the first transistor and a base of the second transistor are electrically connected with each other, whereby the first transistor is prevented from being driven into an extremely deep saturation region.
摘要翻译：一种晶体管电路，其包括NPN型的第一晶体管，PNP型的第二晶体管和NPN型的第三晶体管，并且其中第一晶体管的基极，第二晶体管的发射极和第二晶体管的集电极第三晶体管彼此电连接，而第一晶体管的集电极和第二晶体管的基极彼此电连接，由此防止第一晶体管被驱动到极深的饱和区域。

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