专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20070250284A1 Semiconductor integrated circuit and testing method for the same 审中-公开
公开(公告)号：US20070250284A1
公开(公告)日：2007-10-25
申请号：US11711644
申请日：2007-02-28
申请人： Sadami Takeoka , Mitsuyasu Ohta , Osamu Ichikawa , Masayoshi Yoshimura , Takashi Ishimura
发明人： Sadami Takeoka , Mitsuyasu Ohta , Osamu Ichikawa , Masayoshi Yoshimura , Takashi Ishimura
IPC分类号： G01R31/3187
CPC分类号： G11C29/12015 , G01R31/318552 , G01R31/31858 , G11C29/50012 , H03L7/00 , H03L7/06
摘要： A semiconductor integrated circuit of the present invention is provided with a clock control portion having a clock generation portion for generating a clock signal and an output command signal input portion for receiving a clock output command signal from the outside, and an internal circuit controlled by an output clock signal that is output from the clock control portion, and the clock control portion is configured so that it outputs the output clock signal to the internal circuit when a certain time period has passed from a time when the output command signal is received.

2. 发明授权

US07197725B2 Semiconductor integrated circuit and testing method for the same 有权
标题翻译：半导体集成电路和测试方法相同
公开(公告)号：US07197725B2
公开(公告)日：2007-03-27
申请号：US10187413
申请日：2002-07-02
申请人： Sadami Takeoka , Mitsuyasu Ohta , Osamu Ichikawa , Masayoshi Yoshimura , Takashi Ishimura
发明人： Sadami Takeoka , Mitsuyasu Ohta , Osamu Ichikawa , Masayoshi Yoshimura , Takashi Ishimura
IPC分类号： G06F17/50
CPC分类号： G11C29/12015 , G01R31/318552 , G01R31/31858 , G11C29/50012 , H03L7/00 , H03L7/06
摘要： A semiconductor integrated circuit of the present invention is provided with a clock control portion having a clock generation portion for generating a clock signal and an output command signal input portion for receiving a clock output command signal from the outside, and an internal circuit controlled by an output clock signal that is output from the clock control portion, and the clock control portion is configured so that it outputs the output clock signal to the internal circuit when a certain time period has passed from a time when the output command signal is received.
摘要翻译：本发明的半导体集成电路设置有时钟控制部分，其具有用于产生时钟信号的时钟产生部分和用于从外部接收时钟输出命令信号的输出命令信号输入部分和由外部控制的内部电路输出时钟信号，并且时钟控制部分被配置为使得当从接收到输出命令信号的时间过去一段时间时，它将输出时钟信号输出到内部电路。

3. 发明授权

US07512853B2 Semiconductor integrated circuit and method for testing the same 有权
公开(公告)号：US07512853B2
公开(公告)日：2009-03-31
申请号：US11266406
申请日：2005-11-04
申请人： Takashi Ishimura , Sadami Takeoka
发明人： Takashi Ishimura , Sadami Takeoka
IPC分类号： G01R31/28 , G06F11/00 , G06F1/26 , G06F1/00
摘要： In a semiconductor integrated circuit, power source wiring for supplying power supply voltage to a plurality of flip flop circuits, and power source wiring for supplying different power supply voltage to a combinational circuit are provided individually, so that the power supply to the flip flop circuits and the power supply to the combinational circuit can be performed separately from, and independently of, each other. During shift operation in scan testing, the power supply voltage to the combinational circuit is set to a low voltage or cut off, thereby suppressing the amount of power consumed by the combinational circuit portion during the shift operation. At the same time, the power supply voltage to the flip flop circuits is set to a high voltage during the shift operation.

4. 发明申请

US20090164860A1 SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD FOR TESTING THE SAME 有权
标题翻译：半导体集成电路及其测试方法
公开(公告)号：US20090164860A1
公开(公告)日：2009-06-25
申请号：US12390761
申请日：2009-02-23
申请人： Takashi Ishimura , Sadami Takeoka
发明人： Takashi Ishimura , Sadami Takeoka
IPC分类号： G01R31/3177 , G06F11/25 , G01R31/3187
CPC分类号： G01R31/318575
摘要： In a semiconductor integrated circuit, power source wiring for supplying power supply voltage to a plurality of flip flop circuits, and power source wiring for supplying different power supply voltage to a combinational circuit are provided individually, so that the power supply to the flip flop circuits and the power supply to the combinational circuit can be performed separately from, and independently of, each other. During shift operation in scan testing, the power supply voltage to the combinational circuit is set to a low voltage or cut off, thereby suppressing the amount of power consumed by the combinational circuit portion during the shift operation. At the same time, the power supply voltage to the flip flop circuits is set to a high voltage during the shift operation.
摘要翻译：在半导体集成电路中，分别设置用于向多个触发电路提供电源电压的电源布线和用于向组合电路提供不同的电源电压的电源布线，使得向触发电路的电源并且组合电路的电源可以独立于彼此独立地执行。在扫描测试中的移位操作期间，组合电路的电源电压被设置为低电压或截止，从而抑制在移位操作期间组合电路部分消耗的功率量。同时，在换档操作期间，触发电路的电源电压被设定为高电压。

5. 发明申请

US20060174176A1 Semiconductor integrated circuit and method for testing the same 有权
公开(公告)号：US20060174176A1
公开(公告)日：2006-08-03
申请号：US11266406
申请日：2005-11-04
申请人： Takashi Ishimura , Sadami Takeoka
发明人： Takashi Ishimura , Sadami Takeoka
IPC分类号： G01R31/28
CPC分类号： G01R31/318575
摘要： In a semiconductor integrated circuit, power source wiring for supplying power supply voltage to a plurality of flip flop circuits, and power source wiring for supplying different power supply voltage to a combinational circuit are provided individually, so that the power supply to the flip flop circuits and the power supply to the combinational circuit can be performed separately from, and independently of, each other. During shift operation in scan testing, the power supply voltage to the combinational circuit is set to a low voltage or cut off, thereby suppressing the amount of power consumed by the combinational circuit portion during the shift operation. At the same time, the power supply voltage to the flip flop circuits is set to a high voltage during the shift operation.

6. 发明授权

US07610533B2 Semiconductor integrated circuit and method for testing the same 有权
标题翻译：半导体集成电路及其测试方法
公开(公告)号：US07610533B2
公开(公告)日：2009-10-27
申请号：US11266406
申请日：2005-11-04
申请人： Takashi Ishimura , Sadami Takeoka
发明人： Takashi Ishimura , Sadami Takeoka
IPC分类号： G01R31/28 , G06F11/00 , G06F1/26 , G06F1/00
CPC分类号： G01R31/318575
摘要： In a semiconductor integrated circuit, power source wiring for supplying power supply voltage to a plurality of flip flop circuits, and power source wiring for supplying different power supply voltage to a combinational circuit are provided individually, so that the power supply to the flip flop circuits and the power supply to the combinational circuit can be performed separately from, and independently of, each other. During shift operation in scan testing, the power supply voltage to the combinational circuit is set to a low voltage or cut off, thereby suppressing the amount of power consumed by the combinational circuit portion during the shift operation. At the same time, the power supply voltage to the flip flop circuits is set to a high voltage during the shift operation.
摘要翻译：在半导体集成电路中，分别设置用于向多个触发电路提供电源电压的电源布线和用于向组合电路提供不同的电源电压的电源布线，使得向触发电路的电源并且组合电路的电源可以独立于彼此独立地执行。在扫描测试中的移位操作期间，组合电路的电源电压被设置为低电压或截止，从而抑制在移位操作期间组合电路部分消耗的功率量。同时，在换档操作期间，触发电路的电源电压被设定为高电压。

7. 发明授权

US07590908B2 Semiconductor integrated circuit and method for testing the same 有权
公开(公告)号：US07590908B2
公开(公告)日：2009-09-15
申请号：US12390761
申请日：2009-02-23
申请人： Takashi Ishimura , Sadami Takeoka
发明人： Takashi Ishimura , Sadami Takeoka
IPC分类号： G01R31/28 , G06F11/00 , G06F1/26 , G01F1/00
CPC分类号： G01R31/318575
摘要： In a semiconductor integrated circuit, power source wiring for supplying power supply voltage to a plurality of flip flop circuits, and power source wiring for supplying different power supply voltage to a combinational circuit are provided individually, so that the power supply to the flip flop circuits and the power supply to the combinational circuit can be performed separately from, and independently of, each other. During shift operation in scan testing, the power supply voltage to the combinational circuit is set to a low voltage or cut off, thereby suppressing the amount of power consumed by the combinational circuit portion during the shift operation. At the same time, the power supply voltage to the flip flop circuits is set to a high voltage during the shift operation.

8. 发明申请

US20070089014A1 Semiconductor integrated circuit and method of fabricating the same 审中-公开
标题翻译：半导体集成电路及其制造方法
公开(公告)号：US20070089014A1
公开(公告)日：2007-04-19
申请号：US11542271
申请日：2006-10-04
申请人： Takashi Ishimura , Kenichiro Uda , Yoko Shimada , Katsuya Fujimura , Kasumi Hamaguchi , Kenichirou Higashi
发明人： Takashi Ishimura , Kenichiro Uda , Yoko Shimada , Katsuya Fujimura , Kasumi Hamaguchi , Kenichirou Higashi
IPC分类号： G01R31/28 , G06F11/00
CPC分类号： G01R31/2884 , G01R31/318364
摘要： To provide a semiconductor integrated circuit device in which an occupied area is suppressed from increasing and a high-performance test circuit is included, There is provided a semiconductor integrated circuit having a test circuit, by determining arrangement positions of cells forming a circuit to be tested and non-connected cells prepared to form a test circuit and then determining a connection relationship among the non-connected cells prepared to form the test circuit on the basis of the arrangement information to thereby form the test circuit.
摘要翻译：提供一种半导体集成电路器件，其中抑制占用面积增加并且包括高性能测试电路。提供了一种具有测试电路的半导体集成电路，通过确定形成被测电路的单元的布置位置和非连接的单元，准备形成测试电路，然后根据布置信息确定准备好形成测试电路的非连接单元之间的连接关系，从而形成测试电路。

9. 发明申请

US20070083844A1 Logic circuit design support apparatus, and logic circuit design support method employing this apparatus 审中-公开
标题翻译：采用该装置的逻辑电路设计支持装置和逻辑电路设计支持方法
公开(公告)号：US20070083844A1
公开(公告)日：2007-04-12
申请号：US11542272
申请日：2006-10-04
申请人： Chie Kabuo , Yoko Shimada , Kasumi Hamaguchi , Takashi Ishimura , Katsuya Fujimura
发明人： Chie Kabuo , Yoko Shimada , Kasumi Hamaguchi , Takashi Ishimura , Katsuya Fujimura
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： A circuit structure analysis unit performs structure analysis for logic circuit information, obtained from an HDL description, and acquires analysis results for function parts, such as a register, an operation unit and a multiplexer. A synthesis instruction generation unit compares the analysis results with a synthesis instruction correlation rule, and automatically generates a synthesis instruction to control a logic synthesis method. Finally, an HDL description output unit outputs a synthesis instruction added HDL description, wherein a synthesis instruction is inserted into the original HDL description. When the synthesis instruction added HDL description is employed in the logic synthesis, starting at the top hierarchical level, a synthesis instruction for the logic circuit is not required in a synthesis execution script.
摘要翻译：电路结构分析单元对从HDL描述获得的逻辑电路信息进行结构分析，并且获取诸如寄存器，操作单元和多路复用器等功能部件的分析结果。合成指令生成单元将分析结果与合成指令相关规则进行比较，并且自动生成用于控制逻辑合成方法的合成指令。最后，HDL描述输出单元输出合成指令相加的HDL描述，其中合成指令插入到原始HDL描述中。当合成指令在逻辑合成中被加入HDL描述时，从顶层开始，在合成执行脚本中不需要逻辑电路的合成指令。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式