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1. 发明申请

US20070250284A1 Semiconductor integrated circuit and testing method for the same 审中-公开
公开(公告)号：US20070250284A1
公开(公告)日：2007-10-25
申请号：US11711644
申请日：2007-02-28
申请人： Sadami Takeoka , Mitsuyasu Ohta , Osamu Ichikawa , Masayoshi Yoshimura , Takashi Ishimura
发明人： Sadami Takeoka , Mitsuyasu Ohta , Osamu Ichikawa , Masayoshi Yoshimura , Takashi Ishimura
IPC分类号： G01R31/3187
CPC分类号： G11C29/12015 , G01R31/318552 , G01R31/31858 , G11C29/50012 , H03L7/00 , H03L7/06
摘要： A semiconductor integrated circuit of the present invention is provided with a clock control portion having a clock generation portion for generating a clock signal and an output command signal input portion for receiving a clock output command signal from the outside, and an internal circuit controlled by an output clock signal that is output from the clock control portion, and the clock control portion is configured so that it outputs the output clock signal to the internal circuit when a certain time period has passed from a time when the output command signal is received.

2. 发明授权

US07197725B2 Semiconductor integrated circuit and testing method for the same 有权
标题翻译：半导体集成电路和测试方法相同
公开(公告)号：US07197725B2
公开(公告)日：2007-03-27
申请号：US10187413
申请日：2002-07-02
申请人： Sadami Takeoka , Mitsuyasu Ohta , Osamu Ichikawa , Masayoshi Yoshimura , Takashi Ishimura
发明人： Sadami Takeoka , Mitsuyasu Ohta , Osamu Ichikawa , Masayoshi Yoshimura , Takashi Ishimura
IPC分类号： G06F17/50
CPC分类号： G11C29/12015 , G01R31/318552 , G01R31/31858 , G11C29/50012 , H03L7/00 , H03L7/06
摘要： A semiconductor integrated circuit of the present invention is provided with a clock control portion having a clock generation portion for generating a clock signal and an output command signal input portion for receiving a clock output command signal from the outside, and an internal circuit controlled by an output clock signal that is output from the clock control portion, and the clock control portion is configured so that it outputs the output clock signal to the internal circuit when a certain time period has passed from a time when the output command signal is received.
摘要翻译：本发明的半导体集成电路设置有时钟控制部分，其具有用于产生时钟信号的时钟产生部分和用于从外部接收时钟输出命令信号的输出命令信号输入部分和由外部控制的内部电路输出时钟信号，并且时钟控制部分被配置为使得当从接收到输出命令信号的时间过去一段时间时，它将输出时钟信号输出到内部电路。

3. 发明授权

US07348595B2 Semiconductor wiring substrate, semiconductor device, method for testing semiconductor device, and method for mounting semiconductor device 失效
标题翻译：半导体配线基板，半导体装置，半导体装置的测试方法以及半导体装置的安装方法
公开(公告)号：US07348595B2
公开(公告)日：2008-03-25
申请号：US10828492
申请日：2004-04-21
申请人： Sadami Takeoka , Mitsuyasu Ohta , Osamu Ichikawa , Masayoshi Yoshimura
发明人： Sadami Takeoka , Mitsuyasu Ohta , Osamu Ichikawa , Masayoshi Yoshimura
IPC分类号： G11C5/02
CPC分类号： G01R31/28 , G01R31/318505 , G01R31/318538 , G01R31/318558 , G06F17/50 , G11C5/02 , G11C5/025 , G11C29/48 , G11C2029/3202 , H01L23/12
摘要： A semiconductor device constructed by mounting a plurality of chip intellectual properties (IPs) on a common semiconductor wiring substrate, a method for testing the device and a method for mounting the chip IPs. A silicon wiring substrate on which chip IPs can be mounted is provided. A circuit for a boundary scan test is formed on the silicon wiring substrate by connecting flip flops. The flip flops are connected to wiring and are arranged to test connections in the wiring. The entire IP On Super-Sub (IPOS) device or each chip IP may be arranged to facilitate a scan test, a built-in self-test (BIST), etc., on the internal circuit of the chip IP.
摘要翻译：通过将多个芯片智能特性（IP）安装在公共半导体布线基板上构成的半导体器件，测试器件的方法和安装芯片IP的方法。提供了可以安装芯片IP的硅布线基板。通过连接触发器在硅布线基板上形成用于边界扫描测试的电路。触发器连接到布线并被布置成测试布线中的连接。整个IP On Super Sub（IPOS）设备或每个芯片IP可以被布置成便于在芯片IP的内部电路上进行扫描测试，内置自检（BIST）等。

4. 发明授权

US07032196B2 Semiconductor wiring substrate, semiconductor device, method for testing semiconductor device, and method for mounting semiconductor device 失效
公开(公告)号：US07032196B2
公开(公告)日：2006-04-18
申请号：US10828230
申请日：2004-04-21
申请人： Sadami Takeoka , Mitsuyasu Ohta , Osamu Ichikawa , Masayoshi Yoshimura
发明人： Sadami Takeoka , Mitsuyasu Ohta , Osamu Ichikawa , Masayoshi Yoshimura
IPC分类号： G06F17/50 , H01L23/58 , G01R31/28
CPC分类号： G01R31/28 , G01R31/318505 , G01R31/318538 , G01R31/318558 , G06F17/50 , G11C5/02 , G11C5/025 , G11C29/48 , G11C2029/3202 , H01L23/12
摘要： A semiconductor device constructed by mounting a plurality of chip intellectual properties (IPs) on a common semiconductor wiring substrate, a method for testing the device and a method for mounting the chip IPs. A silicon wiring substrate on which chip IPs can be mounted is provided. A circuit for a boundary scan test is formed on the silicon wiring substrate by connecting flip flops. The flip flops are connected to wiring and are arranged to test connections in the wiring. The entire IP On Super-Sub (IPOS) device or each chip IP may be arranged to facilitate a scan test, a built-in self-test (BIST), etc., on the internal circuit of the chip IP.

5. 发明授权

US06734549B2 Semiconductor device having a device for testing the semiconductor 失效
标题翻译：具有用于测试半导体的器件的半导体器件
公开(公告)号：US06734549B2
公开(公告)日：2004-05-11
申请号：US10187269
申请日：2002-07-02
申请人： Sadami Takeoka , Mitsuyasu Ohta , Osamu Ichikawa , Masayoshi Yoshimura
发明人： Sadami Takeoka , Mitsuyasu Ohta , Osamu Ichikawa , Masayoshi Yoshimura
IPC分类号： H01L2312
CPC分类号： G01R31/28 , G01R31/318505 , G01R31/318538 , G01R31/318558 , G06F17/50 , G11C5/02 , G11C5/025 , G11C29/48 , G11C2029/3202 , H01L23/12
摘要： A semiconductor device constructed by mounting a plurality of chip intellectual properties (IPs) on a common semiconductor wiring substrate, a method for testing the device and a method for mounting the chip IPs. A silicon wiring substrate on which chip IPs can be mounted is provided. A circuit for a boundary scan test is formed on the silicon wiring substrate by connecting flip flops. The flip flops are connected to wiring and are arranged to test connections in the wiring. The entire IP On Super-Sub (IPOS) device or each chip IP may be arranged to facilitate a scan test, a built-in self-test (BIST), etc., on the internal circuit of the chip IP.
摘要翻译：通过将多个芯片智能特性（IP）安装在公共半导体布线基板上构成的半导体器件，测试器件的方法和安装芯片IP的方法。提供了可以安装芯片IP的硅布线基板。通过连接触发器在硅布线基板上形成用于边界扫描测试的电路。触发器连接到布线并被布置成测试布线中的连接。整个IP On Super Sub（IPOS）设备或每个芯片IP可以被布置成便于在芯片IP的内部电路上进行扫描测试，内置自检（BIST）等。

6. 发明授权

US07171600B2 Semiconductor wiring substrate, semiconductor device, method for testing semiconductor device, and method for mounting semiconductor device 有权
标题翻译：半导体配线基板，半导体装置，半导体装置的测试方法以及半导体装置的安装方法
公开(公告)号：US07171600B2
公开(公告)日：2007-01-30
申请号：US10828263
申请日：2004-04-21
申请人： Sadami Takeoka , Mitsuyasu Ohta , Osamu Ichikawa , Masayoshi Yoshimura
发明人： Sadami Takeoka , Mitsuyasu Ohta , Osamu Ichikawa , Masayoshi Yoshimura
IPC分类号： G01R31/28
CPC分类号： G01R31/28 , G01R31/318505 , G01R31/318538 , G01R31/318558 , G06F17/50 , G11C5/02 , G11C5/025 , G11C29/48 , G11C2029/3202 , H01L23/12
摘要： An apparatus for testing a semiconductor device by mounting a plurality of chip intellectual properties (IPs) on a common semiconductor wiring substrate, including a silicon wiring substrate on which the chip IPs are mounted. A circuit for a boundary scan test is formed on the silicon wiring substrate by connecting flip-flops to wiring, which are arranged to test connections in the wiring. An IP on Super-Sub (IPOS) device or each chip IP may be arranged to facilitate a scan test, a built-in self-test (BIST), etc., on the internal circuit of the chip IP.
摘要翻译：一种用于通过在公共半导体布线基板上安装多个芯片智能特性（IP）来测试半导体器件的装置，包括安装有芯片IP的硅布线基板。通过将触发器连接到布线来测试布线中的连接，在硅布线基板上形成用于边界扫描测试的电路。可以安排IP超级（IPOS）设备上的IP或每个芯片IP，以便在芯片IP的内部电路上进行扫描测试，内置自检（BIST）等。

7. 发明授权

US06271677B1 Semiconductor integrated circuit and method for testing the semiconductor integrated circuit 失效
标题翻译：半导体集成电路和半导体集成电路测试方法
公开(公告)号：US06271677B1
公开(公告)日：2001-08-07
申请号：US09560126
申请日：2000-04-28
申请人： Mitsuyasu Ohta , Toshinori Hosokawa , Sadami Takeoka , Osamu Ichikawa
发明人： Mitsuyasu Ohta , Toshinori Hosokawa , Sadami Takeoka , Osamu Ichikawa
IPC分类号： H03K1900
CPC分类号： G01R31/318328
摘要： A semiconductor IC includes a test circuit comprising a logic circuit, a test timing generator, a first register serving as a test signal generation point, and second and third registers serving as test signal observation points. In this test circuit, a target signal transmission path to be tested is selected from a plurality of signal transmission paths in the logic circuit, and the test timing generator outputs a test clock having a cycle according to a delay time of the selected signal transmission path on design to the first to third registers, whereby the first register generates a test signal and the second and third registers observe the test signal. Therefore, the signal transmission paths connecting the test signal generation point and the test signal observation point are tested with high efficiency, whereby more signal transmission paths are tested for delay faults with less number of times the test is executed.
摘要翻译：半导体IC包括测试电路，其包括逻辑电路，测试定时发生器，用作测试信号生成点的第一寄存器，以及用作测试信号观测点的第二和第三寄存器。在该测试电路中，从逻辑电路中的多个信号传输路径选择要测试的目标信号传输路径，并且测试定时发生器输出具有根据所选信号传输路径的延迟时间的周期的测试时钟设计到第一至第三寄存器，由此第一寄存器产生测试信号，第二和第三寄存器观察测试信号。因此，连接测试信号生成点和测试信号观察点的信号传输路径被高效率地测试，由此对于执行测试次数较少的延迟故障来测试更多的信号传输路径。

8. 发明授权

US06615389B1 Database for designing integrated circuit device, and method for designing integrated circuit device 有权
标题翻译：集成电路器件设计数据库，集成电路器件设计方法
公开(公告)号：US06615389B1
公开(公告)日：2003-09-02
申请号：US09561342
申请日：2000-04-28
申请人： Mitsuyasu Ohta , Sadami Takeoka , Osamu Ichikawa
发明人： Mitsuyasu Ohta , Sadami Takeoka , Osamu Ichikawa
IPC分类号： G06F1750
CPC分类号： G06F17/5045
摘要： In response to a design request, fault detection strategy optimizing means selects RT-VCs and a fault detection method from a VCDB. The design request includes: requirements for a system LSI (e.g., area, number of pins, test time and information about the weights of prioritized constraints); and VC information. The fault detection strategy optimizing means performs computations for optimization in view of various parameters, thereby specifying a best fault detection strategy and a method of constructing a single-chip fault detection controller. On the VCDB, multiple VCs associated with the same function and mutually different test techniques are stored. By weighting the parameters affecting a test cost in accordance with a user defined priority order, a test technique of the type minimizing the total test cost can be selected from the VCDB.
摘要翻译：响应于设计请求，故障检测策略优化装置从VCDB中选择RT-VC和故障检测方法。设计请求包括：对系统LSI的要求（例如，区域，引脚数，测试时间和关于优先约束的权重的信息）; 和VC信息。故障检测策略优化装置根据各种参数进行优化计算，从而指定最佳故障检测策略和构建单片故障检测控制器的方法。在VCDB上，存储与相同功能和相互不同的测试技术相关联的多个VC。通过根据用户定义的优先顺序加权影响测试成本的参数，可以从VCDB中选择最小化总测试成本的类型的测试技术。

9. 发明申请

US20070011543A1 Test pattern generation method 审中-公开
标题翻译：测试模式生成方法
公开(公告)号：US20070011543A1
公开(公告)日：2007-01-11
申请号：US11447302
申请日：2006-06-06
申请人： Shinichi Yoshimura , Tomokazu Miura , Mitsuyasu Ohta , Osamu Ichikawa
发明人： Shinichi Yoshimura , Tomokazu Miura , Mitsuyasu Ohta , Osamu Ichikawa
IPC分类号： G01R31/28 , G06F11/00
CPC分类号： G01R31/318328
摘要： A high-quality test pattern for testing a delay fault is generated at a high speed. In order that a second test pattern provided at a test cycle that follows a test cycle should be generated, a fault value set up in a circuit is propagated to an observation point. At a branch point in the circuit, a signal line for propagating the fault value is selected from the branches. Then, activation and justification are performed so that a value of the signal line in the circuit is acquired. When the activation and the justification have been successful, the second test pattern is updated on the basis of the acquired value of the signal line. In the selection of the signal line, one of branches is selected on the basis of the length of the longest path from each branch to the observation point.
摘要翻译：产生用于测试延迟故障的高质量测试模式。为了产生在测试周期之后的测试周期提供的第二测试图案，将在电路中建立的故障值传播到观测点。在电路中的分支点处，从分支中选择用于传播故障值的信号线。然后，执行激活和对齐，以便获取电路中的信号线的值。当激活和对齐成功时，基于获取的信号线的值来更新第二测试模式。在信号线的选择中，基于从每个分支到观察点的最长路径的长度来选择分支之一。

10. 发明授权

US09022588B2 Mirror surface angle adjusting device 有权
标题翻译：镜面角度调节装置
公开(公告)号：US09022588B2
公开(公告)日：2015-05-05
申请号：US13503895
申请日：2010-11-02
申请人： Masaru Chino , Tetsuya Murakoshi , Hiroshi Morishita , Osamu Ichikawa
发明人： Masaru Chino , Tetsuya Murakoshi , Hiroshi Morishita , Osamu Ichikawa
IPC分类号： G02B7/182 , B60R1/072 , G02B7/198
CPC分类号： B60R1/072 , G02B7/198
摘要： A mirror surface angle adjusting device includes: a pivot plate (10) which supports a mirror (6) and is attached to a holder (9) pivotably three-dimensionally on a pivot shaft (76); a bracket (8) disposed on a vehicle body; a mirror tilting drive section (11) contained between the bracket (8) and the holder (9) attached to the bracket (8); an operation shaft (44A, 44B) of the mirror tilting drive section (11), the operation shaft penetrating through the holder (9) and being connected to the pivot plate (10); a detection rod (101A, 101B) which moves following the pivot plate (10); an angle detection section (100) which detects a tilt angle of the pivot plate (10); a pivot depressed portion (80) into which the pivot shaft can be press-fitted; and a gear positioning rib (69) provided on an inner wall of the holder (9) to position the mirror tilting drive section (42).
摘要翻译：镜面角度调节装置包括：支撑反射镜（6）并且在枢轴（76）上三维可枢转地固定在支架（9）上的枢轴板（10）; 设置在车身上的支架（8）; 容纳在支架（8）和安装在支架（8）上的支架（9）之间的镜子倾斜驱动部分（11）; 镜倾斜驱动部分（11）的操作轴（44A，44B），操作轴穿过保持器（9）并连接到枢转板（10）; 检测杆（101A，101B），其沿着所述枢转板（10）移动; 角度检测部（100），其检测所述枢转板（10）的倾斜角度; 枢轴凹部（80），枢轴可压入其中; 以及设置在所述保持器（9）的内壁上以定位所述镜子倾斜驱动部分（42）的齿轮定位肋（69）。

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