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    • 1. 发明授权
    • Microprocessor runaway monitoring control circuit
    • 微处理器失控监控控制电路
    • US06883123B2
    • 2005-04-19
    • US10127484
    • 2002-04-23
    • Kohji HashimotoKatsuya NakamotoMasahide FujitaHiroyuki Mitsueda
    • Kohji HashimotoKatsuya NakamotoMasahide FujitaHiroyuki Mitsueda
    • F02D45/00G06F11/00G06F11/18G06F11/22G06F11/30H02H3/05
    • G06F11/079G06F11/0721G06F11/0757
    • A microprocessor runaway monitoring control circuit with which self-diagnosis of a watchdog timer WDT can be carried out safely and cheaply even during operation of the microprocessor (CPU). A microprocessor 101 supplies first and second watchdog clearing signals WD1 and WD2 to first and second watchdog timers WDT1 and WDT2, and when the both of the watchdog clearing signals WD1 and WD2 stop, the microprocessor 101 is reset by way of a logical connector circuit 122. The microprocessor 101 has failure diagnosing means 103 which intentionally stops the first watchdog clearing signal WD1 and diagnoses the response of the first watchdog timer WDT1 on the basis of a monitor signal MN1 and stops the second watchdog clearing signal WD2 and diagnoses the response of the second watchdog timer WDT2 on the basis of a monitor signal MN2, whereby diagnosis of the watchdog timers WDT1, WDT2 is carried out without the microprocessor 101 being stopped.
    • 即使在微处理器(CPU)的操作期间,微处理器失控的监视控制电路也可以安全且便宜地执行看门狗定时器WDT的自诊断。 微处理器101将第一和第二看门狗清除信号WD1和WD2提供给第一和第二看门狗定时器WDT 1和WDT 2,并且当看门狗清除信号WD1和WD2都停止时,微处理器101被复位 逻辑连接器电路122。 微处理器101具有故障诊断装置103,其有意地停止第一看门狗清除信号WD1,并且基于监视信号MN 1诊断第一看门狗定时器WDT 1的响应,并停止第二看门狗清除信号WD2,并诊断第 基于监视信号MN 2的第二看门狗定时器WDT 2的响应,从而执行看门狗定时器WDT 1,WDT 2的诊断,而微处理器101不被停止。
    • 6. 发明授权
    • Eeprom write device
    • Eeprom写设备
    • US06256226B1
    • 2001-07-03
    • US09561955
    • 2000-05-01
    • Masahide Fujita
    • Masahide Fujita
    • G11C1604
    • G11C16/102
    • An EEPROM write device includes an ECU 2A having a microcomputer 3A including a CPU 30A, an EEPROM 31 and a boot program 32A, and an external write device 1A which communicates serial signals SE and SR with the CPU, in which the ECU includes write control means associated with the CPU, the write control means generates a write enable signal to the CPU in response to a receive start of the serial signal from the external write device, and the CPU switches from a normal operation mode to a write mode to the EEPROM in response to the write enable signal, to thereby rewrite the contents of the EEPROM.
    • EEPROM写入装置包括具有包括CPU 30A,EEPROM 31和引导程序32A的微型计算机3A的ECU 2A以及与串行信号SE和SR通信的外部写入装置1A,其中ECU包括写入控制 与CPU相关联的装置,写入控制装置响应于来自外部写入装置的串行信号的接收开始而向CPU发出写入使能信号,并且CPU从正常操作模式切换到写入模式到EEPROM 响应于写使能信号,从而重写EEPROM的内容。
    • 8. 发明授权
    • Vehicle controlling apparatus
    • 车辆控制装置
    • US06411872B1
    • 2002-06-25
    • US09919852
    • 2001-08-02
    • Masahide FujitaKohji HashimotoKatsuya Nakamoto
    • Masahide FujitaKohji HashimotoKatsuya Nakamoto
    • G06F700
    • G06F11/0757
    • To secure normal operation and then restart a microprocessor (CPU) when a CPU built into an on-vehicle electronic apparatus runs away. A number of on-vehicle loads driven from a CPU, a watchdog timer for monitoring the CPU to reset and restart it on occurrence of an abnormality, and a memory element for storing generation of the reset output are provided, and load driving elements or a load relay is rendered inoperative by output of the memory element. The memory element is reset by cutting off or reclosing the power switch, and an on-vehicle electronic apparatus returns to a normal state.
    • 当内置于车载电子设备中的CPU耗尽时,确保正常操作,然后重新启动微处理器(CPU)。 提供了从CPU驱动的多个车载负载,用于在发生异常时监视CPU重新启动的看门狗定时器和用于存储复位输出的生成的存储元件,并且负载驱动元件或 通过存储器元件的输出使负载继电器不起作用。 通过切断或重新闭合电源开关来复位存储器元件,并且车载电子设备恢复正常状态。