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1. 发明申请

US20050102598A1 Error-correcting multi-stage code generator and decoder for communication systems having single transmitters or multiple transmitters 有权
标题翻译：用于具有单个发射机或多个发射机的通信系统的纠错多级码发生器和解码器
公开(公告)号：US20050102598A1
公开(公告)日：2005-05-12
申请号：US10960790
申请日：2004-10-06
申请人： M. Shokrollahi
发明人： M. Shokrollahi
IPC分类号： G06F11/00 , G06F11/30 , G08C25/00 , H03D1/00 , H03M20060101 , H03M13/00 , H03M13/37 , H04L1/00 , H04L27/06
CPC分类号： H03M13/3761
摘要： A communications system includes an encoder that produces a plurality of redundant symbols. For a given key, an output symbol is generated from a combined set of symbols including the input symbols and the redundant symbols. The output symbols are generally independent of each other, and an effectively unbounded number of output symbols (subject to the resolution of the key used) can be generated, if needed. The output symbols are information additive such that a received output symbol is likely to provide additional information for decoding even when many symbols are already received. The output symbols are such that a collection of received output symbols can provide probabilistic information to support error correction. A decoder calculates check symbols from the output symbols received, wherein each check symbol is associated with one or more input symbols and redundant symbols For each received output symbol, the decoder updates a running total of estimated information content and, in one or more rounds, generates a probability distribution for each input symbol over all or some of the possible values of input symbols. This process may be repeated until, for all of the input symbols, one of the many possible values is much more probable than others, or the process may be repeated a predetermined number of rounds, or other criteria is met. The updating can take into account already decoded symbols, additional output symbols and the check symbols.
摘要翻译：通信系统包括产生多个冗余符号的编码器。对于给定的密钥，从包括输入符号和冗余符号的组合组合生成输出符号。输出符号通常彼此独立，并且如果需要，可以产生有效无限数量的输出符号（取决于所使用的密钥的分辨率）。输出符号是信息加法，使得即使已经接收到许多符号，所接收的输出符号也可能提供用于解码的附加信息。输出符号使得所接收的输出符号的集合可以提供概率信息以支持纠错。解码器从接收到的输出符号计算检查符号，其中每个检查符号与一个或多个输入符号和冗余符号相关联对于每个接收的输出符号，解码器更新估计信息内容的运行总计，并且在一个或多个循环中，在输入符号的全部或部分可能的值上生成每个输入符号的概率分布。可以重复该过程，直到对于所有输入符号来说，许多可能值中的一个值比其他值更可能更多，或者可以重复该过程预定数量的循环，或满足其他标准。更新可以考虑已经解码的符号，附加的输出符号和检查符号。

2. 发明申请

US20050031039A1 Adaptive joint source channel coding 失效
公开(公告)号：US20050031039A1
公开(公告)日：2005-02-10
申请号：US10877589
申请日：2004-06-25
申请人： Jim Chou , Ali Tabatabai
发明人： Jim Chou , Ali Tabatabai
IPC分类号： H03M20060101 , H04B1/66 , H04L1/00 , H04N7/12
CPC分类号： H04L1/0041 , H04N19/30 , H04N19/577 , H04N19/61 , H04N19/619 , H04N19/63 , H04N19/94
摘要： Adaptive joint source channel coding associates multiple predictors with a reference data unit, such as a macroblock or frame of video data. An encoder determines a sub-codebook in which each of the selected multiple predictors decodes to the reference data unit. An identifier for the sub-codebook is transmitted through a channel to a decoder for subsequent decoding of the reference data unit. The reference data unit itself does not need to be sent. The multiple predictors are contained within a decoding region and the identifier for the sub-codebook specifies the decoding region. The decoder uses the identified sub-codebook and one of the predictors to decode the reference data unit. If none of the original predictors are correctly received, different types of error handling are employed based on the type of channel.

3. 发明授权

US5917837A Method and apparatus for performing decoding of codes with the use of side information associated with the encoded data 失效
标题翻译：使用与编码数据相关联的侧信息来执行代码解码的方法和装置
公开(公告)号：US5917837A
公开(公告)日：1999-06-29
申请号：US712065
申请日：1996-09-11
申请人： Jeremy M. Stein
发明人： Jeremy M. Stein
IPC分类号： H03M13/09 , H03M20060101 , H03M13/00 , H03M13/41 , H04L20060101 , H04L1/00
CPC分类号： H03M13/3738 , H03M13/3776 , H04L1/0046 , H04L1/0061
摘要： The present invention is a novel and improved method and apparatus for decoding a frame of digital data which contains redundant information provided to validate the decoding operation. In the present invention, a frame of data contains information bits and cyclic redundancy check (CRC) bits. The received frame is decoded and a check is conducted to determine whether the CRC bits correspond correctly for the decoded information bits. If the decoded frame passes the CRC test process, the decoded fame is provided to the user. However, if the decoded frame does not pass the CRC test, then at least one additional decoding process is performed on the received frame. In the first exemplary embodiment of the present invention, if the CRC test is failed, a noise vector of a predetermined set of noise vectors is summed with the received frame and the resultant frame is decoded for a second time. In the second exemplary embodiment of the present invention, when the CRC test fails, a set of the received symbols are replaced with symbol erasure indications.
摘要翻译：本发明是一种用于解码数字数据帧的新颖且改进的方法和装置，其包含提供的用于验证解码操作的冗余信息。在本发明中，数据帧包含信息比特和循环冗余校验（CRC）比特。接收到的帧被解码，并进行检查以确定CRC比特是否对应于解码的信息比特正确对应。如果解码的帧通过CRC测试过程，则将解码的声望提供给用户。然而，如果解码帧不通过CRC测试，则对接收到的帧执行至少一个附加解码处理。在本发明的第一示例性实施例中，如果CRC测试失败，则将预定的一组噪声矢量的噪声向量与接收的帧相加，并且所得到的帧被解码第二次。在本发明的第二示例性实施例中，当CRC测试失败时，一组接收到的符号被替换为符号擦除指示。

4. 发明授权

US6154161A Integrated audio mixer 有权
标题翻译：集成音频混音器
公开(公告)号：US6154161A
公开(公告)日：2000-11-28
申请号：US168223
申请日：1998-10-07
申请人： Carlos Azeredo Leme , Christian Dupuy , Jose Epifanio da Franca
发明人： Carlos Azeredo Leme , Christian Dupuy , Jose Epifanio da Franca
IPC分类号： G11B31/00 , H03M20060101 , H03M3/00 , H03M3/02 , H04S20060101 , H04S1/00 , H04S3/00 , H04S7/00
CPC分类号： H04H60/04
摘要： An integrated, multi-input audio mixer receiving a plurality of analog input signals, internally digitizing the analog input signals, digitally processing and mixing the digitized input signals and producing both digital and analog representations of the mixed inputs. All analog inputs are applied to half of a full delta-sigma analog-to-digital converter. That is, each input is applied to a respective delta-sigma modulator, but all the delta-sigma modulators share a single sigma-decimation filter. The output of each delta/sigma modulator controls a respective multiplexer having a separate input channel for each quantization level of its respective delta/sigma modulator. The output of the multiplexers is selectively applied to a summing circuit. The output from the summing circuit is applied to a D/A converter to provide an analog output, and is also applied to the single sigma-decimation filter, which recovers the mixed data from the delta/sigma modulators.
摘要翻译：接收多个模拟输入信号的集成多输入音频混合器，对模拟输入信号进行内部数字化，数字处理和混合数字化的输入信号，并产生混合输入的数字和模拟表示。所有模拟输入都应用于全delta-sigma模数转换器的一半。也就是说，每个输入被施加到相应的Δ-Σ调制器，但是所有的Δ-Σ调制器共享单个Σ-Σ抽取滤波器。每个Δ/Σ调制器的输出控制对其各自的Δ/Σ调制器的每个量化级别具有单独的输入通道的相应多路复用器。多路复用器的输出被选择性地施加到求和电路。来自求和电路的输出被施加到D / A转换器以提供模拟输出，并且也被应用于从Σ/Σ调制器恢复混合数据的单个Σ-抽取滤波器。

5. 发明授权

US5579433A Digital coding of speech signals using analysis filtering and synthesis filtering 失效
标题翻译：使用分析滤波和合成滤波对语音信号进行数字编码
公开(公告)号：US5579433A
公开(公告)日：1996-11-26
申请号：US60427
申请日：1993-05-07
申请人： Kari J. Jarvinen
发明人： Kari J. Jarvinen
IPC分类号： G10L19/08 , H03M20060101 , G10L3/02 , G10L5/00 , G10L7/00 , G10L9/00
CPC分类号： G10L19/08
摘要： A digital speech encoder is constructed to include a short term analyzer for forming a set of prediction parameters a(i), corresponding to an input speech signal, and an encoder for producing an excitation signal. The encoder includes a plurality of serially coupled coding blocks, wherein each coding block includes an analysis filter, a sample selection block, and a synthesizer filter. The analysis filter outputs speech signal sample values to the sample selection block, which selects and outputs K.sub.i sample values representing a selected partial excitation signal. The synthesis filter synthesizes a speech signal corresponding to the selected partial excitation signal output by the selection block and outputs a partial excitation synthesis result to an output of the coding block. At the output of each coding block is a subtractor arranged for subtracting a partial excitation synthesis result that is output from the coding block from the speech signal to obtain a difference signal. The difference signal is coupled to the input of an analysis filter of a next serially coupled coding block. A quantizer is also provided for forming the excitation signal in accordance with all of the partial excitation signals generated by the coding blocks.
摘要翻译：数字语音编码器被构造成包括用于形成对应于输入语音信号的一组预测参数a（i）的短期分析器和用于产生激励信号的编码器。编码器包括多个串行编码块，其中每个编码块包括分析滤波器，采样选择块和合成器滤波器。分析滤波器将语音信号采样值输出到采样选择块，其选择并输出表示所选择的部分激励信号的Ki采样值。合成滤波器合成对应于由选择块输出的所选择的部分激励信号的语音信号，并将部分激励合成结果输出到编码块的输出。在每个编码块的输出端是减法器，被设置为从语音信号中减去从编码块输出的部分激励合成结果以获得差分信号。差分信号耦合到下一个串行编码块的分析滤波器的输入端。还提供量化器，用于根据由编码块产生的所有部分激励信号形成激励信号。

6. 发明授权

US5054036A Digital signal coding 失效
标题翻译：数字信号编码
公开(公告)号：US5054036A
公开(公告)日：1991-10-01
申请号：US368357
申请日：1989-05-31
申请人： John D. Brownlie , Barry G. Lloyd
发明人： John D. Brownlie , Barry G. Lloyd
IPC分类号： H04L27/36 , H03M20060101 , H03M13/25 , H04L20060101 , H04L27/00 , H04L27/34
CPC分类号： H04L27/3438 , H03M13/25
摘要： A trellis coder has a convolutional encoder which has n states and can progress from a current state to a follower state depending on an input. The state progressions are selected such that they can be represented by a diagram having 90.degree. rotational symmetry. A state transition produces via mapping means by quadrature modulation one of four output carrier signal phases, such that any three state sequence gives rise to a pair of signals having the same phase difference as the pair generated by a corresponding sequence having a position in the diagram rotated by 90.degree. from that of the sequence in question. Input means enable a single bit data input to control the coder state progression so that a given differential output phase always corresponds to the same input bit value.
摘要翻译： PCT No.PCT / GB87 / 00861 Sec。 371日期：1989年5月31日 102（e）日期1989年5月31日PCT提交1987年12月1日PCT公布。第WO88 / 04500号公报日期1988年6月16日。格状编码器具有卷积编码器，其具有n个状态，并且可以根据输入从当前状态进入到随动状态。选择状态进行，使得它们可以由具有90°旋转对称性的图表示。状态转换通过映射装置产生四个输出载波信号相位之一的正交调制，使得任何三个状态序列产生与由具有图中位置的相应序列产生的对相同的相位差的一对信号与所讨论的序列相比旋转90°。输入装置使单个位数据输入能够控制编码器状态进展，使得给定的差分输出相位总是对应于相同的输入位值。

7. 发明申请

US20050116849A1 Feedback steering delta-sigma modulators and systems using the same 有权
公开(公告)号：US20050116849A1
公开(公告)日：2005-06-02
申请号：US10379742
申请日：2003-03-05
申请人： John Melanson , Xiaofan Fei , Johann Gaboriau
发明人： John Melanson , Xiaofan Fei , Johann Gaboriau
IPC分类号： H03M20060101 , H03M3/00 , H03M7/32 , H03M7/34 , H03M7/36 , H03M7/38 , H03M1/56
CPC分类号： H03M7/3006 , H03M7/3011 , H03M7/3026 , H03M7/3033 , H03M7/3037
摘要： A digital to analog converter including an input for receiving an input signal, a ramp generator, and a delta-sigma modulator responsive to the input signal and an output of the ramp generator. An order of a noise shaping transfer function of the delta-sigma modulator is response to a level of the output of the ramp generator.

8. 发明申请

US20050078021A1 Dual phase pulse modulation encoder circuit 有权
标题翻译：双相脉冲调制编码电路
公开(公告)号：US20050078021A1
公开(公告)日：2005-04-14
申请号：US10836703
申请日：2004-04-29
申请人： Daniel Cohen , John Fagan , Mark Bossard
发明人： Daniel Cohen , John Fagan , Mark Bossard
IPC分类号： H03M20060101 , H03M5/06 , H03M5/08 , H04L27/04 , H04L27/12 , H04L27/20
CPC分类号： H03M5/08
摘要： An dual phase pulse modulation (DPPM) encoder circuit converts data into a series of high and low signal pulses, each of whose time durations or pulse widths represents a group of M data bits, with the alternating high and low pulses representing successive groups. The encoder circuit may include a set of parallel-in, serial-out shift registers that subdivide received data words into the M-bit groups, a state machine that specified the pulse durations for each received group, e.g., by incrementing a state that indicates selected signal pulse transition times, a system clock delay chain with multiple taps, a multiplexer controlled by the state machine for successively selecting different taps, and a toggle flip-flop that is clocked by the multiplexer output.
摘要翻译：双相脉冲调制（DPPM）编码器电路将数据转换为一系列高和低信号脉冲，其中每个时间持续时间或脉冲宽度表示一组M个数据位，交替的高和低脉冲表示连续的组。编码器电路可以包括一组并行的串行输出移位寄存器，其将接收到的数据字细分到M位组中，状态机指定每个接收到的组的脉冲持续时间，例如通过递增指示选择的信号脉冲转换时间，具有多个抽头的系统时钟延迟链，由状态机控制的用于连续选择不同抽头的多路复用器，以及由多路复用器输出计时的开关触发器。

9. 发明申请

US20050062631A1 Low distortion digital to analog converter and digital signal synthesizer systems 失效
标题翻译：低失真数模转换器和数字信号合成器系统
公开(公告)号：US20050062631A1
公开(公告)日：2005-03-24
申请号：US10898006
申请日：2004-07-23
申请人： Robert Washburn , Robert McClanahan
发明人： Robert Washburn , Robert McClanahan
IPC分类号： H03M20060101 , H03M1/66
CPC分类号： H03M1/661
摘要： The present invention is a digital to analog converter circuit that provides significantly lower distortion than achieved by digital to analog converter circuits having comparable speed and resolution utilizing the present art. The present invention provides linear or higher order transitions between clock transition time points rather than step transitions used in the present art. Distortion reduction can exceed 30 dB in the embodiment with linear sample-to-sample transitions and greater in alternate embodiments with non-linear transitions. In other embodiments, the present invention can provide low distortion at resolutions from 16 to 24 bits or more at sample rates typical of high-speed 8-bit devices of the present art.
摘要翻译：本发明是一种数模转换器电路，其提供比通过本技术具有相当的速度和分辨率的数模转换器电路实现的低得多的失真。本发明提供在本技术中使用的时钟转换时间点之间的线性或更高阶跃迁，而不是阶跃转换。在具有线性样品到样品转变的实施方案中，失真降低可以超过30dB，并且在具有非线性跃迁的替代实施方案中变差更大。在其他实施例中，本发明可以在本技术的高速8位器件的典型的采样率下以16至24位或更高的分辨率提供低失真。

10. 发明申请

US20050010847A1 Systems and processes for fast encoding of hamming codes 有权
标题翻译：汉明码快速编码的系统和流程
公开(公告)号：US20050010847A1
公开(公告)日：2005-01-13
申请号：US10769732
申请日：2004-01-29
申请人： M. Shokrollahi , Soren Lassen
发明人： M. Shokrollahi , Soren Lassen
IPC分类号： H03M20060101 , H03M13/00 , H03M13/19 , H03M13/37
CPC分类号： H03M13/6502 , H03M13/1102 , H03M13/19 , H03M13/3761
摘要： Decoding that uses an extended Hamming code in one of the primary stages of static encoding uses a calculation of the r+1 Hamming redundant symbols for k input symbols from which Hamming redundant symbols are calculated, where r satisfies 2r−1−r≦k
摘要翻译：在静态编码的一个主要阶段中使用扩展汉明码的解码使用计算汉明冗余符号的k个输入符号的r + 1汉明冗余符号的计算，其中r满足2 -r <= K <2 -r-1。这种有效的方法要求输入符号的2k + 3r + 1个异或，以计算r + 1汉明冗余符号。

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