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1. 发明授权

US06620657B2 Method of forming a planar polymer transistor using substrate bonding techniques 失效
标题翻译：使用基板接合技术形成平面聚合物晶体管的方法
公开(公告)号：US06620657B2
公开(公告)日：2003-09-16
申请号：US10052151
申请日：2002-01-15
申请人： Tricia L. Breen , Lawrence A. Clevenger , Louis L. Hsu , Li-Kong Wang , Kwong Hon Wong
发明人： Tricia L. Breen , Lawrence A. Clevenger , Louis L. Hsu , Li-Kong Wang , Kwong Hon Wong
IPC分类号： H01L2100
CPC分类号： H01L51/0001 , H01L51/0024 , H01L51/0516 , H01L51/0541 , H01L51/0545
摘要： A structure and method of forming a fully planarized polymer thin-film transistor by using a first planar carrier to process a first portion of the device including gate, source, drain and body elements. Preferably, the thin-film transistors made with all organic materials. The gate dielectric can be a high-k polymer to boost the device performance. Then, the partially-finished device structures are flipped upside-down and transferred to a second planar carrier. A layer of wax or photo-sensitive organic material is then applied, and can be used as the temporary glue. The device, including its body area, is then defined by an etching process. Contacts to the devices are formed by conductive material deposition and chemical-mechanical polish.
摘要翻译：通过使用第一平面载体来形成包括栅极，源极，漏极和主体元件的器件的第一部分来形成完全平坦化的聚合物薄膜晶体管的结构和方法。优选地，由所有有机材料制成的薄膜晶体管。栅极电介质可以是高k聚合物，以提高器件性能。然后，部分完成的装置结构被颠倒翻转并转移到第二平面载体。然后施加一层蜡或光敏有机材料，并且可以用作临时胶。然后通过蚀刻工艺限定该装置，包括其身体区域。与器件的接触通过导电材料沉积和化学机械抛光形成。

2. 发明授权

US06911354B2 Polymer thin-film transistor with contact etch stops 失效
标题翻译：具有接触蚀刻的聚合物薄膜晶体管停止
公开(公告)号：US06911354B2
公开(公告)日：2005-06-28
申请号：US10681464
申请日：2003-10-08
申请人： Tricia L. Breen , Lawrence A. Clevenger , Louis L. Hsu , Li-Kong Wang , Kwong Hon Wong
发明人： Tricia L. Breen , Lawrence A. Clevenger , Louis L. Hsu , Li-Kong Wang , Kwong Hon Wong
IPC分类号： H01L21/00 , H01L29/786 , H01L51/40
CPC分类号： H01L51/057 , H01L51/0021
摘要： A method and structure of forming a vertical polymer transistor structure is disclosed having a first conductive layer, filler structures co-planar with the first conductive layer, a semiconductor body layer above the first conductive layer, a second conductive layer above the semiconductor body layer, and an etch stop strip positioned between a portion of the first conductive layer and the semiconductor body layer.
摘要翻译：公开了形成垂直聚合物晶体管结构的方法和结构，其具有第一导电层，与第一导电层共平面的填充结构，在第一导电层上方的半导体本体层，半导体本体层上方的第二导电层，以及位于第一导电层的一部分和半导体本体层之间的蚀刻停止带。

3. 发明授权

US06864504B2 Planar polymer transistor 失效
标题翻译：平面聚合物晶体管
公开(公告)号：US06864504B2
公开(公告)日：2005-03-08
申请号：US10453381
申请日：2003-06-03
申请人： Tricia L. Breen , Lawrence A. Clevenger , Louis L. Hsu , Li-Kong Wang , Kwong Hon Wong
发明人： Tricia L. Breen , Lawrence A. Clevenger , Louis L. Hsu , Li-Kong Wang , Kwong Hon Wong
IPC分类号： H01L51/05 , H01L21/00 , H01L21/336 , H01L29/786 , H01L35/24 , H01L51/00 , H01L51/40
CPC分类号： H01L51/0001 , H01L51/0024 , H01L51/0516 , H01L51/0541 , H01L51/0545
摘要： A structure and method of forming a fully planarized polymer thin-film transistor by using a first planar carrier to process a first portion of the device including gate, source, drain and body elements. Preferably, the thin-film transistor is made with all organic materials. The gate dielectric can be a high-k polymer to boost the device performance. Then, the partially-finished device structures are flipped upside-down and transferred to a second planar carrier. A layer of wax or photo-sensitive organic material is then applied, and can be used as the temporary glue. The device, including its body area, is then defined by an etching process. Contacts to the devices are formed by conductive material deposition and chemical-mechanical polish.
摘要翻译：通过使用第一平面载体来形成包括栅极，源极，漏极和主体元件的器件的第一部分来形成完全平坦化的聚合物薄膜晶体管的结构和方法。优选地，薄膜晶体管由所有有机材料制成。栅极电介质可以是高k聚合物，以提高器件性能。然后，部分完成的装置结构被颠倒翻转并转移到第二平面载体。然后施加一层蜡或光敏有机材料，并且可以用作临时胶。然后通过蚀刻工艺限定该装置，包括其身体区域。与器件的接触通过导电材料沉积和化学机械抛光形成。

4. 发明授权

US06664576B1 Polymer thin-film transistor with contact etch stops 失效
标题翻译：具有接触蚀刻的聚合物薄膜晶体管停止
公开(公告)号：US06664576B1
公开(公告)日：2003-12-16
申请号：US10254739
申请日：2002-09-25
申请人： Tricia L. Breen , Lawrence A. Clevenger , Louis L. Hsu , Li-Kong Wang , Kwong Hon Wong
发明人： Tricia L. Breen , Lawrence A. Clevenger , Louis L. Hsu , Li-Kong Wang , Kwong Hon Wong
IPC分类号： H01L27148
CPC分类号： H01L51/057 , H01L51/0021
摘要： A method and structure of forming a vertical polymer transistor structure is disclosed having a first conductive layer, filler structures co-planar with the first conductive layer, a semiconductor body layer above the first conductive layer, a second conductive layer above the semiconductor body layer, and an etch stop strip positioned between a portion of the first conductive layer and the semiconductor body layer.
摘要翻译：公开了形成垂直聚合物晶体管结构的方法和结构，其具有第一导电层，与第一导电层共平面的填充结构，在第一导电层上方的半导体本体层，半导体本体层上方的第二导电层，以及位于第一导电层的一部分和半导体本体层之间的蚀刻停止带。

5. 发明授权

US07041525B2 Three-dimensional island pixel photo-sensor 有权
公开(公告)号：US07041525B2
公开(公告)日：2006-05-09
申请号：US10751205
申请日：2004-01-02
申请人： Lawrence A. Clevenger , Louis L. Hsu , Carl J. Radens , Li-Kong Wang , Kwong Hon Wong
发明人： Lawrence A. Clevenger , Louis L. Hsu , Carl J. Radens , Li-Kong Wang , Kwong Hon Wong
IPC分类号： H01L21/66 , H01L21/00
CPC分类号： H01L27/14634 , H01L27/1463 , H01L27/14643
摘要： A method and structure for a photodiode array comprising a plurality of photodiode cores, light sensing sidewalls along an exterior of the cores, logic circuitry above the cores, trenches separating the cores, and a transparent material in the trenches is disclosed. With the invention, the sidewalls are perpendicular to the surface of the photodiode that receives incident light. The light sensing sidewalls comprise a junction region that causes electron transfer when struck with light. The sidewalls comprise four vertical sidewalls around each island core. The logic circuitry blocks light from the core so light is primarily only sensed by the sidewalls.

6. 发明授权

US06452110B1 Patterning microelectronic features without using photoresists 失效
标题翻译：图案化微电子特征，而不使用光致抗蚀剂
公开(公告)号：US06452110B1
公开(公告)日：2002-09-17
申请号：US09897889
申请日：2001-07-05
申请人： Lawrence A. Clevenger , Louis L. Hsu , Carl J. Radens , Li-Kong Wang , Keith Kwong Hon Wong
发明人： Lawrence A. Clevenger , Louis L. Hsu , Carl J. Radens , Li-Kong Wang , Keith Kwong Hon Wong
IPC分类号： H05K109
CPC分类号： H05K3/02 , H01L21/288 , H01L21/32134 , H01L21/76885 , Y10T29/49155 , Y10T29/49156
摘要： A method and structure for producing metallic polymer conductor lines comprising of an alternative methodology to a traditional damascene approach, called a cloisonne or inverse damascene approach. The cloisonne approach comprises the steps of coating a photosensitive polymer such as pyrrole or aniline with a silver salt on a semiconductor substrate. Using standard photolithography and resist developing techniques, the conducting polymer is exposed to a wet chemical developer, removing a portion of the exposed conducting polymer region, leaving only conducting polymer lines on top of the substrate. Next, an insulating dielectric layer is deposited over the entire structure and a chemical mechanical polish planarization of the insulator is performed creating the conducting polymer lines. Included in another aspect of the invention is a method and structure for a self-planarizing interconnect material comprising a conductive polymer thereby reducing the number of processing steps relative to the prior art.
摘要翻译：一种用于生产金属聚合物导体线的方法和结构，其包括传统大马士革方法的替代方法，称为景泰蓝或逆大马士革方法。景泰蓝方法包括在半导体衬底上用银盐将光敏聚合物如吡咯或苯胺涂覆的步骤。使用标准光刻和抗蚀显影技术，将导电聚合物暴露于湿化学显影剂，除去暴露的导电聚合物区域的一部分，仅在基底顶部留下导电聚合物线。接下来，在整个结构上沉积绝缘电介质层，并进行绝缘体的化学机械抛光平面化，产生导电聚合物线。包括在本发明的另一方面中的是一种用于自平坦化互连材料的方法和结构，其包括导电聚合物，从而减少相对于现有技术的加工步骤的数量。

7. 发明授权

US07112502B2 Method to fabricate passive components using conductive polymer 有权
公开(公告)号：US07112502B2
公开(公告)日：2006-09-26
申请号：US10828374
申请日：2004-04-20
申请人： Lawrence A. Clevenger , Louis L. Hsu , Carl J. Radens , Li-Kong Wang , Kwong Hon Wong
发明人： Lawrence A. Clevenger , Louis L. Hsu , Carl J. Radens , Li-Kong Wang , Kwong Hon Wong
IPC分类号： H01L21/20
CPC分类号： H01C7/005 , H01C7/006 , H01C17/075 , H01G4/18 , H01G4/33 , H01L23/5223 , H01L23/5227 , H01L23/5228 , H01L23/5328 , H01L27/0688 , H01L2924/0002 , H01L2924/00
摘要： A method and structure for an integrated circuit chip has a logic core which includes a plurality of insulating and conducting levels, an exterior conductor level and passive devices having a conductive polymer directly connected to the exterior conductor level. The passive devices contain RF devices which also includes resistor, capacitor, and/or inductor. The resistors can be serpentine resistors and the capacitors can be interdigitated capacitors.

8. 发明授权

US06958522B2 Method to fabricate passive components using conductive polymer 有权
标题翻译：使用导电聚合物制造无源元件的方法
公开(公告)号：US06958522B2
公开(公告)日：2005-10-25
申请号：US09897891
申请日：2001-07-05
申请人： Lawrence A. Clevenger , Louis L. Hsu , Carl J. Radens , Li-Kong Wang , Kwong Hon Wong
发明人： Lawrence A. Clevenger , Louis L. Hsu , Carl J. Radens , Li-Kong Wang , Kwong Hon Wong
IPC分类号： H01L27/06 , H01L29/00 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01C7/005 , H01C7/006 , H01C17/075 , H01G4/18 , H01G4/33 , H01L23/5223 , H01L23/5227 , H01L23/5228 , H01L23/5328 , H01L27/0688 , H01L2924/0002 , H01L2924/00
摘要： A method and structure for an integrated circuit chip has a logic core which includes a plurality of insulating and conducting levels, an exterior conductor level and passive devices having a conductive polymer directly connected to the exterior conductor level. The passive devices contain RF devices which also includes resistor, capacitor, and/or inductor. The resistors can be serpentine resistors and the capacitors can be interdigitated capacitors.
摘要翻译：集成电路芯片的方法和结构具有包括多个绝缘和导电水平的逻辑芯，外部导体水平和具有直接连接到外部导体水平的导电聚合物的无源器件。无源器件包含还包括电阻器，电容器和/或电感器的RF器件。电阻器可以是蛇形电阻器，电容器可以是交错电容器。

9. 发明授权

US06720595B2 Three-dimensional island pixel photo-sensor 有权
标题翻译：三维岛像素光电传感器
公开(公告)号：US06720595B2
公开(公告)日：2004-04-13
申请号：US09922077
申请日：2001-08-06
申请人： Lawrence A. Clevenger , Louis L. Hsu , Carl J. Radens , Li-Kong Wang , Kwong Hon Wong
发明人： Lawrence A. Clevenger , Louis L. Hsu , Carl J. Radens , Li-Kong Wang , Kwong Hon Wong
IPC分类号： H01L31062
CPC分类号： H01L27/14634 , H01L27/1463 , H01L27/14643
摘要： A method and structure for a photodiode array comprising a plurality of photodiode cores, light sensing sidewalls along an exterior of the cores, logic circuitry above the cores, trenches separating the cores, and a transparent material in the trenches is disclosed. With the invention, the sidewalls are perpendicular to the surface of the photodiode that receives incident light. The light sensing sidewalls comprise a junction region that causes electron transfer when struck with light. The sidewalls comprise four vertical sidewalls around each island core. The logic circuitry blocks light from the core so light is primarily only sensed by the sidewalls.
摘要翻译：公开了一种用于光电二极管阵列的方法和结构，该阵列包括多个光电二极管芯，沿芯的外部的感光侧壁，芯之上的逻辑电路，分离芯的沟槽和沟槽中的透明材料。利用本发明，侧壁垂直于接收入射光的光电二极管的表面。感光侧壁包括当用光照射时引起电子转移的结区域。侧壁包围围绕每个岛芯的四个垂直侧壁。逻辑电路阻挡来自芯的光，因此光仅主要由侧壁感测。

10. 发明申请

US20080171418A1 Method to Fabricate Passive Components Using Conductive Polymer 审中-公开
标题翻译：使用导电聚合物制造被动元件的方法
公开(公告)号：US20080171418A1
公开(公告)日：2008-07-17
申请号：US12054545
申请日：2008-03-25
申请人： Lawrence A. Clevenger , Louis L. Hsu , Cart J. Radens , Li-Kong Wang , Kwong Hon Wong
发明人： Lawrence A. Clevenger , Louis L. Hsu , Cart J. Radens , Li-Kong Wang , Kwong Hon Wong
IPC分类号： H01L21/02
CPC分类号： H01C7/005 , H01C7/006 , H01C17/075 , H01G4/18 , H01G4/33 , H01L23/5223 , H01L23/5227 , H01L23/5228 , H01L23/5328 , H01L2924/0002 , H01L2924/00
摘要： A method and structure for an integrated circuit chip has a logic core which includes a plurality of insulating and conducting levels, an exterior conductor level and passive devices having a conductive polymer directly connected to the exterior conductor level. The passive devices contain RF devices which also includes resistor, capacitor, and/or inductor. The resistors can be serpentine resistors and the capacitors can be interdigitated capacitors.
摘要翻译：集成电路芯片的方法和结构具有包括多个绝缘和导电水平的逻辑芯，外部导体水平和具有直接连接到外部导体水平的导电聚合物的无源器件。无源器件包含还包括电阻器，电容器和/或电感器的RF器件。电阻器可以是蛇形电阻器，电容器可以是交错电容器。

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