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1. 发明授权

US6141632A Method for use in simulation of an SOI device 有权
标题翻译：用于SOI器件仿真的方法
公开(公告)号：US6141632A
公开(公告)日：2000-10-31
申请号：US388594
申请日：1999-09-02
申请人： George E. Smith, III , Fariborz Assaderaghi , Paul D. Muench , Lawrence F. Wagner, Jr. , Timothy L. Walters
发明人： George E. Smith, III , Fariborz Assaderaghi , Paul D. Muench , Lawrence F. Wagner, Jr. , Timothy L. Walters
IPC分类号： G06F17/50 , G06G7/48
CPC分类号： G06F17/5036
摘要： A method for use in electronic design models encoded into design software for use in SOI based FET logic design includes simulation of an SOI device by and setting a floating body voltage to any desired value at any time during the simulation, by adding to the model an ideal voltage source, whose value is a desired body voltage, in series with an ideal current source, whose value is a constant times the voltage across itself. When the constant is zero, no current can flow, and any additional components have no effect on the circuit. When the constant is non-zero, said ideal current source appears to be the same as a resistor such that current can flow in to or out from the body node, setting its voltage. The constant is kept zero at all times, except when it is desired to change the body voltage. The body voltage can be reset at any time to solve the problem of successive delays in one simulation run and resetting the voltage before each delay measurement starts. To solve the problem of predicting the delay in a delay predictor (for example, delay rules generation), the offset from the body voltage as a part of the best case/worst case determination is included. The improved process employs a topological analysis for circuit elements to determine whether the element falls in one of several categories, and in the process determines which elements of a circuit might be in AC equilibrium.
摘要翻译：用于编码为用于基于SOI的FET逻辑设计的设计软件的电子设计模型中的方法包括通过在仿真期间的任何时间对浮动体电压进行模拟并将浮体电压设置为任何期望值，通过向模型添加理想的电压源，其值是期望的体电压，与理想电流源串联，其值是恒定倍数自身的电压。当常数为零时，不会流过电流，任何附加组件对电路都没有影响。当常数不为零时，所述理想电流源似乎与电阻器相同，使得电流可以流入或流出身体节点，从而设定其电压。恒定值始终保持为零，除非需要改变体电压。可以随时重置体电压，以解决一次模拟运行中连续延迟的问题，并在每次延迟测量开始之前复位电压。为了解决预测延迟预测器中的延迟（例如，延迟规则生成）的问题，包括作为最佳情况/最坏情况确定的一部分的与体电压的偏移。改进的过程采用电路元件的拓扑分析来确定元件是否属于几个类别之一，并且在该过程中确定电路的哪些元件可能处于AC平衡状态。

2. 发明授权

US5371022A Method of forming a novel vertical-gate CMOS compatible lateral bipolar transistor 失效
标题翻译：形成新型垂直栅极CMOS兼容横向双极晶体管的方法
公开(公告)号：US5371022A
公开(公告)日：1994-12-06
申请号：US203129
申请日：1994-02-28
申请人： Chang-Ming Hsieh , Louis L. G. Hsu , Shaw-Ning Mei , Ronald W. Knepper , Lawrence F. Wagner, Jr.
发明人： Chang-Ming Hsieh , Louis L. G. Hsu , Shaw-Ning Mei , Ronald W. Knepper , Lawrence F. Wagner, Jr.
IPC分类号： H01L21/331 , H01L21/8222 , H01L21/8249 , H01L27/06 , H01L27/082 , H01L29/73 , H01L29/735 , H01L21/265
CPC分类号： H01L29/7317 , H01L27/0623 , H01L29/735
摘要： A transistor with silicon on insulator (SOI) intrinsic base and a collector each formed by a low temperature epitaxial process and each orientated vertically with respect to the (SOI) substrate. The base width can be as narrow as in a conventional vertical transistor. Similarly, the collector width can be precisely controlled.
摘要翻译：具有绝缘体上硅（SOI）本征基极和集电极的晶体管各自由低温外延工艺形成，并且各自相对于（SOI）衬底垂直取向。基极宽度可以像传统的垂直晶体管那样窄。类似地，可以精确地控制收集器宽度。

3. 发明授权

US5341023A Novel vertical-gate CMOS compatible lateral bipolar transistor 失效
标题翻译：新型垂直门CMOS兼容横向双极晶体管
公开(公告)号：US5341023A
公开(公告)日：1994-08-23
申请号：US900881
申请日：1992-06-18
申请人： Chang-Ming Hsieh , Louis L. C. Hsu , Shaw-Ning Mei , Ronald W. Knepper , Lawrence F. Wagner, Jr.
发明人： Chang-Ming Hsieh , Louis L. C. Hsu , Shaw-Ning Mei , Ronald W. Knepper , Lawrence F. Wagner, Jr.
IPC分类号： H01L21/331 , H01L21/8222 , H01L21/8249 , H01L27/06 , H01L27/082 , H01L29/73 , H01L29/735 , H01L29/72
CPC分类号： H01L29/7317 , H01L27/0623 , H01L29/735
摘要： A lateral bipolar transistor has an extrinsic base layer on either side of a centrally disposed emitter layer and an intrinsic base and a collector oriented perpendicularly to the extrinsic base and collector layers.
摘要翻译：横向双极晶体管在中心布置的发射极层的任一侧上具有非本征基极层，并且本征基极和集电极垂直于外部基极和集电极层取向。

4. 发明申请

US20090224334A1 Merged Field Effect Transistor Cells For Switching 失效
标题翻译：合并场效应晶体管电池用于开关
公开(公告)号：US20090224334A1
公开(公告)日：2009-09-10
申请号：US12045159
申请日：2008-03-10
申请人： Lawrence F. Wagner, JR. , Randy L. Wolf
发明人： Lawrence F. Wagner, JR. , Randy L. Wolf
IPC分类号： H01L27/088 , H01L21/82 , G06F9/455
CPC分类号： H01L27/1203 , H01L27/0705
摘要： Disclosed are embodiments of an improved integrated circuit switching device that incorporates multiple sets of series connected field effect transistors with each set further connected in parallel between two nodes. The sets are arranged in a linear fashion with each set positioned such that it is in contact with and essentially symmetrical relative to an adjacent set. Arranging the sets in this manner allows adjacent diffusion regions of the same type (i.e., sources or drains) from adjacent sets to be merged. Merging of the diffusion regions provides several benefits, including but not limited to, reducing the device size, reducing the amount of required wiring for the device (i.e., reducing resistance) and reducing side capacitance between the now merged diffusion regions and the substrate. Also disclosed are embodiments of an associated design structure for the device and an associated method of forming the device.
摘要翻译：公开了一种改进的集成电路开关装置的实施例，其包括多组串联连接的场效应晶体管，每组集合进一步在两个节点之间并联连接。这些组以线性方式布置，其中每组被定位成使得其相对于相邻组接触并且基本上对称。以这种方式布置集合允许相邻集合的相邻类型（即，源或漏极）的相邻扩散区域被合并。扩散区域的合并提供了几个好处，包括但不限于减小器件尺寸，减少器件所需的布线的量（即降低电阻）并减小现在合并的扩散区域和衬底之间的侧电容。还公开了用于装置的相关联的设计结构的实施例以及形成装置的相关联的方法。

5. 发明授权

US06562666B1 Integrated circuits with reduced substrate capacitance 失效
标题翻译：具有降低衬底电容的集成电路
公开(公告)号：US06562666B1
公开(公告)日：2003-05-13
申请号：US09702314
申请日：2000-10-31
申请人： Heemyong Park , Fariborz Assaderaghi , Jack A. Mandelman , Ghavam G. Shahidi , Lawrence F. Wagner, Jr.
发明人： Heemyong Park , Fariborz Assaderaghi , Jack A. Mandelman , Ghavam G. Shahidi , Lawrence F. Wagner, Jr.
IPC分类号： H01L2100
CPC分类号： H01L21/84 , H01L27/1203
摘要： Capacitance between source/drain and p-type substrate in SOI CMOS circuits is reduced by implanting an n-type layer below the oxide layer, thereby forming a fully depleted region that adds to the thickness of the oxide layer, while creating a junction capacitance region that reduces the total device to substrate capacitance.
摘要翻译：在SOI CMOS电路中的源极/漏极和p型衬底之间的电容通过在氧化物层下方注入n型层来减少，从而形成增加氧化物层的厚度的完全耗尽区，同时产生结电容区这将总体器件减少到衬底电容。

6. 发明授权

US06490546B1 Method for obtaining DC convergence for SOI FET models in a circuit simulation program 失效
标题翻译：在电路仿真程序中获得SOI FET模型的直流收敛的方法
公开(公告)号：US06490546B1
公开(公告)日：2002-12-03
申请号：US09304611
申请日：1999-05-04
申请人： Richard Kimmel , Lawrence F. Wagner, Jr.
发明人： Richard Kimmel , Lawrence F. Wagner, Jr.
IPC分类号： G06F1750
CPC分类号： G06F17/5036
摘要： A process for obtaining accurate DC convergence in a DC phase of a circuit simulation program for models of field effect transistors (FETs) on a silicon-on-insulator (SOI) substrate. The process comprises running iterations of the DC phase of the circuit simulation program such that error criteria are satisfied, wherein the pseudo-time step changes at each iteration until it reaches a value such that a desired current value is achieved. DC convergence is also achieved by reducing the magnitude of the capacitive and/or charge elements connected to the floating body regions of the field effect transistors on the silicon-on-insulator substrate model during the DC phase to achieve a desired current value.
摘要翻译：一种用于在绝缘体上硅（SOI）衬底上的场效应晶体管（FET）模型的电路仿真程序的DC相中获得精确DC收敛的过程。该过程包括运行电路仿真程序的DC阶段的迭代，使得满足错误准则，其中伪时间步骤在每次迭代期间改变，直到达到实现所需电流值的值。通过在DC阶段期间减小连接到绝缘体上硅衬底模型上的场效应晶体管的浮体区域的电容和/或电荷元件的大小以实现期望电流值，也可实现DC收敛。

7. 发明授权

US5258640A Gate controlled Schottky barrier diode 失效
标题翻译：门控肖特基势垒二极管
公开(公告)号：US5258640A
公开(公告)日：1993-11-02
申请号：US939214
申请日：1992-09-02
申请人： Chang-Ming Hsieh , Louis L. Hsu , Phung T. Nguyen , Lawrence F. Wagner, Jr.
发明人： Chang-Ming Hsieh , Louis L. Hsu , Phung T. Nguyen , Lawrence F. Wagner, Jr.
IPC分类号： H01L29/739 , H01L29/48 , H01L29/56
CPC分类号： H01L29/7391
摘要： An integrated gate and semiconductor barrier layer diode which functions as a regular diode when the gate is turned off and as, a Schottky barrier diode with the gate turned on.
摘要翻译：集成栅极和半导体势垒层二极管，当栅极截止时用作正常二极管，并且作为肖特基势垒二极管导通。

8. 发明授权

US07863691B2 Merged field effect transistor cells for switching 失效
标题翻译：合并场效应晶体管单元进行开关
公开(公告)号：US07863691B2
公开(公告)日：2011-01-04
申请号：US12045159
申请日：2008-03-10
申请人： Lawrence F. Wagner, Jr. , Randy L. Wolf
发明人： Lawrence F. Wagner, Jr. , Randy L. Wolf
IPC分类号： H01L27/10
CPC分类号： H01L27/1203 , H01L27/0705
摘要： Disclosed are embodiments of an improved integrated circuit switching device that incorporates multiple sets of series connected field effect transistors with each set further connected in parallel between two nodes. The sets are arranged in a linear fashion with each set positioned such that it is in contact with and essentially symmetrical relative to an adjacent set. Arranging the sets in this manner allows adjacent diffusion regions of the same type (i.e., sources or drains) from adjacent sets to be merged. Merging of the diffusion regions provides several benefits, including but not limited to, reducing the device size, reducing the amount of required wiring for the device (i.e., reducing resistance) and reducing side capacitance between the now merged diffusion regions and the substrate. Also disclosed are embodiments of an associated design structure for the device and an associated method of forming the device.
摘要翻译：公开了一种改进的集成电路开关装置的实施例，其包括多组串联连接的场效应晶体管，每组集合进一步在两个节点之间并联连接。这些组以线性方式布置，其中每组被定位成使得其相对于相邻组接触并且基本上对称。以这种方式布置集合允许相邻集合的相邻类型（即，源或漏极）的相邻扩散区域被合并。扩散区域的合并提供了几个好处，包括但不限于减小器件尺寸，减少器件所需的布线的量（即降低电阻）并减小现在合并的扩散区域和衬底之间的侧电容。还公开了用于装置的相关联的设计结构的实施例以及形成装置的相关联的方法。

9. 发明授权

US07139990B2 Method of checking the layout versus the schematic of multi-fingered MOS transistor layouts using a sub-circuit based extraction 失效
标题翻译：使用基于子电路的提取来检查布局与多指MOS晶体管布局的示意图的方法
公开(公告)号：US07139990B2
公开(公告)日：2006-11-21
申请号：US10807478
申请日：2004-03-23
申请人： Raminderpal Singh , Yue Tan , Jean-Oliver Plouchart , Lawrence F. Wagner, Jr. , Mohamed Talbi , John M. Safran , Kun Wu
发明人： Raminderpal Singh , Yue Tan , Jean-Oliver Plouchart , Lawrence F. Wagner, Jr. , Mohamed Talbi , John M. Safran , Kun Wu
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5022
摘要： A sub-circuit based extraction method which extracts a multi-finger MOS transistor directly as a sub-circuit is described. By adding three marking layers, the method provides the layout extracted netlist with a complete list of device geometric parameters corresponding to the device properties as presented in the sub-circuit model based schematic netlist. By performing a layout-versus-schematic comparison based on all geometric parameters extracted, the layout checking is performed in a complete and accurate way where each device parameter is checked against the corresponding design schematic. This complete and accurate geometric parameter comparison enhances the confidence level of the layout physical verification.
摘要翻译：描述了一种基于子电路的提取方法，其直接提取多指状MOS晶体管作为子电路。通过添加三个标记层，该方法为布局提取的网表提供了与基于子电路模型的示意图网表中所示的设备属性对应的设备几何参数的完整列表。通过基于提取的所有几何参数执行布局与原理图比较，以完整和准确的方式执行布局检查，其中根据相应的设计原理图检查每个设备参数。这种完整和准确的几何参数比较增强了布局物理验证的置信度。

10. 发明授权

US6023577A Method for use in simulation of an SOI device 失效
标题翻译：用于SOI器件仿真的方法
公开(公告)号：US6023577A
公开(公告)日：2000-02-08
申请号：US938676
申请日：1997-09-26
申请人： George E. Smith, III , Lawrence F. Wagner, Jr. , Timothy L. Walters , Fariborz Assaderaghi
发明人： George E. Smith, III , Lawrence F. Wagner, Jr. , Timothy L. Walters , Fariborz Assaderaghi
IPC分类号： G06F17/50 , G06G7/48
CPC分类号： G06F17/5036
摘要： A method for use in electronic design models encoded into design software for use in SOI based FET logic design includes simulation of an SOI device and setting a floating body voltage to any desired value at any time during the simulation, by adding to the model an ideal voltage source, whose value is a desired body voltage, in series with an ideal current source, whose value is a constant times the voltage across itself. When the constant is zero no current can flow, and any additional components have no effect on the circuit. When the constant is non-zero, said ideal current source appears to be the same as a resistor such that, current can flow in to or out from the body node, setting its voltage. The constant is kept zero at all times, except when it is desired to change the body voltage. The body voltage can be reset at any time to solve the problem of successive delays in one simulation run and resetting the voltage before each delay measurement starts. To solve the problem of predicting the delay in a delay predictor (for example, NDR rules generation), the offset from the body voltage as a part of the best case/worst case determination is included.
摘要翻译：用于编码为用于基于SOI的FET逻辑设计的设计软件的电子设计模型中的方法包括在模拟期间的任何时间，模拟SOI器件并将浮动体电压设置为任何所需值，通过向模型添加理想电压源，其值是期望的体电压，与理想电流源串联，其值为恒定倍数的电压。当常数为零时，电流不能流动，任何附加的组件对电路都没有影响。当常数不为零时，所述理想电流源似乎与电阻器相同，使得电流可以流入或流出体节点，从而设定其电压。恒定值始终保持为零，除非需要改变体电压。可以随时重置体电压，以解决一次模拟运行中连续延迟的问题，并在每次延迟测量开始之前复位电压。为了解决预测延迟预测器中的延迟（例如，NDR规则生成）的问题，包括作为最佳情况/最坏情况判定的一部分的与体电压的偏移。

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