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1. 发明专利

IL178857D0 A SYSTEM AND METHOD FOR PHOTOLITHOGRAPHY IN SEMICONDUCTOR MANUFACTURING 未知
公开(公告)号：IL178857D0
公开(公告)日：2007-03-08
申请号：IL17885706
申请日：2006-10-25
申请人： TAIWAN SEMICONDUCTOR MFG , CHIN HSIANG LIN , KUEI SHUN CHEN , TSAI SHENG GAU , CHUN KUANG CHEN , HSIAO TZU LU , FU JYE LIANG
摘要： The method involves providing a substrate, and coating a photo resist layer on the substrate. The substrate is exposed by utilizing a combination of high angle illumination and focus drift exposure methods. A circular area is formed within an illumination area. A torus-shaped area is formed immediately adjacent to the circular area and within the illumination area. Another torus-shaped area is formed that is not adjacent to the circular area and is within the illumination area. The focus drift exposure method comprises titling the substrate. Independent claims are also included for the following: (1) a photolithography system for processing a semiconductor wafer (2) a method for patterning a semiconductor substrate.

2. 发明授权

US09070623B2 Controlling gate formation for high density cell layout 有权
标题翻译：控制高密度电池布局的栅极形成
公开(公告)号：US09070623B2
公开(公告)日：2015-06-30
申请号：US12897559
申请日：2010-10-04
申请人： Harry-Hak-Lay Chuang , Bao-Ru Young , Kuei Shun Chen , Cheng Cheng Kuo , George Liu , Tsung-Chieh Tsai , Yuhi-Jier Mii
发明人： Harry-Hak-Lay Chuang , Bao-Ru Young , Kuei Shun Chen , Cheng Cheng Kuo , George Liu , Tsung-Chieh Tsai , Yuhi-Jier Mii
IPC分类号： H01L21/338 , H01L21/28 , H01L29/66 , H01L21/8234 , H01L27/02 , H01L29/423 , H01L29/49
CPC分类号： H01L21/28123 , H01L21/823437 , H01L27/0207 , H01L29/0653 , H01L29/0696 , H01L29/42376 , H01L29/4238 , H01L29/4966 , H01L29/66545 , H01L29/66606 , H01L29/7831
摘要： Methods of forming a semiconductor structure and the semiconductor structure are disclosed. In one embodiment, a method includes forming a gate dielectric layer over a substrate, forming a gate electrode layer over the gate dielectric layer, and etching the gate electrode layer and the gate dielectric layer to form a horizontal gate structure and a vertical gate structure, wherein the horizontal gate structure and the vertical gate structure are connected by an interconnection portion. The method further includes forming a photoresist covering the horizontal gate structure and the vertical gate structure, with the photoresist having a gap exposing the interconnection portion between the horizontal gate structure and the vertical gate structure, and then etching the interconnection portion.
摘要翻译：公开了形成半导体结构和半导体结构的方法。在一个实施例中，一种方法包括在衬底上形成栅极电介质层，在栅极电介质层上形成栅极电极层，并蚀刻栅极电极层和栅极电介质层以形成水平栅极结构和垂直栅极结构，其中所述水平栅极结构和所述垂直栅极结构通过互连部分连接。该方法还包括形成覆盖水平栅极结构和垂直栅极结构的光致抗蚀剂，其中光致抗蚀剂具有暴露水平栅极结构和垂直栅极结构之间的互连部分的间隙，然后蚀刻互连部分。

3. 发明授权

US08932936B2 Method of forming a FinFET device 有权
标题翻译：形成FinFET器件的方法
公开(公告)号：US08932936B2
公开(公告)日：2015-01-13
申请号：US13449118
申请日：2012-04-17
申请人： Chia-Chu Liu , Kuei-Shun Chen , Chih-Hsiung Peng , Chi-Kang Chang , Chiang Mu-Chi , Sheng-Yu Chang , Hua Feng Chen , Chao-Cheng Chen , Ryan Chia-Jen Chen
发明人： Chia-Chu Liu , Kuei-Shun Chen , Chih-Hsiung Peng , Chi-Kang Chang , Chiang Mu-Chi , Sheng-Yu Chang , Hua Feng Chen , Chao-Cheng Chen , Ryan Chia-Jen Chen
IPC分类号： H01L21/00
CPC分类号： H01L21/3086 , H01L21/76224
摘要： A method for fabricating a device is disclosed. An exemplary method includes providing a substrate and forming a plurality of fins over the substrate. The method further includes forming a first opening in the substrate in a first longitudinal direction. The method further includes forming a second opening in the substrate in a second longitudinal direction. The first and second longitudinal directions are different. The method further includes depositing a filling material in the first and second openings.
摘要翻译：公开了一种制造装置的方法。一种示例性的方法包括提供衬底并在衬底上形成多个鳍。该方法还包括在第一纵向方向上在基板中形成第一开口。该方法还包括在第二纵向方向上在基板中形成第二开口。第一和第二纵向是不同的。该方法还包括在第一和第二开口中沉积填充材料。

4. 发明授权

US08877598B2 Method of lithography process with an under isolation material layer 有权
标题翻译：具有隔离材料层的光刻工艺方法
公开(公告)号：US08877598B2
公开(公告)日：2014-11-04
申请号：US13486050
申请日：2012-06-01
申请人： Chung-Ming Wang , Yu Lun Liu , Chia-Chu Liu , Ya Hui Chang , Kuei-Shun Chen
发明人： Chung-Ming Wang , Yu Lun Liu , Chia-Chu Liu , Ya Hui Chang , Kuei-Shun Chen
IPC分类号： H01L21/336 , H01L21/4763 , H01L29/786 , H01L27/12
CPC分类号： H01L29/78606 , H01L21/02118 , H01L21/02282 , H01L21/0271 , H01L21/2652 , H01L21/31144 , H01L27/1292 , H01L29/6659
摘要： A method of forming a integrated circuit pattern. The method includes forming gate stacks on a substrate, two adjacent gate stacks of the gate stacks being spaced away by a dimension G; forming a nitrogen-containing layer on the gate stacks and the substrate; forming a dielectric material layer on the nitrogen-containing layer, the dielectric material layer having a thickness T substantially less than G/2; coating a photoresist layer on the dielectric material layer; and patterning the photoresist layer by a lithography process.
摘要翻译：一种形成集成电路图案的方法。该方法包括在衬底上形成栅极堆叠，门堆叠的两个相邻栅堆叠被尺寸G间隔开; 在栅叠层和衬底上形成含氮层; 在所述含氮层上形成介电材料层，所述电介质材料层的厚度T大致小于G / 2; 在介电材料层上涂覆光致抗蚀剂层; 并通过光刻工艺图案化光致抗蚀剂层。

5. 发明授权

US08623231B2 Method for etching an ultra thin film 有权
标题翻译：蚀刻超薄膜的方法
公开(公告)号：US08623231B2
公开(公告)日：2014-01-07
申请号：US12137186
申请日：2008-06-11
申请人： George Liu , Kuei Shun Chen , Vencent Chang , Chih-Yang Yeh
发明人： George Liu , Kuei Shun Chen , Vencent Chang , Chih-Yang Yeh
IPC分类号： H01L21/302 , H01L21/461 , C03C15/00 , C03C25/68 , C25F3/00
CPC分类号： H01L21/30604 , C09K13/00 , C09K13/02 , C09K13/06 , H01L21/308 , H01L21/31111 , H01L21/31144 , H01L21/32134
摘要： A method for etching an ultra thin film is provided which includes providing a substrate having the ultra thin film formed thereon, patterning a photosensitive layer formed over the ultra thin film, etching the ultra thin film using the patterned photosensitive layer, and removing the patterned photosensitive layer. The etching process includes utilizing an etch material with a diffusion resistant carrier such that the etch material is prevented from diffusing to a region underneath the photosensitive layer and removing portions of the ultra thin film underneath the photosensitive layer.
摘要翻译：提供了一种用于蚀刻超薄膜的方法，其包括提供其上形成有超薄膜的基板，对形成在超薄膜上的感光层进行图案化，使用图案化感光层蚀刻超薄膜，以及去除图案化感光层层。蚀刻工艺包括利用具有抗扩散性载体的蚀刻材料，使得防止蚀刻材料扩散到感光层下方的区域并去除感光层下面的超薄膜的部分。

6. 发明授权

US08431291B2 Intensity selective exposure photomask 有权
标题翻译：强度选择性曝光光掩模
公开(公告)号：US08431291B2
公开(公告)日：2013-04-30
申请号：US13281198
申请日：2011-10-25
申请人： George Liu , Kuei Shun Chen , Chih-Yang Yeh , Te-Chih Huang , Wen-Hao Liu , Ying-Chou Cheng , Boren Luo , Tsong-Hua Ou , Yu-Po Tang , Wen-Chun Huang , Ru-Gun Liu , Shu-Chen Lu , Yu Lun Liu , Yao-Ching Ku , Tsai-Sheng Gau
发明人： George Liu , Kuei Shun Chen , Chih-Yang Yeh , Te-Chih Huang , Wen-Hao Liu , Ying-Chou Cheng , Boren Luo , Tsong-Hua Ou , Yu-Po Tang , Wen-Chun Huang , Ru-Gun Liu , Shu-Chen Lu , Yu Lun Liu , Yao-Ching Ku , Tsai-Sheng Gau
IPC分类号： G03F1/00 , G03F1/36
CPC分类号： G06F17/5068 , G03F1/00 , G03F1/68
摘要： An intensity selective exposure photomask, also describes as a gradated photomask, is provided. The photomask includes a first region including a first array of sub-resolution features. The first region blocks a first percentage of the incident radiation. The photomask also includes a second region including a second array of sub-resolution features. The second region blocks a second percentage of the incident radiation different that the first percentage.
摘要翻译：还提供强度选择性曝光光掩模，还描述为渐变光掩模。光掩模包括包括第一子分解特征阵列的第一区域。第一个区域阻止了第一个入射辐射的百分比。光掩模还包括包括第二子分辨率特征阵列的第二区域。第二个区域阻止了第二个百分比的入射辐射不同于第一个百分比。

7. 发明授权

US08158306B2 Method and system for combining photomasks to form semiconductor devices 有权
标题翻译：用于组合光掩模以形成半导体器件的方法和系统
公开(公告)号：US08158306B2
公开(公告)日：2012-04-17
申请号：US12886391
申请日：2010-09-20
申请人： Kuei Shun Chen , Chin-Hsiang Lin , Chih-Cheng Chiu
发明人： Kuei Shun Chen , Chin-Hsiang Lin , Chih-Cheng Chiu
IPC分类号： G03F1/00
CPC分类号： G03F1/36 , G03F1/70
摘要： A photomask set includes at least two masks that combine to form a device pattern in a semiconductor device. Orthogonal corners may be produced in a semiconductor device pattern to include one edge defined by a first mask and an orthogonal edge defined by a second mask. The mask set may include a first mask with compensation features and a second mask with void areas overlaying the compensation features when the first and second masks are aligned with one another, such that the compensation features are removed when patterns are successfully formed from the first and second masks. The compensation features alleviate proximity effects during the formation of device features.
摘要翻译：光掩模组包括组合以在半导体器件中形成器件图案的至少两个掩模。可以在半导体器件图案中产生正交角，以包括由第一掩模限定的一个边缘和由第二掩模限定的正交边缘。掩模组可以包括具有补偿特征的第一掩模和当第一和第二掩模彼此对准时覆盖补偿特征的空隙区域的第二掩模，使得当从第一和第二掩模成功形成图案时，补偿特征被去除第二个面具补偿功能可以减轻设备特征形成过程中的邻近效应。

8. 发明授权

US08119992B2 System for overlay measurement in semiconductor manufacturing 有权
标题翻译：半导体制造中覆盖测量系统
公开(公告)号：US08119992B2
公开(公告)日：2012-02-21
申请号：US12537410
申请日：2009-08-07
申请人： Hsiao-Tzu Lu , Chin-Hsiang Lin , Hua-Shu Wu , Chia-Hsiang Lin , Kuei Shun Chen
发明人： Hsiao-Tzu Lu , Chin-Hsiang Lin , Hua-Shu Wu , Chia-Hsiang Lin , Kuei Shun Chen
IPC分类号： G01J1/42 , H01L23/544 , H01L21/76
CPC分类号： G03F7/70633 , H01L2924/0002 , H01L2924/00
摘要： Provided is a system for overlay measurement in semiconductor manufacturing that includes a generator for exposing an overlay target to radiation and a detector for detecting reflected beams of the overlay target. The reflected beams are for overlay measurement and include at least two different beams.
摘要翻译：提供了一种用于半导体制造中的覆盖测量的系统，其包括用于将覆盖目标曝光于辐射的发生器和用于检测覆盖目标的反射光束的检测器。反射光束用于重叠测量，并且包括至少两个不同的光束。

9. 发明申请

US20120040276A1 METHOD OF FORMING AND USING PHOTOLITHOGRAPHY MASK HAVING A SCATTERING BAR STRUCTURE 有权
标题翻译：形成和使用具有散射条结构的光刻胶掩模的方法
公开(公告)号：US20120040276A1
公开(公告)日：2012-02-16
申请号：US13277920
申请日：2011-10-20
申请人： Yung-Sung Yen , Kuei Shun Chen , Chien-Wen Lai , Cherng-Shyan Tsay
发明人： Yung-Sung Yen , Kuei Shun Chen , Chien-Wen Lai , Cherng-Shyan Tsay
IPC分类号： G03F7/20 , G03F1/36
CPC分类号： G03F1/36
摘要： A method of forming a photolithography mask including forming a first linear non-dense feature on the mask and forming a plurality of parallel linear assist features disposed substantially perpendicular to the at least one linear non-dense design feature. In an embodiment, the photolithography mask further includes a first transverse linear assist feature disposed substantially transverse to the plurality of parallel linear assist features.
摘要翻译：一种形成光刻掩模的方法，包括在掩模上形成第一线性非致密特征并形成基本上垂直于至少一个线性非致密设计特征设置的多个平行线性辅助特征。在一个实施例中，光刻掩模还包括基本横向于多个平行线性辅助特征设置的第一横向线性辅助特征。

10. 发明授权

US08101340B2 Method of inhibiting photoresist pattern collapse 有权
标题翻译：抑制光刻胶图案崩溃的方法
公开(公告)号：US08101340B2
公开(公告)日：2012-01-24
申请号：US11746202
申请日：2007-05-09
申请人： Ching-Yu Chang , Heng-Jen Lee , Chin-Hsiang Lin , Hua-Tai Lin , Kuei Shun Chen , Bang-Chein Ho , Li-Kong Turn , Hung-Jui Kuo , Ko-Bin Kao , Tsung-Chih Chien
发明人： Ching-Yu Chang , Heng-Jen Lee , Chin-Hsiang Lin , Hua-Tai Lin , Kuei Shun Chen , Bang-Chein Ho , Li-Kong Turn , Hung-Jui Kuo , Ko-Bin Kao , Tsung-Chih Chien
IPC分类号： G03F7/00
CPC分类号： G03F7/40
摘要： A method of inhibiting photoresist pattern collapse which includes the steps of providing a substrate; providing a photoresist layer on the substrate; exposing and developing the photoresist layer; applying a top anti-reflective coating layer to the photoresist layer; rinsing the photoresist layer; and drying the photoresist layer.
摘要翻译：一种抑制光致抗蚀剂图案塌陷的方法，包括提供基底的步骤; 在衬底上提供光致抗蚀剂层; 曝光和显影光致抗蚀剂层; 将顶部抗反射涂层施加到光致抗蚀剂层上; 冲洗光刻胶层; 并干燥光刻胶层。

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