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1. 发明专利

IL178857D0 A SYSTEM AND METHOD FOR PHOTOLITHOGRAPHY IN SEMICONDUCTOR MANUFACTURING 未知
公开(公告)号：IL178857D0
公开(公告)日：2007-03-08
申请号：IL17885706
申请日：2006-10-25
申请人： TAIWAN SEMICONDUCTOR MFG , CHIN HSIANG LIN , KUEI SHUN CHEN , TSAI SHENG GAU , CHUN KUANG CHEN , HSIAO TZU LU , FU JYE LIANG
摘要： The method involves providing a substrate, and coating a photo resist layer on the substrate. The substrate is exposed by utilizing a combination of high angle illumination and focus drift exposure methods. A circular area is formed within an illumination area. A torus-shaped area is formed immediately adjacent to the circular area and within the illumination area. Another torus-shaped area is formed that is not adjacent to the circular area and is within the illumination area. The focus drift exposure method comprises titling the substrate. Independent claims are also included for the following: (1) a photolithography system for processing a semiconductor wafer (2) a method for patterning a semiconductor substrate.

2. 发明授权

US09201022B2 Extraction of systematic defects 有权
标题翻译：提取系统缺陷
公开(公告)号：US09201022B2
公开(公告)日：2015-12-01
申请号：US13152135
申请日：2011-06-02
申请人： Jia-Rui Hu , Te-Chih Huang , Chih-Ming Ke , Hua-Tai Lin , Tsai-Sheng Gau
发明人： Jia-Rui Hu , Te-Chih Huang , Chih-Ming Ke , Hua-Tai Lin , Tsai-Sheng Gau
IPC分类号： G06K9/00 , G01N21/95 , G06T7/00 , G01N23/00 , G01N21/956 , G01N21/88
CPC分类号： G01N21/9501 , G01N21/95607 , G01N23/00 , G01N23/225 , G01N2021/8825 , G01N2021/8861 , G01N2021/8867 , G01N2021/8874 , G01N2021/95676 , G01N2223/6116 , G06T7/0004 , G06T7/0006 , G06T2207/30148
摘要： In one embodiment, a method for extracting systematic defects is provided. The method includes inspecting a wafer outside a process window to obtain inspection data, defining a defect pattern from the inspection data, filtering defects from design data using a pattern search for the defined defect pattern within the design data, inspecting defects inside the process window with greater sensitivity than outside the process window, and determining systematic defects inside the process window. A computer readable storage medium, and a system for extracting systematic defects are also provided.
摘要翻译：在一个实施例中，提供了用于提取系统缺陷的方法。该方法包括检查处理窗口外部的晶片以获得检查数据，从检查数据中定义缺陷图案，使用对设计数据内定义的缺陷图案的模式搜索过滤设计数据中的缺陷，检查处理窗口内的缺陷，比过程窗口以外的灵敏度更高，并确定过程窗口内的系统缺陷。还提供了计算机可读存储介质和用于提取系统缺陷的系统。

3. 发明授权

US08656319B2 Optical proximity correction convergence control 有权
标题翻译：光学接近校正收敛控制
公开(公告)号：US08656319B2
公开(公告)日：2014-02-18
申请号：US13368919
申请日：2012-02-08
申请人： Cheng-Cheng Kuo , Ching-Che Tsai , Tzu-Chun Lo , Chih-Wei Hsu , Hua-Tai Lin , Tsai-Sheng Gau , Wen-Chun Huang , Chih-Shiang Chou , Hsin-Chang Lee , Kuei Shun Chen
发明人： Cheng-Cheng Kuo , Ching-Che Tsai , Tzu-Chun Lo , Chih-Wei Hsu , Hua-Tai Lin , Tsai-Sheng Gau , Wen-Chun Huang , Chih-Shiang Chou , Hsin-Chang Lee , Kuei Shun Chen
IPC分类号： G06F17/50
CPC分类号： G03F7/70441 , G03F7/70125
摘要： A method of optical proximity correction (OPC) convergence control that includes providing a lithography system having a photomask and an illuminator. The method further includes performing an exposure by the illuminator on the photomask. Also, the method includes optimizing an optical illuminator setting for the lithography system with a defined gate pitch in a first direction in a first template. Additionally, the method includes determining OPC correctors to converge the OPC results with a target edge placement error (EPE) to produce a first OPC setting for the first template. The first OPC setting targets a relatively small EPE and mask error enhancement factor (MEEF)of the defined gate pitch in the first template. In addition, the method includes checking the first OPC setting for a relatively small EPE, MEEF and DOM consistency with the first template of the defined gate pitch in a second, adjacent template.
摘要翻译：一种光学邻近校正（OPC）会聚控制的方法，包括提供具有光掩模和照明器的光刻系统。该方法还包括执行照明器在光掩模上的曝光。此外，该方法包括在第一模板中以第一方向限定的门间距优化光刻系统的光照射器设置。此外，该方法包括确定OPC校正器以使目标边缘放置误差（EPE）收敛OPC结果，以产生第一模板的第一OPC设置。第一个OPC设置针对第一个模板中定义的门间距的相对较小的EPE和掩模误差增强因子（MEEF）。此外，该方法包括在第二相邻模板中检查第一OPC设置以获得相对较小的EPE，MEEF和DOM与限定的门间距的第一模板的一致性。

4. 发明授权

US08631379B2 Decomposing integrated circuit layout 有权
标题翻译：分解集成电路布局
公开(公告)号：US08631379B2
公开(公告)日：2014-01-14
申请号：US12702591
申请日：2010-02-09
申请人： Pi-Tsung Chen , Ming-Hui Chih , Ken-Hsien Hsieh , Wei-Long Wang , Wen-Chun Huang , Ru-Gun Liu , Tsai-Sheng Gau , Wen-Ju Yang , Gwan Sin Chang , Yung-Sung Yen
发明人： Pi-Tsung Chen , Ming-Hui Chih , Ken-Hsien Hsieh , Wei-Long Wang , Wen-Chun Huang , Ru-Gun Liu , Tsai-Sheng Gau , Wen-Ju Yang , Gwan Sin Chang , Yung-Sung Yen
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： Various embodiments of the invention provide techniques to ensure a layout for an integrated circuit is split-able. In a method embodiment, a layout is generated in a customer site having a layout library as inputs wherein the library provides exemplary layouts that have been verified to be spit-able and that can be used and layouts that can cause conflicts to avoid. A real-time odd cycle checker is also provided in which the checker identifies in real time conflict areas and odd cycles as they arise during layout generation. To reduce memory usage layouts of various devices may be separated so that each individual layout or a small number of layouts, rather than a large layout for the whole application circuit, can be checked against conflicts. Once the layout is ready at the customer site, it is sent to the foundry site to be decomposed into two masks and taped-out. Other embodiments are also disclosed.
摘要翻译：本发明的各种实施例提供了确保集成电路的布局是可分割的技术。在方法实施例中，在具有布局库作为输入的客户站点中生成布局，其中库提供已经被验证为可以吐出并且可以被使用的示例性布局以及可能引起冲突的布局。还提供了实时奇数周期检查器，其中检查器在布局生成期间出现时实时地识别冲突区域和奇数周期。为了减少各种设备的存储器使用布局可以被分离，使得可以针对冲突来检查每个单独布局或少量布局而不是用于整个应用电路的大布局。一旦布局在客户现场准备就绪，就将其发送到代工厂，将其分解成两个面具并进行录制。还公开了其他实施例。

5. 发明申请

US20130130410A1 METHOD FOR METAL CORRELATED VIA SPLIT FOR DOUBLE PATTERNING 有权
标题翻译：金属相关方法，用于双重方式分割
公开(公告)号：US20130130410A1
公开(公告)日：2013-05-23
申请号：US13743087
申请日：2013-01-16
申请人： Burn Jeng LIN , Tsai-Sheng GAU , Ru-Gun LIU , Wen-Chun HUANG
发明人： Burn Jeng LIN , Tsai-Sheng GAU , Ru-Gun LIU , Wen-Chun HUANG
IPC分类号： H01L21/66
CPC分类号： H01L22/10 , G03F1/70 , G03F7/70433 , G03F7/70466 , G06F17/5036 , G06F17/5072 , G06F17/5081 , H01L21/31144 , H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： A method of via patterning mask assignment for a via layer using double patterning technology, the method includes determining, using a processor, if a via of the via layer intercepts an underlying or overlaying metal structure assigned to a first metal mask. If the via intercepts the metal structure assigned to the first metal mask, assigning the via to a first via mask, wherein the first via mask aligns with the first metal mask. Otherwise, assigning the via to a second via mask, wherein the second via mask aligns with a second metal mask different from the first metal mask.
摘要翻译：一种通过使用双重图案化技术对通孔层进行图案掩模分配的方法，所述方法包括使用处理器来确定通孔层的通孔是否拦截分配给第一金属掩模的下面或重叠的金属结构。如果通孔截取分配给第一金属掩模的金属结构，则将通孔分配给第一通孔掩模，其中第一通孔掩模与第一金属掩模对准。否则，将通孔分配给第二通孔掩模，其中第二通孔掩模与不同于第一金属掩模的第二金属掩模对准。

6. 发明授权

US08381153B2 Dissection splitting with optical proximity correction and mask rule check enforcement 有权
标题翻译：用光学邻近校正和掩模规则检查执行的解剖分割
公开(公告)号：US08381153B2
公开(公告)日：2013-02-19
申请号：US12884442
申请日：2010-09-17
申请人： Chia-Ping Chiang , Yu-Po Tang , Ming-Hui Chih , Cheng-Kun Tsai , Wei-Long Wang , Wen-Chun Huang , Ru-Gun Liu , Tsai-Sheng Gau , Cheng-Lung Tsai , Josh J. H. Feng , Bing-Syun Yeh , Jeng-Shiun Ho , Cheng-Cheng Kuo
发明人： Chia-Ping Chiang , Yu-Po Tang , Ming-Hui Chih , Cheng-Kun Tsai , Wei-Long Wang , Wen-Chun Huang , Ru-Gun Liu , Tsai-Sheng Gau , Cheng-Lung Tsai , Josh J. H. Feng , Bing-Syun Yeh , Jeng-Shiun Ho , Cheng-Cheng Kuo
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/12 , Y02P90/265
摘要： The present disclosure provides one embodiment of an integrated circuit (IC) design method. The method includes receiving an IC design layout having a plurality of main features; applying a main feature dissection to the main features of the IC design layout and generating sub-portions of the main features; performing an optical proximity correction (OPC) to the main features; performing a mask rule check (MRC) to a main feature of the IC design layout; and modifying one of the sub-portions of the main feature if the main feature fails the MRC.
摘要翻译：本公开提供了集成电路（IC）设计方法的一个实施例。该方法包括接收具有多个主要特征的IC设计布局; 将主要特征解剖应用于IC设计布局的主要特征，并生成主要特征的子部分; 对主要特征执行光学邻近校正（OPC）; 执行掩模规则检查（MRC）到IC设计布局的主要特征; 并且如果主要特征使MRC故障，则修改主要特征的一个子部分。

7. 发明授权

US08381139B2 Method for metal correlated via split for double patterning 有权
标题翻译：用于双重图案化的金属相互分离的方法
公开(公告)号：US08381139B2
公开(公告)日：2013-02-19
申请号：US13006608
申请日：2011-01-14
申请人： Burn Jeng Lin , Tsai-Sheng Gau , Ru-Gun Liu , Wen-Chun Huang
发明人： Burn Jeng Lin , Tsai-Sheng Gau , Ru-Gun Liu , Wen-Chun Huang
IPC分类号： G06F17/50
CPC分类号： H01L22/10 , G03F1/70 , G03F7/70433 , G03F7/70466 , G06F17/5036 , G06F17/5072 , G06F17/5081 , H01L21/31144 , H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： The embodiments of via mask splitting methods for double patterning technology described enable via patterning to align to a metal layer underneath or overlying to reduce overlay error and to increase via landing. If adjacent vias violate the G0-mask-split-rule for space or pitch (or both) between vias, the mask assignment of end vias are given higher priority to ensure good landing of end vias, since they are at higher risk of mislanding. The metal correlated via mask splitting methods enable better via performance, such as lower via resistance, and higher via yield.
摘要翻译：所描述的用于双重图案化技术的通孔掩模分裂方法的实施例使得能够经由图案化以对准下面的金属层或覆盖以减少覆盖误差并增加通过着陆。如果相邻的通孔违反了通孔之间的空间或间距（或两者）的G0-掩模分割规则，则优先考虑末端通孔的掩模分配，以确保最终通孔的良好着陆，因为它们具有较高的误放置风险。通过掩模分离方法相关的金属能够实现更好的通过性能，例如较低的通孔电阻和较高的通孔产量。

8. 发明申请

US20120308112A1 EXTRACTION OF SYSTEMATIC DEFECTS 有权
标题翻译：提取系统缺陷
公开(公告)号：US20120308112A1
公开(公告)日：2012-12-06
申请号：US13152135
申请日：2011-06-02
申请人： Jia-Rui Hu , Te-Chih Huang , Chih-Ming Ke , Hua-Tai Lin , Tsai-Sheng Gau
发明人： Jia-Rui Hu , Te-Chih Huang , Chih-Ming Ke , Hua-Tai Lin , Tsai-Sheng Gau
IPC分类号： G06K9/00
CPC分类号： G01N21/9501 , G01N21/95607 , G01N23/00 , G01N23/225 , G01N2021/8825 , G01N2021/8861 , G01N2021/8867 , G01N2021/8874 , G01N2021/95676 , G01N2223/6116 , G06T7/0004 , G06T7/0006 , G06T2207/30148
摘要： In one embodiment, a method for extracting systematic defects is provided. The method includes inspecting a wafer outside a process window to obtain inspection data, defining a defect pattern from the inspection data, filtering defects from design data using a pattern search for the defined defect pattern within the design data, inspecting defects inside the process window with greater sensitivity than outside the process window, and determining systematic defects inside the process window. A computer readable storage medium, and a system for extracting systematic defects are also provided.
摘要翻译：在一个实施例中，提供了用于提取系统缺陷的方法。该方法包括检查处理窗口外部的晶片以获得检查数据，从检查数据中定义缺陷图案，使用对设计数据内定义的缺陷图案的模式搜索过滤设计数据中的缺陷，检查处理窗口内的缺陷，比过程窗口以外的灵敏度更高，并确定过程窗口内的系统缺陷。还提供了计算机可读存储介质和用于提取系统缺陷的系统。

9. 发明申请

US20120264057A1 PATTERNING PROCESS AND PHOTORESIST WITH A PHOTODEGRADABLE BASE 有权
标题翻译：绘图工艺和具有可光控基座的光电元件
公开(公告)号：US20120264057A1
公开(公告)日：2012-10-18
申请号：US13534961
申请日：2012-06-27
申请人： Chien-Wei Wang , Ching-Yu Chang , Tsai-Sheng Gau , Burn Jen Lin
发明人： Chien-Wei Wang , Ching-Yu Chang , Tsai-Sheng Gau , Burn Jen Lin
IPC分类号： G03F7/004 , G03F7/20 , G03F7/027
CPC分类号： G03F7/0045 , Y10S430/106 , Y10S430/114 , Y10S430/12 , Y10S430/128
摘要： A resist material and methods using the resist material are disclosed herein. An exemplary method includes forming a resist layer over a substrate, wherein the resist layer includes a polymer, a photoacid generator, an electron acceptor, and a photodegradable base; performing an exposure process that exposes portions of the resist layer with radiation, wherein the photodegradable base is depleted in the exposed portions of the resist layer during the exposure process; and performing an developing process on the resist layer.
摘要翻译：本文公开了抗蚀剂材料和使用抗蚀剂材料的方法。一种示例性方法包括在衬底上形成抗蚀剂层，其中抗蚀剂层包括聚合物，光致酸产生剂，电子受体和可光降解的碱; 执行曝光处理，其用辐射曝光抗蚀剂层的一部分，其中光可降解碱在曝光过程中耗尽抗蚀剂层的曝光部分; 并对抗蚀剂层进行显影处理。

10. 发明授权

US08264662B2 In-line particle detection for immersion lithography 有权
标题翻译：浸没光刻的在线粒子检测
公开(公告)号：US08264662B2
公开(公告)日：2012-09-11
申请号：US11764573
申请日：2007-06-18
申请人： Li-Jui Chen , Tsai-Sheng Gau , Chi-Kang Peng
发明人： Li-Jui Chen , Tsai-Sheng Gau , Chi-Kang Peng
IPC分类号： G03B27/52 , G03B27/58 , G03B27/32 , G03B27/42
CPC分类号： G03B27/42 , G03F7/70341 , G03F7/7085 , G03F7/70908
摘要： An immersion lithography system, comprising a lens unit configured to project a pattern from an end thereof and onto a wafer, a hood unit configured to confine an immersion fluid to a region of the wafer surrounding the end of the lens unit, a wafer stage configured to position the wafer proximate the end of the lens unit, and at least one of an image capturing apparatus and a scattering light detection apparatus, wherein the image capturing apparatus is coupled to the wafer stage and is configured to capture an image of a surface of the hood unit proximate the wafer stage, and wherein the scattering light detection apparatus is proximate the end of the lens unit and the hood unit and is configured to detect particles on a surface of the wafer stage.
摘要翻译：一种浸没光刻系统，包括被配置为将图案从其端部突出到晶片上的透镜单元，被配置为将浸没流体限制在围绕透镜单元的端部的晶片的区域的罩单元，被配置为将晶片定位在透镜单元的端部附近，以及图像捕获设备和散射光检测设备中的至少一个，其中图像捕获设备耦合到晶片台，并且被配置为捕获图像的表面的图像所述罩单元靠近所述晶片台，并且其中所述散射光检测装置靠近所述透镜单元和所述罩单元的端部，并且被配置为检测所述晶片台的表面上的颗粒。

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