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1. 发明申请

US20120217578A1 METHOD AND SYSTEM FOR METAL GATE FORMATION WITH WIDER METAL GATE FILL MARGIN 有权
标题翻译：用于金属栅格形成的方法和系统，具有宽的金属栅格膜
公开(公告)号：US20120217578A1
公开(公告)日：2012-08-30
申请号：US13466665
申请日：2012-05-08
申请人： Peng-Soon Lim , Meng-Hsuan Chan , Kuang-Yuan Hsu
发明人： Peng-Soon Lim , Meng-Hsuan Chan , Kuang-Yuan Hsu
IPC分类号： H01L29/78 , H01L21/28
CPC分类号： H01L29/4236 , H01L21/28114 , H01L29/42376 , H01L29/66621
摘要： A method includes providing a semiconductor substrate having a gate trench and depositing a metal layer, using a physical vapor deposition (PVD) process, over the substrate to partially fill the trench. The metal layer includes a bottom portion and a sidewall portion that is thinner than the bottom portion. The method also includes forming a coating layer on the metal layer, etching back the coating layer such that a portion of the coating layer protects a portion of the metal layer within the trench, and removing the unprotected portion of the metal layer. A different aspect involves a semiconductor device that includes a gate that includes a trench having a top surface, and a metal layer formed over the trench, wherein the metal layer includes a sidewall portion and a bottom portion, and wherein the sidewall portion is thinner than the bottom portion.
摘要翻译：一种方法包括提供具有栅极沟槽的半导体衬底，并且使用物理气相沉积（PVD）工艺在衬底上沉积金属层以部分地填充沟槽。金属层包括比底部更薄的底部部分和侧壁部分。所述方法还包括在所述金属层上形成涂层，使所述涂层回蚀刻，使得所述涂层的一部分保护所述沟槽内的所述金属层的一部分，以及去除所述金属层的未被保护的部分。不同的方面涉及一种半导体器件，其包括包括具有顶表面的沟槽的栅极和在沟槽上形成的金属层，其中金属层包括侧壁部分和底部，并且其中侧壁部分比底部。

2. 发明授权

US08716785B2 Method and system for metal gate formation with wider metal gate fill margin 有权
标题翻译：金属栅极形成的方法和系统具有更宽的金属栅极填充边缘
公开(公告)号：US08716785B2
公开(公告)日：2014-05-06
申请号：US13466665
申请日：2012-05-08
申请人： Peng-Soon Lim , Meng-Hsuan Chan , Kuang-Yuan Hsu
发明人： Peng-Soon Lim , Meng-Hsuan Chan , Kuang-Yuan Hsu
IPC分类号： H01L29/66
CPC分类号： H01L29/4236 , H01L21/28114 , H01L29/42376 , H01L29/66621
摘要： A method includes providing a semiconductor substrate having a gate trench and depositing a metal layer, using a physical vapor deposition (PVD) process, over the substrate to partially fill the trench. The metal layer includes a bottom portion and a sidewall portion that is thinner than the bottom portion. The method also includes forming a coating layer on the metal layer, etching back the coating layer such that a portion of the coating layer protects a portion of the metal layer within the trench, and removing the unprotected portion of the metal layer. A different aspect involves a semiconductor device that includes a gate that includes a trench having a top surface, and a metal layer formed over the trench, wherein the metal layer includes a sidewall portion and a bottom portion, and wherein the sidewall portion is thinner than the bottom portion.
摘要翻译：一种方法包括提供具有栅极沟槽的半导体衬底，并且使用物理气相沉积（PVD）工艺在衬底上沉积金属层以部分地填充沟槽。金属层包括比底部更薄的底部部分和侧壁部分。所述方法还包括在所述金属层上形成涂层，使所述涂层回蚀刻，使得所述涂层的一部分保护所述沟槽内的所述金属层的一部分，以及去除所述金属层的未被保护的部分。不同的方面涉及一种半导体器件，其包括包括具有顶表面的沟槽的栅极和在沟槽上形成的金属层，其中金属层包括侧壁部分和底部，并且其中侧壁部分比底部。

3. 发明授权

US08193081B2 Method and system for metal gate formation with wider metal gate fill margin 有权
标题翻译：金属栅极形成的方法和系统具有更宽的金属栅极填充边缘
公开(公告)号：US08193081B2
公开(公告)日：2012-06-05
申请号：US12582031
申请日：2009-10-20
申请人： Peng-Soon Lim , Meng-Hsuan Chan , Kuang-Yuan Hsu
发明人： Peng-Soon Lim , Meng-Hsuan Chan , Kuang-Yuan Hsu
IPC分类号： H01L21/283
CPC分类号： H01L29/4236 , H01L21/28114 , H01L29/42376 , H01L29/66621
摘要： A method includes providing a semiconductor substrate having a gate trench and depositing a metal layer, using a physical vapor deposition (PVD) process, over the substrate to partially fill the trench. The metal layer includes a bottom portion and a sidewall portion that is thinner than the bottom portion. The method also includes forming a coating layer on the metal layer, etching back the coating layer such that a portion of the coating layer protects a portion of the metal layer within the trench, and removing the unprotected portion of the metal layer. A different aspect involves a semiconductor device that includes a gate that includes a trench having a top surface, and a metal layer formed over the trench, wherein the metal layer includes a sidewall portion and a bottom portion, and wherein the sidewall portion is thinner than the bottom portion.
摘要翻译：一种方法包括提供具有栅极沟槽的半导体衬底，并且使用物理气相沉积（PVD）工艺在衬底上沉积金属层以部分地填充沟槽。金属层包括比底部更薄的底部部分和侧壁部分。所述方法还包括在所述金属层上形成涂层，使所述涂层回蚀刻，使得所述涂层的一部分保护所述沟槽内的所述金属层的一部分，以及去除所述金属层的未被保护的部分。不同的方面涉及一种半导体器件，其包括包括具有顶表面的沟槽的栅极和在沟槽上形成的金属层，其中金属层包括侧壁部分和底部，并且其中侧壁部分比底部。

4. 发明申请

US20110089484A1 METHOD AND SYSTEM FOR METAL GATE FORMATION WITH WIDER METAL GATE FILL MARGIN 有权
标题翻译：用于金属栅格形成的方法和系统，具有宽的金属栅格膜
公开(公告)号：US20110089484A1
公开(公告)日：2011-04-21
申请号：US12582031
申请日：2009-10-20
申请人： Peng-Soon Lim , Meng-Hsuan Chan , Kuang-Yuan Hsu
发明人： Peng-Soon Lim , Meng-Hsuan Chan , Kuang-Yuan Hsu
IPC分类号： H01L29/78 , H01L21/283
CPC分类号： H01L29/4236 , H01L21/28114 , H01L29/42376 , H01L29/66621
摘要： A method includes providing a semiconductor substrate having a gate trench and depositing a metal layer, using a physical vapor deposition (PVD) process, over the substrate to partially fill the trench. The metal layer includes a bottom portion and a sidewall portion that is thinner than the bottom portion. The method also includes forming a coating layer on the metal layer, etching back the coating layer such that a portion of the coating layer protects a portion of the metal layer within the trench, and removing the unprotected portion of the metal layer. A different aspect involves a semiconductor device that includes a gate that includes a trench having a top surface, and a metal layer formed over the trench, wherein the metal layer includes a sidewall portion and a bottom portion, and wherein the sidewall portion is thinner than the bottom portion.
摘要翻译：一种方法包括提供具有栅极沟槽的半导体衬底，并且使用物理气相沉积（PVD）工艺在衬底上沉积金属层以部分地填充沟槽。金属层包括比底部更薄的底部部分和侧壁部分。所述方法还包括在所述金属层上形成涂层，使所述涂层回蚀刻，使得所述涂层的一部分保护所述沟槽内的所述金属层的一部分，以及去除所述金属层的未被保护的部分。不同的方面涉及一种半导体器件，其包括包括具有顶表面的沟槽的栅极和在沟槽上形成的金属层，其中金属层包括侧壁部分和底部，并且其中侧壁部分比底部。

5. 发明授权

US08962477B2 High temperature anneal for stress modulation 有权
标题翻译：高温退火应力调制
公开(公告)号：US08962477B2
公开(公告)日：2015-02-24
申请号：US13208435
申请日：2011-08-12
申请人： Meng-Hsuan Chan , Wei-Yang Lee , Da-Yuan Lee , Kuang-Yuan Hsu
发明人： Meng-Hsuan Chan , Wei-Yang Lee , Da-Yuan Lee , Kuang-Yuan Hsu
IPC分类号： H01L21/44 , H01L21/28 , H01L29/49 , H01L29/66 , H01L29/78
CPC分类号： H01L21/28088 , H01L29/4966 , H01L29/66545 , H01L29/78 , H01L29/7845
摘要： A method for modulating stress in films formed in semiconductor device manufacturing provides for high temperature annealing of an as-deposited compressive film such as titanium nitride. The high temperature annealing converts the initially compressive film to a tensile film without compromising other film qualities and characteristics. The converted tensile films are particularly advantageous as work function adjusting films in PMOS transistor devices and are advantageously used in conjunction with additional metal gate materials.
摘要翻译：用于调制在半导体器件制造中形成的膜中的应力的方法提供了诸如氮化钛的沉积压缩膜的高温退火。高温退火将初始压缩膜转化为拉伸膜，而不损害其它膜的质量和特性。转换的拉伸薄膜作为PMOS晶体管器件中的功函数调节膜是特别有利的，并且有利地与额外的金属栅极材料结合使用。

6. 发明授权

US08530294B2 Stress modulation for metal gate semiconductor device 有权
标题翻译：金属栅半导体器件的应力调制
公开(公告)号：US08530294B2
公开(公告)日：2013-09-10
申请号：US13278725
申请日：2011-10-21
申请人： Wei-Yang Lee , Meng-Hsuan Chan , Huang Ching Yu , Da-Yuan Lee , Kuang-Yuan Hsu
发明人： Wei-Yang Lee , Meng-Hsuan Chan , Huang Ching Yu , Da-Yuan Lee , Kuang-Yuan Hsu
IPC分类号： H01L21/8238
CPC分类号： H01L21/265 , H01L21/28088 , H01L21/823807 , H01L21/823842 , H01L29/513 , H01L29/66545 , H01L29/78 , H01L29/7843 , H01L29/7845
摘要： The present disclosure provides a method of semiconductor device fabrication including removing a sacrificial gate structure formed on a substrate to provide an opening. A metal gate structure is then formed in the opening. The forming of the metal gate structure includes forming a first layer (including metal) on a gate dielectric layer, wherein the first layer includes a metal and performing a stress modulation process on the first layer. The stress modulation process may include ion implantation of a neutral species such as silicon, argon, germanium, and xenon.
摘要翻译：本公开提供了一种半导体器件制造方法，包括去除形成在衬底上的牺牲栅极结构以提供开口。然后在开口中形成金属栅极结构。金属栅极结构的形成包括在栅极介电层上形成第一层（包括金属），其中第一层包括金属并在第一层上执行应力调制过程。应力调制过程可以包括中性物质如硅，氩，锗和氙的离子注入。

7. 发明申请

US20130102142A1 STRESS MODULATION FOR METAL GATE SEMICONDUCTOR DEVICE 有权
标题翻译：金属栅极半导体器件的应力调制
公开(公告)号：US20130102142A1
公开(公告)日：2013-04-25
申请号：US13278725
申请日：2011-10-21
申请人： Wei-Yang Lee , Meng-Hsuan Chan , Huang Ching Yu , Da-Yuan Lee , Kuang-Yuan Hsu
发明人： Wei-Yang Lee , Meng-Hsuan Chan , Huang Ching Yu , Da-Yuan Lee , Kuang-Yuan Hsu
IPC分类号： H01L21/28
CPC分类号： H01L21/265 , H01L21/28088 , H01L21/823807 , H01L21/823842 , H01L29/513 , H01L29/66545 , H01L29/78 , H01L29/7843 , H01L29/7845
摘要： The present disclosure provides a method of semiconductor device fabrication including removing a sacrificial gate structure formed on a substrate to provide an opening. A metal gate structure is then formed in the opening. The forming of the metal gate structure includes forming a first layer (including metal) on a gate dielectric layer, wherein the first layer includes a metal and performing a stress modulation process on the first layer. The stress modulation process may include ion implantation of a neutral species such as silicon, argon, germanium, and xenon.
摘要翻译：本公开提供了一种半导体器件制造方法，包括去除形成在衬底上的牺牲栅极结构以提供开口。然后在开口中形成金属栅极结构。金属栅极结构的形成包括在栅极介电层上形成第一层（包括金属），其中第一层包括金属并在第一层上执行应力调制过程。应力调制过程可以包括中性物质如硅，氩，锗和氙的离子注入。

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