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1. 发明授权

US08389350B2 Semiconductor device and method for manufacturing the same in which variations are reduced and characteristics are improved 失效
标题翻译：半导体器件及其制造方法，其中减小了变化并提高了特性
公开(公告)号：US08389350B2
公开(公告)日：2013-03-05
申请号：US13178248
申请日：2011-07-07
申请人： Akihito Sakakidani , Kiyotaka Imai
发明人： Akihito Sakakidani , Kiyotaka Imai
IPC分类号： H01L21/336
CPC分类号： H01L29/7833 , H01L21/26506 , H01L21/26513 , H01L21/28202 , H01L21/28229 , H01L29/1045 , H01L29/105 , H01L29/1083 , H01L29/518 , H01L29/66537 , H01L29/6659
摘要： A method of manufacturing N-type MOSFET includes: implanting a p-type dopant into in a surface layer of a semiconductor substrate to form a channel region; forming a gate insulating film including High-k material and a gate electrode on said channel region; implanting a p-type dopant into both ends of said channel region in an inner portion of said semiconductor substrate to form halo regions; implanting a p-type dopant into both ends of said channel region in a surface layer of said semiconductor substrate to form extension regions. One of said step of forming said channel region and said step of forming halo regions includes: implanting C into one of said channel region and said halo regions. An inclusion amount of said High-k material is an amount that increase of a threshold voltage caused by said High-k material being included in said gate insulating film compensates for decrease of said threshold voltage caused by said C being implanted.
摘要翻译：一种制造N型MOSFET的方法包括：将p型掺杂剂注入到半导体衬底的表面层中以形成沟道区; 在所述沟道区上形成包括High-k材料和栅电极的栅极绝缘膜; 在所述半导体衬底的内部部分中将p型掺杂剂注入所述沟道区的两端以形成晕圈; 在所述半导体衬底的表面层中将p型掺杂剂注入所述沟道区的两端以形成扩展区。形成所述通道区域和所述形成晕圈区的步骤的所述步骤之一包括：将C注入所述通道区域和所述晕区域之一。所述High-k材料的包含量是由包括在所述栅极绝缘膜中的所述High-k材料引起的阈值电压的增加补偿由所述C植入引起的所述阈值电压的降低。

2. 发明申请

US20100117156A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件及制造半导体器件的方法
公开(公告)号：US20100117156A1
公开(公告)日：2010-05-13
申请号：US12617434
申请日：2009-11-12
申请人： Gen TSUTSUI , Kiyotaka IMAI
发明人： Gen TSUTSUI , Kiyotaka IMAI
IPC分类号： H01L27/088 , H01L21/8234
CPC分类号： H01L27/088 , H01L21/823418 , H01L21/823431 , H01L21/823437 , H01L21/823475 , H01L29/785
摘要： A semiconductor device includes a first transistor, a second transistor, a first interconnect, a second interconnect, and a first gate electrode. The first gate electrode is a gate electrode of the first and second transistors and extends linearly over first and second channel regions. In addition, a first source of the first transistor is located at the opposite side of a second source of the second transistor with the first gate electrode interposed therebetween, and a first drain of the first transistor is located at the opposite side of a second drain of the second transistor with the first gate electrode interposed therebetween.
摘要翻译：半导体器件包括第一晶体管，第二晶体管，第一互连，第二互连和第一栅电极。第一栅电极是第一和第二晶体管的栅电极，并且在第一和第二沟道区上线性延伸。此外，第一晶体管的第一源位于第二晶体管的第二源极的相反侧，第一栅电极介于其间，第一晶体管的第一漏极位于第二漏极的相对侧的第二晶体管，其间插入有第一栅电极。

3. 发明申请

US20080093699A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20080093699A1
公开(公告)日：2008-04-24
申请号：US11874221
申请日：2007-10-18
申请人： Tomohisa ABE , Gen Tsutsui , Tadashi Fukase , Yasushi Nakahara , Kiyotaka Imai
发明人： Tomohisa ABE , Gen Tsutsui , Tadashi Fukase , Yasushi Nakahara , Kiyotaka Imai
IPC分类号： H01L29/00
CPC分类号： H01L21/2652 , H01L21/82385 , H01L27/0207 , H01L27/105 , H01L27/11 , H01L27/1116 , H01L29/105
摘要： The semiconductor device includes a plurality of transistors at least having different channel widths from each other. Threshold voltages of those transistors are set to be substantially equal to each other, by using both of substantially the same channel dose for each of those transistors, and work function control using a predetermined metal to be deposited on a gate insulating of those transistors and/or a gate electrode material of each of those transistors (that is, work function control based on a gate structure (gate insulating film and/or gate electrode) with respect to a channel region of each of those transistors).
摘要翻译：半导体器件包括至少具有彼此不同沟道宽度的多个晶体管。这些晶体管的阈值电压通过使用这些晶体管中的每一个的基本上相同的通道剂量和使用要沉积在那些晶体管的栅极绝缘上的预定金属的功函数控制来设置为彼此基本相等，和/ 或这些晶体管中的每一个的栅极电极材料（即，相对于这些晶体管的沟道区域，基于栅极结构（栅极绝缘膜和/或栅电极）的功函数控制）。

4. 发明授权

US07102183B2 MOS transistor 失效
标题翻译： MOS晶体管
公开(公告)号：US07102183B2
公开(公告)日：2006-09-05
申请号：US11001310
申请日：2004-12-02
申请人： Naohiko Kimizuka , Kiyotaka Imai , Yuri Masuoka
发明人： Naohiko Kimizuka , Kiyotaka Imai , Yuri Masuoka
IPC分类号： H01L29/78 , H01L27/108 , H01L21/336
CPC分类号： H01L29/7838 , H01L21/823807
摘要： In P-channel MOS transistor comprising a gate insulating film composed of a high dielectric constant material and the gate electrode composed of polycrystalline silicon, a technology for preventing Fermi level pinning and providing a stable reduction of the threshold voltage is provided. The MOS transistor functions as a buried channel transistor formed by implanting In as a P-type impurity into the channel region. In addition, the gate electrode is composed of the polycrystalline silicon film, which is doped with N-type impurity. Thus, the gate depletion caused by Fermi level pinning can be effectively inhibited. Therefore the depletion in the gate electrode can be avoided and the threshold voltage can be stably diminished. In this case, the threshold voltage is stably reduced since electric charge is induced by applying a constant voltage to the gate electrode.
摘要翻译：在包括由高介电常数材料构成的栅极绝缘膜和由多晶硅构成的栅电极的P沟道MOS晶体管中，提供了用于防止费米能级钉扎并提供阈值电压的稳定降低的技术。 MOS晶体管用作通过将In作为P型杂质注入沟道区而形成的埋入沟道晶体管。此外，栅电极由掺杂有N型杂质的多晶硅膜构成。因此，可以有效地抑制由费米能量钉扎引起的栅极耗尽。因此，能够避免栅电极的耗尽，能够稳定地降低阈值电压。在这种情况下，由于通过向栅电极施加恒定电压而引起电荷，所以阈值电压稳定地降低。

5. 发明申请

US20050263802A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20050263802A1
公开(公告)日：2005-12-01
申请号：US11129439
申请日：2005-05-16
申请人： Naohiko Kimizuka , Kiyotaka Imai , Yuri Masuoka , Toshiyuki Iwamoto , Motofumi Saitoh , Hirohito Watanabe , Ayuka Tada
发明人： Naohiko Kimizuka , Kiyotaka Imai , Yuri Masuoka , Toshiyuki Iwamoto , Motofumi Saitoh , Hirohito Watanabe , Ayuka Tada
IPC分类号： H01L27/092 , H01L21/28 , H01L21/3115 , H01L21/336 , H01L21/8238 , H01L29/51 , H01L29/76 , H01L29/78
CPC分类号： H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L21/31155 , H01L21/823857 , H01L29/513 , H01L29/517
摘要： A semiconductor device 100 comprises a silicon substrate 102, an N-type MOSFET 118 including a high concentration-high dielectric constant film 108b formed on the silicon substrate 102 and a polycrystalline silicon film 114, and a P-type MOSFET 120 including a low concentration-high dielectric constant film 108a and a polycrystalline silicon film 114 formed on the semiconductor substrate 102 to be juxtaposed to the N-type MOSFET 118. The low concentration-high dielectric constant film 108a and the high concentration-high dielectric constant film 108b are composed of a material containing one or more element (s) selected from a group consisting of Hf and Zr. The concentration of the above-described metallic element contained in the low concentration-high dielectric constant film 108a is lower than that contained in the high concentration-high dielectric constant film 108b.
摘要翻译：半导体器件100包括硅衬底102，包括形成在硅衬底102上的高浓度 - 高介电常数膜108b和多晶硅膜114的N型MOSFET 118以及包括低电平的P型MOSFET 120 浓度高介电常数膜108a和形成在半导体衬底102上并与N型MOSFET 118并置的多晶硅膜114。低浓度 - 高介电常数膜108a和高浓度 - 高介电常数膜108b由含有选自Hf和Zr的一种或多种元素的材料构成。包含在低浓度 - 高介电常数膜108a中的上述金属元素的浓度低于高浓度 - 高介电常数膜108b中包含的金属元素的浓度。

6. 发明申请

US20050224857A1 MOS transistor 失效
标题翻译： MOS晶体管
公开(公告)号：US20050224857A1
公开(公告)日：2005-10-13
申请号：US11001310
申请日：2004-12-02
申请人： Naohiko Kimizuka , Kiyotaka Imai , Yuri Masuoka
发明人： Naohiko Kimizuka , Kiyotaka Imai , Yuri Masuoka
IPC分类号： H01L27/092 , H01L21/8238 , H01L29/78 , H01L31/062
CPC分类号： H01L29/7838 , H01L21/823807
摘要： In P-channel MOS transistor comprising a gate insulating film composed of a high dielectric constant material and the gate electrode composed of polycrystalline silicon, a technology for preventing Fermi level pinning and providing a stable reduction of the threshold voltage is provided. The MOS transistor functions as a buried channel transistor formed by implanting In as a P-type impurity into the channel region. In addition, the gate electrode is composed of the polycrystalline silicon film, which is doped with N-type impurity. Thus, the gate depletion caused by Fermi level pinning can be effectively inhibited. Therefore the depletion in the gate electrode can be avoided and the threshold voltage can be stably diminished. In this case, the threshold voltage is stably reduced since electric charge is induced by applying a constant voltage to the gate electrode.
摘要翻译：在包括由高介电常数材料构成的栅极绝缘膜和由多晶硅构成的栅电极的P沟道MOS晶体管中，提供了用于防止费米能级钉扎并提供阈值电压的稳定降低的技术。 MOS晶体管用作通过将In作为P型杂质注入沟道区而形成的埋入沟道晶体管。此外，栅电极由掺杂有N型杂质的多晶硅膜构成。因此，可以有效地抑制由费米能量钉扎引起的栅极耗尽。因此，能够避免栅电极的耗尽，能够稳定地降低阈值电压。在这种情况下，由于通过向栅电极施加恒定电压而引起电荷，所以阈值电压稳定地降低。

7. 发明授权

US06342413B1 Method of manufacturing semiconductor device 失效
公开(公告)号：US06342413B1
公开(公告)日：2002-01-29
申请号：US09693909
申请日：2000-10-23
申请人： Sadaaki Masuoka , Kiyotaka Imai
发明人： Sadaaki Masuoka , Kiyotaka Imai
IPC分类号： H01L21336
CPC分类号： H01L21/26513 , H01L21/2658 , H01L21/823412
摘要： In a method of manufacturing a semiconductor device having first through third MOS transistors, using a first mask (311), wells (313, 314) and first threshold adjustment regions (315, 316) are formed at transistor areas (306n, 308n) for the second and the third MOS transistors in a semiconductor substrate (301). Next, using a second mask (319), second threshold adjustment regions (320, 321) are formed at transistor areas (304n and 308n) for the first and the third MOS transistors. In the transistor area for the third MOS transistor, both of the first threshold adjustment region and the second threshold adjustment region form a third adjustment region. Thus, using the two masks, three thresholds of the MOS transistors are obtained.

8. 发明授权

US06337248B1 Process for manufacturing semiconductor devices 失效
标题翻译：制造半导体器件的工艺
公开(公告)号：US06337248B1
公开(公告)日：2002-01-08
申请号：US09377047
申请日：1999-08-19
申请人： Kiyotaka Imai
发明人： Kiyotaka Imai
IPC分类号： H01L21336
CPC分类号： H01L21/823842 , H01L29/7838
摘要： Manufactured is a semiconductor device that has a substrate and a surface channel nMOS and a buried channel nMOS as well as a surface channel pMOS and a buried channel pMOS formed on the substrate. An n+ dopant is introduced prior to pattering a polycrystalline semiconductor layer that forms respective gate electrodes of the surface channel nMOS and the buried channel pMOS. A p+ dopant is also introduced prior to pattering a polycrystalline semiconductor layer that forms respective gate electrodes of the surface channel pMOS and the buried channel nMOS.
摘要翻译：制造的半导体器件具有衬底和表面沟道nMOS和掩埋沟道nMOS以及在衬底上形成的表面沟道pMOS和掩埋沟道pMOS。在形成形成表面沟道nMOS和掩埋沟道pMOS的相应栅电极的多晶半导体层之前，引入n +掺杂剂。在图形形成表面沟道pMOS和掩埋沟道nMOS的相应栅电极的多晶半导体层之前，还引入p +掺杂剂。

9. 发明授权

US06194261B1 High yield semiconductor device and method of fabricating the same 有权
标题翻译：高收率半导体器件及其制造方法
公开(公告)号：US06194261B1
公开(公告)日：2001-02-27
申请号：US09255695
申请日：1999-02-23
申请人： Kiyotaka Imai
发明人： Kiyotaka Imai
IPC分类号： H01L218234
CPC分类号： H01L27/1104 , H01L21/76897
摘要： A unit cell of a static random-access memory includes a laminated gate electrode structure adjacent to a diffusion layer. A top surface of the gate electrode structure is coated with a first silicide layer and the diffusion layer includes a second silicide layer. The second silicide layer is separated from the gate electrode structure by a distance that is the same as a width of a sidewall spacer on an opposite side of the gate electrode structure. The portion of the diffusion layer that is exposed between the second silicide layer and the gate electrode structure has a higher impurity concentration than the remainder of the diffusion layer to reduce or eliminate undesired leakage voltage.
摘要翻译：静态随机存取存储器的单位单元包括与扩散层相邻的叠层栅电极结构。栅电极结构的顶表面涂覆有第一硅化物层，扩散层包括第二硅化物层。第二硅化物层与栅电极结构隔开与栅电极结构的相对侧上的侧壁间隔物的宽度相同的距离。暴露在第二硅化物层和栅电极结构之间的扩散层的部分具有比扩散层的其余部分更高的杂质浓度，以减少或消除不期望的泄漏电压。

10. 发明授权

US6031271A High yield semiconductor device and method of fabricating the same 有权
标题翻译：高收率半导体器件及其制造方法
公开(公告)号：US6031271A
公开(公告)日：2000-02-29
申请号：US188378
申请日：1998-11-10
申请人： Kiyotaka Imai
发明人： Kiyotaka Imai
IPC分类号： H01L21/28 , H01L21/768 , H01L21/8244 , H01L27/11 , H01L29/78 , H01L29/76
CPC分类号： H01L27/1104 , H01L21/76897
摘要： A unit cell of a static random-access memory includes a laminated gate electrode structure adjacent to a diffusion layer. A top surface of the gate electrode structure is coated with a first silicide layer and the diffusion layer includes a second silicide layer. The second silicide layer is separated from the gate electrode structure by a distance that is the same as a width of a sidewall spacer on an opposite side of the gate electrode structure. The portion of the diffusion layer that is exposed between the second silicide layer and the gate electrode structure has a higher impurity concentration than the remainder of the diffusion layer to reduce or eliminate undesired leakage voltage.
摘要翻译：静态随机存取存储器的单位单元包括与扩散层相邻的叠层栅电极结构。栅电极结构的顶表面涂覆有第一硅化物层，扩散层包括第二硅化物层。第二硅化物层与栅电极结构隔开与栅电极结构的相对侧上的侧壁间隔物的宽度相同的距离。暴露在第二硅化物层和栅电极结构之间的扩散层的部分具有比扩散层的其余部分更高的杂质浓度，以减少或消除不期望的泄漏电压。

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