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1. 发明申请

US20100117156A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件及制造半导体器件的方法
公开(公告)号：US20100117156A1
公开(公告)日：2010-05-13
申请号：US12617434
申请日：2009-11-12
申请人： Gen TSUTSUI , Kiyotaka IMAI
发明人： Gen TSUTSUI , Kiyotaka IMAI
IPC分类号： H01L27/088 , H01L21/8234
CPC分类号： H01L27/088 , H01L21/823418 , H01L21/823431 , H01L21/823437 , H01L21/823475 , H01L29/785
摘要： A semiconductor device includes a first transistor, a second transistor, a first interconnect, a second interconnect, and a first gate electrode. The first gate electrode is a gate electrode of the first and second transistors and extends linearly over first and second channel regions. In addition, a first source of the first transistor is located at the opposite side of a second source of the second transistor with the first gate electrode interposed therebetween, and a first drain of the first transistor is located at the opposite side of a second drain of the second transistor with the first gate electrode interposed therebetween.
摘要翻译：半导体器件包括第一晶体管，第二晶体管，第一互连，第二互连和第一栅电极。第一栅电极是第一和第二晶体管的栅电极，并且在第一和第二沟道区上线性延伸。此外，第一晶体管的第一源位于第二晶体管的第二源极的相反侧，第一栅电极介于其间，第一晶体管的第一漏极位于第二漏极的相对侧的第二晶体管，其间插入有第一栅电极。

2. 发明申请

US20100224914A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：US20100224914A1
公开(公告)日：2010-09-09
申请号：US12715712
申请日：2010-03-02
申请人： Toshiyuki IWAMOTO , Gen TSUTSUI , Kiyotaka IMAI
发明人： Toshiyuki IWAMOTO , Gen TSUTSUI , Kiyotaka IMAI
IPC分类号： H01L29/04
CPC分类号： H01L21/823431 , H01L21/823456 , H01L29/045 , H01L29/785
摘要： Provided is a semiconductor device including: a first n-channel fin-type field effect transistor formed on a first crystal plane; and a second n-channel fin-type field effect transistor formed on the first crystal plane and having a gate length longer than that of the first n-channel fin-type field effect transistor. A side surface of a fin of the first n-channel fin-type field effect transistor and a side surface of a fin of the second n-channel fin-type field effect transistor are both formed on a second crystal plane having a carrier mobility lower than that of the first crystal plane. The width of the fin of the second n-channel fin-type field effect transistor is greater than the width of the fin of the first n-channel fin-type field effect transistor.
摘要翻译：提供一种半导体器件，包括：形成在第一晶体平面上的第一n沟道鳍式场效应晶体管; 以及形成在所述第一晶面上并且具有比所述第一n沟道鳍型场效应晶体管的栅长长的栅极长度的第二n沟道鳍型场效应晶体管。第一n沟道鳍式场效应晶体管的鳍的侧表面和第二n沟道鳍型场效应晶体管的鳍的侧表面都形成在具有载流子迁移率较低的第二晶面上比第一个水晶面。第二n沟道鳍式场效应晶体管的鳍的宽度大于第一n沟道鳍式场效应晶体管的鳍的宽度。

3. 发明申请

US20120007194A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME IN WHICH VARIATIONS ARE REDUCED AND CHARACTERISTICS ARE IMPROVED 失效
标题翻译：半导体器件及其制造方法，其中变化减少和特性得到改善
公开(公告)号：US20120007194A1
公开(公告)日：2012-01-12
申请号：US13178248
申请日：2011-07-07
申请人： Akihito SAKAKIDANI , Kiyotaka IMAI
发明人： Akihito SAKAKIDANI , Kiyotaka IMAI
IPC分类号： H01L29/772 , H01L21/336
CPC分类号： H01L29/7833 , H01L21/26506 , H01L21/26513 , H01L21/28202 , H01L21/28229 , H01L29/1045 , H01L29/105 , H01L29/1083 , H01L29/518 , H01L29/66537 , H01L29/6659
摘要： A method of manufacturing N-type MOSFET includes: implanting a p-type dopant into in a surface layer of a semiconductor substrate to form a channel region; forming a gate insulating film including High-k material and a gate electrode on said channel region; implanting a p-type dopant into both ends of said channel region in an inner portion of said semiconductor substrate to form halo regions; implanting a p-type dopant into both ends of said channel region in a surface layer of said semiconductor substrate to form extension regions. One of said step of forming said channel region and said step of forming halo regions includes: implanting C into one of said channel region and said halo regions. An inclusion amount of said High-k material is an amount that increase of a threshold voltage caused by said High-k material being included in said gate insulating film compensates for decrease of said threshold voltage caused by said C being implanted.
摘要翻译：一种制造N型MOSFET的方法包括：将p型掺杂剂注入到半导体衬底的表面层中以形成沟道区; 在所述沟道区上形成包括High-k材料和栅电极的栅极绝缘膜; 在所述半导体衬底的内部部分中将p型掺杂剂注入所述沟道区的两端以形成晕圈; 在所述半导体衬底的表面层中将p型掺杂剂注入所述沟道区的两端以形成扩展区。形成所述通道区域和所述形成晕圈区的步骤的所述步骤之一包括：将C注入所述通道区域和所述晕区域之一。所述High-k材料的包含量是由包括在所述栅极绝缘膜中的所述High-k材料引起的阈值电压的增加补偿由所述C植入引起的所述阈值电压的降低。

4. 发明申请

US20150118817A1 SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20150118817A1
公开(公告)日：2015-04-30
申请号：US14285649
申请日：2014-05-23
申请人： Kiyotaka IMAI , Young-Gwon KIM , Shigenobu MAEDA , Soon-Chul HWANG
发明人： Kiyotaka IMAI , Young-Gwon KIM , Shigenobu MAEDA , Soon-Chul HWANG
IPC分类号： H01L29/66 , H01L21/266 , H01L21/02
CPC分类号： H01L29/66545 , H01L21/02667 , H01L21/266 , H01L21/823418 , H01L29/7833
摘要： A method for fabricating a semiconductor device is provided, which includes forming a screen layer on a substrate, the screen layer including a first portion doped with a first type impurity, forming a first undoped semiconductor layer on the screen layer, forming a gate structure on the first semiconductor layer, forming a first amorphous region on both sides of the gate structure in the first semiconductor layer, and re-crystallizing the first amorphous region through performing a first heat treatment of the first amorphous region.
摘要翻译：提供一种制造半导体器件的方法，其包括在衬底上形成屏幕层，所述屏幕层包括掺杂有第一类型杂质的第一部分，在所述屏幕层上形成第一未掺杂半导体层，形成栅极结构第一半导体层，在第一半导体层中的栅极结构的两侧上形成第一非晶区，并且通过进行第一非晶区的第一热处理，使第一非晶区再结晶。

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