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    • 4. 发明授权
    • MOS transistor
    • MOS晶体管
    • US07102183B2
    • 2006-09-05
    • US11001310
    • 2004-12-02
    • Naohiko KimizukaKiyotaka ImaiYuri Masuoka
    • Naohiko KimizukaKiyotaka ImaiYuri Masuoka
    • H01L29/78H01L27/108H01L21/336
    • H01L29/7838H01L21/823807
    • In P-channel MOS transistor comprising a gate insulating film composed of a high dielectric constant material and the gate electrode composed of polycrystalline silicon, a technology for preventing Fermi level pinning and providing a stable reduction of the threshold voltage is provided. The MOS transistor functions as a buried channel transistor formed by implanting In as a P-type impurity into the channel region. In addition, the gate electrode is composed of the polycrystalline silicon film, which is doped with N-type impurity. Thus, the gate depletion caused by Fermi level pinning can be effectively inhibited. Therefore the depletion in the gate electrode can be avoided and the threshold voltage can be stably diminished. In this case, the threshold voltage is stably reduced since electric charge is induced by applying a constant voltage to the gate electrode.
    • 在包括由高介电常数材料构成的栅极绝缘膜和由多晶硅构成的栅电极的P沟道MOS晶体管中,提供了用于防止费米能级钉扎并提供阈值电压的稳定降低的技术。 MOS晶体管用作通过将In作为P型杂质注入沟道区而形成的埋入沟道晶体管。 此外,栅电极由掺杂有N型杂质的多晶硅膜构成。 因此,可以有效地抑制由费米能量钉扎引起的栅极耗尽。 因此,能够避免栅电极的耗尽,能够稳定地降低阈值电压。 在这种情况下,由于通过向栅电极施加恒定电压而引起电荷,所以阈值电压稳定地降低。
    • 6. 发明申请
    • MOS transistor
    • MOS晶体管
    • US20050224857A1
    • 2005-10-13
    • US11001310
    • 2004-12-02
    • Naohiko KimizukaKiyotaka ImaiYuri Masuoka
    • Naohiko KimizukaKiyotaka ImaiYuri Masuoka
    • H01L27/092H01L21/8238H01L29/78H01L31/062
    • H01L29/7838H01L21/823807
    • In P-channel MOS transistor comprising a gate insulating film composed of a high dielectric constant material and the gate electrode composed of polycrystalline silicon, a technology for preventing Fermi level pinning and providing a stable reduction of the threshold voltage is provided. The MOS transistor functions as a buried channel transistor formed by implanting In as a P-type impurity into the channel region. In addition, the gate electrode is composed of the polycrystalline silicon film, which is doped with N-type impurity. Thus, the gate depletion caused by Fermi level pinning can be effectively inhibited. Therefore the depletion in the gate electrode can be avoided and the threshold voltage can be stably diminished. In this case, the threshold voltage is stably reduced since electric charge is induced by applying a constant voltage to the gate electrode.
    • 在包括由高介电常数材料构成的栅极绝缘膜和由多晶硅构成的栅电极的P沟道MOS晶体管中,提供了用于防止费米能级钉扎并提供阈值电压的稳定降低的技术。 MOS晶体管用作通过将In作为P型杂质注入沟道区而形成的埋入沟道晶体管。 此外,栅电极由掺杂有N型杂质的多晶硅膜构成。 因此,可以有效地抑制由费米能量钉扎引起的栅极耗尽。 因此,能够避免栅电极的耗尽,能够稳定地降低阈值电压。 在这种情况下,由于通过向栅电极施加恒定电压而引起电荷,所以阈值电压稳定地降低。